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Code Activity
14797 commits 93 branches 53 tags 44 MiB
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2435 commits

Author SHA1 Message Date
chunlin min
19d3214861 use output reg instead of additional reg declaration 2024-07-04 14:13:26 -04:00
C77874
5ba06fd947 another typo 2024-07-04 10:33:59 -07:00
C77874
6b80e02d62 missed a few pf instances 2024-07-04 10:25:15 -07:00
C77874
c385421c17 rename options 2024-07-04 09:45:04 -07:00
C77874
d0cd01adfe fixed typos, build with makefile succeeds 2024-07-04 09:33:58 -07:00
C77874
59e45be275 Merge branch 'mchp' of https://github.com/tony-min-1/yosys into change_filenames 2024-07-04 09:00:38 -07:00
C77874
0bb7d1373f changes made to filenames + references 2024-07-04 08:53:41 -07:00
Chun Lin Min
7770fa70e1 fix cells_sim.v 2024-07-04 05:20:22 -07:00
Chun Lin Min
f57b624281 fix indent 2024-07-02 13:54:36 -07:00
Chun Lin Min
68a11c9941 more indent fix 2024-07-02 13:51:48 -07:00
Chun Lin Min
2ced2752e9 replace space indent with tab indent 2024-07-02 13:47:18 -07:00
Chun Lin Min
acddc36389 add PolarFire FPGA support 2024-07-02 12:44:30 -07:00
Lofty
8cc9aa7fc6 intel_alm: drop quartus support 2024-05-03 11:32:33 +01:00
KrystalDelusion
c3ae33da33
Merge pull request #4285 from YosysHQ/typo_fixup 
Typo fixing
 2024-04-25 09:54:48 +12:00
Martin Povišer
dc746080f5
Merge pull request #4298 from povik/kogge-stone 
techmap: Add a Kogge-Stone option for `$lcu` mapping
 2024-04-08 16:46:06 +02:00
Martin Povišer
5f4d13ee3f techmap: Note down iteration in Kogge-Stone 2024-04-08 16:45:40 +02:00
N. Engelhardt
8e8885e1cc
Merge pull request #4323 from YosysHQ/tests_update 
Tests update for latest more strict iverilog
 2024-04-08 15:10:59 +02:00
Miodrag Milanovic
4ac10040ce Enable SV for localparam use by Efinix cell_sim 2024-04-08 12:45:43 +02:00
Emil J. Tywoniak
9510293a94 fixup 2024-04-04 18:16:58 +02:00
Emil J. Tywoniak
a580a7c82c docs: Document $macc 2024-04-03 20:37:54 +02:00
Martin Povišer
bc087f91ed techmap: Fix using overwritten results in Kogge-Stone 2024-03-27 18:32:25 +01:00
Martin Povišer
4570d064e5 techmap: Split out Kogge-Stone into a separate file 2024-03-27 11:07:24 +01:00
Martin Povišer
c38201e15d techmap: Add a Kogge-Stone option for $lcu mapping 2024-03-25 14:56:17 +01:00
Richard Herveille
2893938355 Removed SystemVerilog module end label 2024-03-19 01:31:36 +01:00
Krystine Sherwin
ff10aeebd6
Fix some synth_* help messages 
Mostly memory_libmap arg checks; puts the checks into an else block on the `if (help_mode)` check to avoid cases like `synth_ice40` listing `-no-auto-huge [-no-auto-huge]`.
Also fix `map_iopad` section being empty in `synth_fabulous`.
 2024-03-18 11:33:18 +13:00
Richard Herveille
7647eb70a6 removed commented out code 2024-03-15 01:48:22 +01:00
Richard Herveille
2d11c5e2f8 removed comment 2024-03-15 01:48:06 +01:00
Martin Povišer
570a8f12b5
synth: Fix out-of-sync help message 
Co-authored-by: N. Engelhardt <nakengelhardt@gmail.com>
 2024-03-06 14:55:43 +01:00
Richard Herveille
1723aa251a Added DSP support and updates for performance 2024-03-06 02:45:40 +01:00
Richard Herveille
58b1522a20 Added DSP macros 2024-03-06 02:45:29 +01:00
Richard Herveille
2fde482629 Fixed data/address width parameters 2024-03-06 02:45:07 +01:00
Richard Herveille
b16cdaab35 dsp_map for MAX10 2024-03-06 02:43:30 +01:00
Martin Povišer
d2a7ce04ea synth: Rename -inject to -extra-map 2024-03-01 10:54:51 +01:00
Martin Povišer
ba07cba6ce synth: Introduce -inject for amending techmap 2024-02-22 17:38:48 +01:00
Martin Povišer
d77b792156 synth: Put in missing bounds check for -lut 2024-02-22 17:24:26 +01:00
Miodrag Milanović
edb95c69a9
Merge pull request #4084 from jix/scopeinfo 
$scopeinfo support
 2024-02-12 09:51:22 +01:00
Martin Povišer
7a3316dd78 synth: Tweak phrasing of -booth help 2024-02-08 00:05:15 +01:00
Martin Povišer
a98d363d9d synth: Run script in full in help mode 2024-02-08 00:05:15 +01:00
Jannis Harder
f728927307 Add builtin celltype $scopeinfo 
Only declares the cell interface, doesn't make anything use or
understand $scopeinfo yet.
 2024-02-06 17:51:24 +01:00
Catherine
c7bf0e3b8f Add new $check cell to represent assertions with a message. 2024-02-01 20:10:39 +01:00
YRabbit
79c5a06673 gowin: Fix SDP write enable port. 
This primitive does not have a separate WRE port, so we regulate writing
using Clock Enable.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2024-01-30 17:06:59 +10:00
YRabbit
a5fdf3f881 gowin: Change BYTE ENABLE handling. 
When inferring we allow writing to all bytes for now.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2024-01-27 17:19:49 +10:00
YRabbit
ae991abf2e gowin: fix the BRAM mapping. 
The primitives used have been corrected and changes have been made to the set of signals.
The empirically established need to set the OCEx signal to 1 when using READ_MODE=0 is reflected.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2024-01-19 15:26:37 +10:00
Martin Povišer
568418b50b opt_lut: Replace -dlogic with -tech ice40 2024-01-15 12:35:21 +01:00
Miodrag Milanovic
627fbc3477 Fix Windows build by forcing initialization order, fixes #4068 2024-01-02 11:26:48 +01:00
Miodrag Milanović
86b8a1c5ae
Merge pull request #4087 from povik/lattice-dp8kc-fix 
lattice: Fix mapping onto DP8KC for data width 1 or 2
 2023-12-21 11:46:11 +01:00
Martin Povišer
c028f25158 lattice: Disable broken port configuration in bram inference 2023-12-21 10:47:40 +01:00
Martin Povišer
fc5c5172f8 lattice: Fix mapping onto DP8KC for data width 1 or 2 2023-12-20 23:42:12 +01:00
Miodrag Milanović
a4ad7cb81a
Merge pull request #4049 from pepijndevos/patch-3 
Enable bram for Gowin
 2023-12-19 08:16:54 +01:00
N. Engelhardt
d87bd7ca3f
Merge pull request #3887 from kivikakk/env-bash 
tests: use /usr/bin/env for bash.
 2023-12-18 16:33:35 +01:00