changes made to filenames + references

techlibs/microchip/Makefile.inc

@@ -16,16 +16,16 @@
 
 
 
-OBJS += techlibs/mchp/synth_mchp.o
-OBJS += techlibs/mchp/mchp_dffopt.o
+OBJS += techlibs/microchip/synth_microchip.o
+OBJS += techlibs/microchip/microchip_dffopt.o
 
-$(eval $(call add_share_file,share/mchp,techlibs/mchp/arith_map.v))
-$(eval $(call add_share_file,share/mchp,techlibs/mchp/cells_map.v))
-$(eval $(call add_share_file,share/mchp,techlibs/mchp/cells_sim.v))
-$(eval $(call add_share_file,share/mchp,techlibs/mchp/pf_dsp_map.v))
+$(eval $(call add_share_file,share/microchip,techlibs/microchip/arith_map.v))
+$(eval $(call add_share_file,share/microchip,techlibs/microchip/cells_map.v))
+$(eval $(call add_share_file,share/microchip,techlibs/microchip/cells_sim.v))
+$(eval $(call add_share_file,share/microchip,techlibs/microchip/pf_dsp_map.v))
 
-$(eval $(call add_share_file,share/mchp,techlibs/mchp/brams_defs.vh))
-$(eval $(call add_share_file,share/mchp,techlibs/mchp/LSRAM_map.v))
-$(eval $(call add_share_file,share/mchp,techlibs/mchp/LSRAM.txt))
-$(eval $(call add_share_file,share/mchp,techlibs/mchp/uSRAM_map.v))
-$(eval $(call add_share_file,share/mchp,techlibs/mchp/uSRAM.txt))
+$(eval $(call add_share_file,share/microchip,techlibs/microchip/brams_defs.vh))
+$(eval $(call add_share_file,share/microchip,techlibs/microchip/LSRAM_map.v))
+$(eval $(call add_share_file,share/microchip,techlibs/microchip/LSRAM.txt))
+$(eval $(call add_share_file,share/microchip,techlibs/microchip/uSRAM_map.v))
+$(eval $(call add_share_file,share/microchip,techlibs/microchip/uSRAM.txt))

techlibs/microchip/arith_map.v

@@ -21,7 +21,7 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 
 
 (* techmap_celltype = "$_MUX4_" *)
-module \$__mchp_MUX4_ (A, B, C, D, S, T, Y);
+module \$__microchip_MUX4_ (A, B, C, D, S, T, Y);
 	input A, B, C, D, S, T;
 	output Y;
 	MX4 _TECHMAP_REPLACE_.MUX4(.D3(D), .D2(C), .D1(B), .D0(A), .S1(T), .S0(S), .Y(Y));
@@ -30,7 +30,7 @@ endmodule
 
 
 (* techmap_celltype = "$reduce_xor" *)
-module \$__mchp_XOR8_ (A, Y);
+module \$__microchip_XOR8_ (A, Y);
 	parameter A_SIGNED = 0;
 	parameter A_WIDTH = 0;
 	parameter Y_WIDTH = 0;

techlibs/microchip/cells_map.v

@@ -28,11 +28,11 @@ endmodule
 // for sync set/reset registers, we can pass them into ABC9. So we need to follow the simplification idiom
 // and map to intermediate cell types
 module \$_SDFFCE_PN0P_ (input D, C, R, E, output Q);
-	MCHP_SYNC_RESET_DFF _TECHMAP_REPLACE_ (.D(D), .CLK(C), .Reset(R), .En(E), .Q(Q));
+	MICROCHIP_SYNC_RESET_DFF _TECHMAP_REPLACE_ (.D(D), .CLK(C), .Reset(R), .En(E), .Q(Q));
 endmodule
 
 module \$_SDFFCE_PN1P_ (input D, C, R, E, output Q);
-	MCHP_SYNC_SET_DFF _TECHMAP_REPLACE_ (.D(D), .CLK(C), .Set(R), .En(E), .Q(Q));
+	MICROCHIP_SYNC_SET_DFF _TECHMAP_REPLACE_ (.D(D), .CLK(C), .Set(R), .En(E), .Q(Q));
 endmodule
 
 
@@ -52,7 +52,7 @@ endmodule
 
 // map intermediate flops to SLE
 `ifdef FINAL_MAP
-module MCHP_SYNC_SET_DFF(
+module MICROCHIP_SYNC_SET_DFF(
 	input D,
 	input CLK,
 	input Set,
@@ -61,7 +61,7 @@ module MCHP_SYNC_SET_DFF(
 	SLE _TECHMAP_REPLACE_ (.D(D), .CLK(CLK), .EN(En), .ALn(1'b1), .ADn(1'b0), .SLn(Set), .SD(1'b1), .LAT(1'b0), .Q(Q));
 endmodule
 
-module MCHP_SYNC_RESET_DFF(
+module MICROCHIP_SYNC_RESET_DFF(
 	input D,
 	input CLK,
 	input Reset,

techlibs/microchip/cells_sim.v

@@ -155,11 +155,11 @@ endmodule
 
 // sequential elements
 
-// MCHP_SYNC_SET_DFF and MCHP_SYNC_RESET_DFF are intermediate cell types to implement the simplification idiom for abc9 flow 
+// MICROCHIP_SYNC_SET_DFF and MICROCHIP_SYNC_RESET_DFF are intermediate cell types to implement the simplification idiom for abc9 flow 
 //	see: https://yosyshq.readthedocs.io/projects/yosys/en/latest/yosys_internals/extending_yosys/abc_flow.html
 
 (* abc9_flop, lib_whitebox *)
-module MCHP_SYNC_SET_DFF(
+module MICROCHIP_SYNC_SET_DFF(
 	input D,
 	input CLK,
 	input Set,
@@ -185,7 +185,7 @@ module MCHP_SYNC_SET_DFF(
 endmodule
 
 (* abc9_flop, lib_whitebox *)
-module MCHP_SYNC_RESET_DFF(
+module MICROCHIP_SYNC_RESET_DFF(
 	input D,
 	input CLK,
 	input Reset,

techlibs/microchip/microchip_dffopt.cc

@@ -16,8 +16,8 @@ ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */
 
-#include "kernel/yosys.h"
 #include "kernel/sigtools.h"
+#include "kernel/yosys.h"
 
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
@@ -25,7 +25,8 @@ PRIVATE_NAMESPACE_BEGIN
 typedef std::pair<Const, std::vector<SigBit>> LutData;
 
 // Compute a LUT implementing (select ^ select_inv) ? alt_data : data.  Returns true if successful.
-bool merge_lut(LutData &result, const LutData &data, const LutData select, bool select_inv, SigBit alt_data, int max_lut_size) {
+bool merge_lut(LutData &result, const LutData &data, const LutData select, bool select_inv, SigBit alt_data, int max_lut_size)
+{
 	// First, gather input signals -- insert new signals at the beginning
 	// of the vector, so they don't disturb the likely-critical D LUT input
 	// timings.
@@ -97,13 +98,13 @@ bool merge_lut(LutData &result, const LutData &data, const LutData select, bool
 	return true;
 }
 
-struct MchpDffOptPass : public Pass {
-	MchpDffOptPass() : Pass("mchp_dffopt", "MCHP: optimize FF control signal usage") { }
+struct MicrochipDffOptPass : public Pass {
+	MicrochipDffOptPass() : Pass("microchip_dffopt", "MICROCHIP: optimize FF control signal usage") {}
 	void help() override
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
-		log("    mchp_dffopt [options] [selection]\n");
+		log("    microchip_dffopt [options] [selection]\n");
 		log("\n");
 		log("Converts hardware clock enable and set/reset signals on FFs to emulation\n");
 		log("using LUTs, if doing so would improve area. Operates on post-techmap LUT, DFF\n");
@@ -112,15 +113,14 @@ struct MchpDffOptPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
-		log_header(design, "Executing MCHP_DFFOPT pass (optimize FF control signal usage).\n");
+		log_header(design, "Executing MICROCHIP_DFFOPT pass (optimize FF control signal usage).\n");
 
 		size_t argidx;
 		int max_lut_size = 4;
-		
+
 		extra_args(args, argidx, design);
 
-		for (auto module : design->selected_modules())
-		{
+		for (auto module : design->selected_modules()) {
 			log("Optimizing FFs in %s.\n", log_id(module));
 
 			SigMap sigmap(module);
@@ -128,8 +128,7 @@ struct MchpDffOptPass : public Pass {
 			dict<SigBit, int> bit_uses;
 
 			// Gather LUTs.
-			for (auto cell : module->selected_cells())
-			{
+			for (auto cell : module->selected_cells()) {
 				for (auto port : cell->connections())
 					for (auto bit : port.second)
 						bit_uses[sigmap(bit)]++;
@@ -153,8 +152,8 @@ struct MchpDffOptPass : public Pass {
 					if (cell->type == ID(CFG3))
 						goto lut_sigin_done;
 					sigin.push_back(sigmap(cell->getPort(ID(D))));
-					
-lut_sigin_done:
+
+				lut_sigin_done:
 					bit_to_lut[sigout] = make_pair(LutData(init, sigin), cell);
 				}
 			}
@@ -164,8 +163,7 @@ lut_sigin_done:
 						bit_uses[sigmap(SigBit(wire, i))]++;
 
 			// Iterate through FFs.
-			for (auto cell : module->selected_cells())
-			{
+			for (auto cell : module->selected_cells()) {
 
 				if (!cell->type.in(ID(SLE))) // not a SLE
 					continue;
@@ -174,13 +172,12 @@ lut_sigin_done:
 				if (cell->get_bool_attribute(ID::keep)) // keep attribute
 					continue;
 				if (!cell->getPort(ID(ALn)).is_fully_ones()) // async FF
-					continue; 
+					continue;
 
-					
 				const bool hasSyncLoad = cell->getPort(ID(SLn)).is_wire();
 				const bool has_s = hasSyncLoad && cell->getPort(ID(SD)).is_fully_ones();
 				const bool has_r = hasSyncLoad && cell->getPort(ID(SD)).is_fully_zero();
-				
+
 				// SLE cannot have both synchronous set and reset implemented at the same time
 				log_assert(!(has_s && has_r));
 
@@ -196,7 +193,6 @@ lut_sigin_done:
 				LutData lut_d = it_D->second.first;
 				Cell *cell_d = it_D->second.second;
 
-
 				LutData lut_d_post_ce;
 				LutData lut_d_post_s;
 				LutData lut_d_post_r;
@@ -216,7 +212,8 @@ lut_sigin_done:
 					if (!merge_lut(lut_d_post_ce, lut_d, lut_ce, true, sig_Q, max_lut_size))
 						continue;
 
-					// If this gets rid of a CE LUT, it's worth it.  If not, it still may be worth it, if we can remove set/reset as well.
+					// If this gets rid of a CE LUT, it's worth it.  If not, it still may be worth it, if we can remove set/reset
+					// as well.
 					if (it_CE != bit_to_lut.end())
 						worthy_post_ce = true;
 				} else if (sig_CE.data != State::S1) {
@@ -231,7 +228,7 @@ lut_sigin_done:
 				if (has_s) {
 					SigBit sig_S = sigmap(cell->getPort(ID(SLn)));
 					LutData lut_s = LutData(Const(2, 2), {sig_S}); // INIT = 10
-					bool inv_s = true; // active low
+					bool inv_s = true;			       // active low
 					auto it_S = bit_to_lut.find(sig_S);
 					if (it_S != bit_to_lut.end())
 						lut_s = it_S->second.first;
@@ -253,7 +250,7 @@ lut_sigin_done:
 				if (has_r) {
 					SigBit sig_R = sigmap(cell->getPort(ID(SLn)));
 					LutData lut_r = LutData(Const(2, 2), {sig_R}); // INIT = 10
-					bool inv_r = true; // active low
+					bool inv_r = true;			       // active low
 					auto it_R = bit_to_lut.find(sig_R);
 					if (it_R != bit_to_lut.end())
 						lut_r = it_R->second.first;
@@ -270,7 +267,7 @@ lut_sigin_done:
 					}
 				}
 
-unmap:
+			unmap:
 
 				// SLE cannot have both synchronous set and reset implemented at the same time
 				log_assert(!(worthy_post_r && worthy_post_s));
@@ -288,10 +285,14 @@ unmap:
 				}
 
 				std::string ports;
-				if (worthy_post_r) ports += " + R";
-				if (worthy_post_s) ports += " + S";
-				if (worthy_post_ce) ports += " + CE";
-				log("  Merging D%s LUTs for %s/%s (%d -> %d)\n", ports.c_str(), log_id(cell), log_id(sig_Q.wire), GetSize(lut_d.second), GetSize(final_lut.second));
+				if (worthy_post_r)
+					ports += " + R";
+				if (worthy_post_s)
+					ports += " + S";
+				if (worthy_post_ce)
+					ports += " + CE";
+				log("  Merging D%s LUTs for %s/%s (%d -> %d)\n", ports.c_str(), log_id(cell), log_id(sig_Q.wire),
+				    GetSize(lut_d.second), GetSize(final_lut.second));
 
 				// Okay, we're doing it.  Unmap ports.
 				if ((has_s && worthy_post_s) || worthy_post_r) {
@@ -304,20 +305,20 @@ unmap:
 				// Create the new LUT.
 				Cell *lut_cell = nullptr;
 				switch (GetSize(final_lut.second)) {
-					case 1:
-						lut_cell = module->addCell(NEW_ID, ID(CFG1));
-						break;
-					case 2:
-						lut_cell = module->addCell(NEW_ID, ID(CFG2));
-						break;
-					case 3:
-						lut_cell = module->addCell(NEW_ID, ID(CFG3));
-						break;
-					case 4:
-						lut_cell = module->addCell(NEW_ID, ID(CFG4));
-						break;
-					default:
-						log_assert(!"unknown lut size");
+				case 1:
+					lut_cell = module->addCell(NEW_ID, ID(CFG1));
+					break;
+				case 2:
+					lut_cell = module->addCell(NEW_ID, ID(CFG2));
+					break;
+				case 3:
+					lut_cell = module->addCell(NEW_ID, ID(CFG3));
+					break;
+				case 4:
+					lut_cell = module->addCell(NEW_ID, ID(CFG4));
+					break;
+				default:
+					log_assert(!"unknown lut size");
 				}
 				lut_cell->attributes = cell_d->attributes;
 				Wire *lut_out = module->addWire(NEW_ID);
@@ -334,7 +335,6 @@ unmap:
 			}
 		}
 	}
-} MchpDffOptPass;
+} MicrochipDffOptPass;
 
 PRIVATE_NAMESPACE_END
-

techlibs/microchip/synth_microchip.cc

@@ -16,23 +16,22 @@ ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */
 
-#include "kernel/register.h"
 #include "kernel/celltypes.h"
-#include "kernel/rtlil.h"
 #include "kernel/log.h"
+#include "kernel/register.h"
+#include "kernel/rtlil.h"
 
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-struct SynthMchpPass : public ScriptPass
-{
-	SynthMchpPass() : ScriptPass("synth_mchp", "synthesis for Microchip FPGAs") { }
+struct SynthMicrochipPass : public ScriptPass {
+	SynthMicrochipPass() : ScriptPass("synth_microchip", "synthesis for Microchip FPGAs") {}
 
 	void help() override
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
-		log("    synth_mchp [options]\n");
+		log("    synth_microchip [options]\n");
 		log("\n");
 		log("This command runs synthesis for Microchip FPGAs. Operating on\n");
 		log("partly selected designs is not supported (you must submit a fully-selected \n");
@@ -54,7 +53,7 @@ struct SynthMchpPass : public ScriptPass
 		log("\n");
 		log("    -blif <file>\n");
 		log("        Write the design to the specified BLIF file. Writing of an output file\n");
-		log("        is omitted if this parameter is not specified.\n");		
+		log("        is omitted if this parameter is not specified.\n");
 		log("\n");
 		log("    -nobram\n");
 		log("        Do not use block RAM cells in output netlist\n");
@@ -137,30 +136,29 @@ struct SynthMchpPass : public ScriptPass
 		clear_flags();
 
 		size_t argidx;
-		for (argidx = 1; argidx < args.size(); argidx++)
-		{
-			if (args[argidx] == "-top" && argidx+1 < args.size()) {
+		for (argidx = 1; argidx < args.size(); argidx++) {
+			if (args[argidx] == "-top" && argidx + 1 < args.size()) {
 				top_opt = "-top " + args[++argidx];
 				continue;
 			}
-			if ((args[argidx] == "-family" || args[argidx] == "-arch") && argidx+1 < args.size()) {
+			if ((args[argidx] == "-family" || args[argidx] == "-arch") && argidx + 1 < args.size()) {
 				family = args[++argidx];
 				continue;
 			}
-			if (args[argidx] == "-edif" && argidx+1 < args.size()) {
+			if (args[argidx] == "-edif" && argidx + 1 < args.size()) {
 				edif_file = args[++argidx];
 				continue;
 			}
-			if (args[argidx] == "-blif" && argidx+1 < args.size()) {
+			if (args[argidx] == "-blif" && argidx + 1 < args.size()) {
 				blif_file = args[++argidx];
 				continue;
 			}
-			if (args[argidx] == "-run" && argidx+1 < args.size()) {
-				size_t pos = args[argidx+1].find(':');
+			if (args[argidx] == "-run" && argidx + 1 < args.size()) {
+				size_t pos = args[argidx + 1].find(':');
 				if (pos == std::string::npos)
 					break;
 				run_from = args[++argidx].substr(0, pos);
-				run_to = args[argidx].substr(pos+1);
+				run_to = args[argidx].substr(pos + 1);
 				continue;
 			}
 			if (args[argidx] == "-flatten") {
@@ -231,7 +229,7 @@ struct SynthMchpPass : public ScriptPass
 			lut_size = 4;
 		} else {
 			log_cmd_error("Invalid Microchip -family setting: '%s'.\n", family.c_str());
-        }
+		}
 
 		if (!design->full_selection())
 			log_cmd_error("This command only operates on fully selected designs!\n");
@@ -239,8 +237,7 @@ struct SynthMchpPass : public ScriptPass
 		if (abc9 && retime)
 			log_cmd_error("-retime option not currently compatible with -abc9!\n");
 
-
-		log_header(design, "Executing SYNTH_MCHP pass.\n");
+		log_header(design, "Executing SYNTH_MICROCHIP pass.\n");
 		log_push();
 
 		run_script(design, run_from, run_to);
@@ -256,7 +253,7 @@ struct SynthMchpPass : public ScriptPass
 
 		if (check_label("begin")) {
 			std::string read_args;
-			read_args += " -lib -specify +/mchp/cells_sim.v";
+			read_args += " -lib -specify +/microchip/cells_sim.v";
 			run("read_verilog" + read_args);
 
 			run(stringf("hierarchy -check %s", top_opt.c_str()));
@@ -286,29 +283,29 @@ struct SynthMchpPass : public ScriptPass
 
 		if (check_label("map_dsp", "(skip if '-nodsp')")) {
 			if (!nodsp || help_mode) {
-				run("memory_dff"); // mchp_dsp will merge registers, reserve memory port registers first
+				run("memory_dff"); // microchip_dsp will merge registers, reserve memory port registers first
 				if (help_mode)
-					run("techmap -map +/mul2dsp.v -map +/mchp/{family}_dsp_map.v {options}");
+					run("techmap -map +/mul2dsp.v -map +/microchip/{family}_dsp_map.v {options}");
 				else if (family == "pf") // Microchip - map multipliers to DSP
-					run("techmap -map +/mul2dsp.v -map +/mchp/pf_dsp_map.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 "
-						"-D DSP_A_MAXWIDTH_PARTIAL=18 "	// Partial multipliers are intentionally
-										// limited to 18x18 in order to take
-										// advantage of the (PCOUT >> 17) -> PCIN
-										// dedicated cascade chain capability
-						"-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers
-						"-D DSP_Y_MINWIDTH=9 "
-						"-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL18X18");
-				
+					run("techmap -map +/mul2dsp.v -map +/microchip/pf_dsp_map.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 "
+					    "-D DSP_A_MAXWIDTH_PARTIAL=18 " // Partial multipliers are intentionally
+									    // limited to 18x18 in order to take
+									    // advantage of the (PCOUT >> 17) -> PCIN
+									    // dedicated cascade chain capability
+					    "-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers
+					    "-D DSP_Y_MINWIDTH=9 "
+					    "-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL18X18");
+
 				run("select a:mul2dsp");
 				run("setattr -unset mul2dsp");
 				run("opt_expr -fine");
 				run("wreduce");
 				run("select -clear");
 				if (help_mode)
-					run("mchp_dsp -family <family>");
+					run("microchip_dsp -family <family>");
 				else if (family == "pf") // Microchip - absorb cells into DSP
-					run("mchp_dsp -family " + family);
-				
+					run("microchip_dsp -family " + family);
+
 				run("chtype -set $mul t:$__soft_mul");
 			}
 		}
@@ -324,41 +321,44 @@ struct SynthMchpPass : public ScriptPass
 
 		if (check_label("map_memory")) {
 			std::string params = "";
-			std::string LSRAM_map = "+/mchp/LSRAM_map.v";
-			std::string uSRAM_map = "+/mchp/uSRAM_map.v";
-			if (debug_memory) run("write_verilog -noexpr memory_map_pre.vm");
+			std::string LSRAM_map = "+/microchip/LSRAM_map.v";
+			std::string uSRAM_map = "+/microchip/uSRAM_map.v";
+			if (debug_memory)
+				run("write_verilog -noexpr memory_map_pre.vm");
 			if (help_mode) {
 				params = " [...]";
 			} else {
 
 				if (family == "pf") {
 					// cost of a single bit for memory lowered to soft logic
-					params += " -logic-cost-rom 0.015625"; 
+					params += " -logic-cost-rom 0.015625";
 
-					params += " -lib +/mchp/LSRAM.txt";
-					params += " -lib +/mchp/uSRAM.txt";
-					LSRAM_map = "+/mchp/LSRAM_map.v";
-					uSRAM_map = "+/mchp/uSRAM_map.v";
+					params += " -lib +/microchip/LSRAM.txt";
+					params += " -lib +/microchip/uSRAM.txt";
+					LSRAM_map = "+/microchip/LSRAM_map.v";
+					uSRAM_map = "+/microchip/uSRAM_map.v";
 				}
-				if (nobram) params += " -no-auto-block";
+				if (nobram)
+					params += " -no-auto-block";
 			}
 
 			// transform memories into intermediate cells
 			// Cost based transformation. The cost is assigned by us for each cell.
 			run("memory_libmap" + params);
-			if (debug_memory) run("write_verilog -noexpr memory_map_libmap.vm");
+			if (debug_memory)
+				run("write_verilog -noexpr memory_map_libmap.vm");
 
 			// map intermediate cells to actual RAM macros
 			// NOTE: order doesnt matter here
 			run("techmap -map " + LSRAM_map);
 			run("techmap -map " + uSRAM_map);
-			if (debug_memory)  run("write_verilog -noexpr memory_map_final.vm");
+			if (debug_memory)
+				run("write_verilog -noexpr memory_map_final.vm");
 		}
 
 		if (check_label("map_ffram")) {
 			run("opt -fast -full");
 
-
 			// blast unmapped RAM to flops or LUTs
 			run("memory_map");
 		}
@@ -366,7 +366,8 @@ struct SynthMchpPass : public ScriptPass
 		if (check_label("fine")) {
 			run("opt -full");
 
-			if (debug_carry) run("write_verilog -noexpr ARI1_cells.vm");
+			if (debug_carry)
+				run("write_verilog -noexpr ARI1_cells.vm");
 
 			if (!nocarry) {
 				// converts $mux -> $_MUX_ to allow muxcover to work
@@ -376,21 +377,24 @@ struct SynthMchpPass : public ScriptPass
 				run("simplemap t:$xor"); // only mapping reduce_xor
 
 				// mapping based on Yosys internal gates
-				if (debug_carry) run("write_verilog -noexpr ARI1_pre.vm");
+				if (debug_carry)
+					run("write_verilog -noexpr ARI1_pre.vm");
 
 				// collapse $_AND_/$_OR_/$_XOR_ chains into reduction cells
 				run("extract_reduce");
 
-				if (debug_carry) run("write_verilog -noexpr ARI1_extract_reduce.vm");
-				
+				if (debug_carry)
+					run("write_verilog -noexpr ARI1_extract_reduce.vm");
+
 				// pack mux trees into $_MUX4_
 				run("muxcover -nodecode -mux4=220");
 
-				if (debug_carry) run("write_verilog -noexpr ARI1_muxcover.vm");
-				
-				run("techmap -map +/mchp/arith_map.v");
-				if (debug_carry) run("write_verilog -noexpr ARI1_post.vm");
-				
+				if (debug_carry)
+					run("write_verilog -noexpr ARI1_muxcover.vm");
+
+				run("techmap -map +/microchip/arith_map.v");
+				if (debug_carry)
+					run("write_verilog -noexpr ARI1_post.vm");
 			}
 
 			// convert all remaining cells to gates
@@ -403,10 +407,11 @@ struct SynthMchpPass : public ScriptPass
 			// Needs to be done before logic optimization, so that inverters (inserted
 			// 			here because of negative-polarity output enable) are handled.
 			if (help_mode || !noiopad) {
-				run("iopadmap -bits -inpad INBUF Y:PAD -outpad OUTBUF D:PAD -toutpad TRIBUFF E:D:PAD -tinoutpad BIBUF E:Y:D:PAD", "(unless -noiobs)");
+				run("iopadmap -bits -inpad INBUF Y:PAD -outpad OUTBUF D:PAD -toutpad TRIBUFF E:D:PAD -tinoutpad BIBUF E:Y:D:PAD",
+				    "(unless -noiobs)");
 			}
-				
-			std::string techmap_args = "-map +/techmap.v -map +/mchp/cells_map.v";
+
+			std::string techmap_args = "-map +/techmap.v -map +/microchip/cells_map.v";
 			run("techmap " + techmap_args);
 			run("clean");
 		}
@@ -447,14 +452,12 @@ struct SynthMchpPass : public ScriptPass
 			// $_DLATCH_[NP][NP][01]_			(D-latch + reset to 0/1)
 			// $_DLATCHSR_[NP][NP][NP]_			(D-latch + set + reset)
 
-			
 			if (family == "pf") {
 				std::string params = "";
-				
 
 				// D-flop with async reset and enable
 				// posedge CLK, active low reset to 1 or 0, active high EN
-				params += " -cell $_DFFE_PN?P_ 01"; 
+				params += " -cell $_DFFE_PN?P_ 01";
 
 				// D-flop with sync reset and enable, enable takes priority over reset
 				// posedge CLK, active low reset to 1 or 0, active high EN
@@ -466,12 +469,11 @@ struct SynthMchpPass : public ScriptPass
 
 				run("dfflegalize" + params, "(Converts FFs to supported types)");
 			}
-				
 
 			if (abc9 || help_mode) {
 				if (dff || help_mode)
 					run("zinit -all w:* t:$_SDFFCE_*", "('-dff' only)");
-				run("techmap -D NO_LUT -map +/mchp/cells_map.v", "('-abc9' only)");
+				run("techmap -D NO_LUT -map +/microchip/cells_map.v", "('-abc9' only)");
 			}
 		}
 
@@ -482,10 +484,10 @@ struct SynthMchpPass : public ScriptPass
 			if (help_mode)
 				run("abc -luts 2:2,3,6:5[,10,20] [-dff] [-D 1]", "(option for '-nowidelut', '-dff', '-retime')");
 			else if (abc9) {
-                
+
 				std::string abc9_opts;
 				// for the if command in abc to specify wire delay between adjects LUTs (default = 0)
-				// NOTE: should not have 0 wire delay between LUTs, 
+				// NOTE: should not have 0 wire delay between LUTs,
 				//		 otherwise abc might use LUT2+LUT3 instead of single LUT4
 				abc9_opts += " -W 300";
 				if (nowidelut)
@@ -493,8 +495,7 @@ struct SynthMchpPass : public ScriptPass
 				if (dff)
 					abc9_opts += " -dff";
 				run("abc9" + abc9_opts);
-			}
-			else {
+			} else {
 				std::string abc_opts = " -lut " + lut_size_s;
 				if (dff)
 					abc_opts += " -dff";
@@ -505,21 +506,18 @@ struct SynthMchpPass : public ScriptPass
 			run("clean");
 
 			if (help_mode || !abc9)
-				run("techmap -D NO_LUT -map +/mchp/cells_map.v", "(only if not '-abc9')");
-			std::string techmap_args = "-map +/mchp/cells_map.v -D FINAL_MAP";
+				run("techmap -D NO_LUT -map +/microchip/cells_map.v", "(only if not '-abc9')");
+			std::string techmap_args = "-map +/microchip/cells_map.v -D FINAL_MAP";
 			techmap_args += " -D LUT_WIDTH=" + lut_size_s;
 			run("techmap " + techmap_args);
-            
-			if (help_mode || lut_size == 4)
-				run("mchp_dffopt");
 
-            
+			if (help_mode || lut_size == 4)
+				run("microchip_dffopt");
 		}
 
-			run("clkbufmap -buf CLKINT Y:A -inpad CLKBUF Y:PAD");
-
-			run("clean -purge");
+		run("clkbufmap -buf CLKINT Y:A -inpad CLKBUF Y:PAD");
 
+		run("clean -purge");
 
 		if (check_label("check")) {
 			run("hierarchy -check");
@@ -538,6 +536,6 @@ struct SynthMchpPass : public ScriptPass
 				run(stringf("write_blif %s", blif_file.c_str()));
 		}
 	}
-} SynthMchpPass;
+} SynthMicrochipPass;
 
 PRIVATE_NAMESPACE_END

techlibs/microchip/tests/Registers/Registers.ys

@@ -17,7 +17,7 @@
 # read verilog files
 read_verilog Registers.v
 
-synth_mchp -top Registers -abc9 -family pf -noiopad
+synth_microchip -top Registers -abc9 -family polarfire -noiopad
 
 # write final outputfile
 write_verilog -noexpr Registers.vm

techlibs/microchip/tests/carryout/carryout.ys

@@ -16,6 +16,6 @@
 
 read_verilog carryout.v
 
-synth_mchp -top carryout -abc9 -family pf -noiopad
+synth_microchip -top carryout -abc9 -family polarfire -noiopad
 
 write_verilog -noexpr carryout.vm

techlibs/microchip/tests/cascade/cascade.ys

@@ -16,6 +16,6 @@
 
 read_verilog cascade.v
 
-synth_mchp -top cascade -abc9 -family pf -noiopad
+synth_microchip -top cascade -abc9 -family polarfire -noiopad
 
 write_verilog -noexpr cascade.vm

techlibs/microchip/tests/dff_opt/dff_opt.ys

@@ -15,7 +15,7 @@
 # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 read_verilog dff_opt.v 
 
-synth_mchp -top dff_opt -abc9 -family pf -noiopad
+synth_microchip -top dff_opt -abc9 -family polarfire -noiopad
 
 # write final outputfile
 write_verilog -noexpr dff_opt.vm

techlibs/microchip/tests/full_dsp/full_dsp.ys

@@ -16,6 +16,6 @@
 
 read_verilog full_dsp.v
 
-synth_mchp -top full_dsp -abc9 -family pf -noiopad
+synth_microchip -top full_dsp -abc9 -family polarfire -noiopad
 
 write_verilog -noexpr full_dsp.vm

techlibs/microchip/tests/large_mult/large_mult.ys

@@ -16,6 +16,6 @@
 
 read_verilog large_mult.v
 
-synth_mchp -top large_mult -abc9 -family pf -noiopad
+synth_microchip -top large_mult -abc9 -family polarfire -noiopad
 
 write_verilog -noexpr large_mult.vm

techlibs/microchip/tests/mac/mac.ys

@@ -18,7 +18,7 @@
 read_verilog mac.v
 
 # run the synth flow, specifies top module and additional parameters
-synth_mchp -top mac -abc9 -family pf -noiopad
+synticrochip -top mac -abc9 -family polarfire -noiopad
 
 # write final outputfile
 write_verilog -noexpr mac.vm

techlibs/microchip/tests/postAdd_mult/postAdd_mult.ys

@@ -16,6 +16,6 @@
 
 read_verilog postAdd_mult.v
 
-synth_mchp -top postAdd_mult -abc9 -family pf -noiopad
+synth_microchip -top postAdd_mult -abc9 -family polarfire -noiopad
 
 write_verilog -noexpr postAdd_mult.vm

techlibs/microchip/tests/post_adder/post_adder.ys

@@ -16,6 +16,6 @@
 
 read_verilog post_adder.v
 
-synth_mchp -top post_adder -abc9 -family pf
+synth_microchip -top post_adder -abc9 -family polarfire
 
 write_verilog -noexpr post_adder.vm

techlibs/microchip/tests/pre_adder_dsp/pre_adder_dsp.ys

@@ -16,6 +16,6 @@
 
 read_verilog pre_adder_dsp.v
 
-synth_mchp -top pre_adder_dsp -abc9 -family pf -noiopad
+synth_microchip -top pre_adder_dsp -abc9 -family polarfire -noiopad
 
 write_verilog -noexpr pre_adder_dsp.vm

techlibs/microchip/tests/ram_SDP/ram_SDP.ys

@@ -16,6 +16,6 @@
 
 read_verilog ram_SDP.v
 
-synth_mchp -top ram_SDP -abc9 -family pf -noiopad
+synth_microchip -top ram_SDP -abc9 -family polarfire -noiopad
 
 write_verilog -noexpr ram_SDP.vm

techlibs/microchip/tests/ram_TDP/ram_TDP.ys

@@ -16,6 +16,6 @@
 
 read_verilog ram_TDP.v
 
-synth_mchp -top ram_TDP -abc9 -family pf -noiopad -debug_memory
+synth_microchip -top ram_TDP -abc9 -family polarfire -noiopad -debug_memory
 
 write_verilog -noexpr ram_TDP.vm

techlibs/microchip/tests/reduce/reduce.ys

@@ -16,6 +16,6 @@
 
 read_verilog reduce.v
 
-synth_mchp -top reduce -abc9 -family pf -noiopad
+synth_microchip -top reduce -abc9 -family polarfire -noiopad
 
 write_verilog -noexpr reduce.vm

techlibs/microchip/tests/reg_c/reg_c.ys

@@ -16,6 +16,6 @@
 
 read_verilog reg_c.v
 
-synth_mchp -top reg_c -abc9 -family pf -noiopad
+synth_microchip -top reg_c -abc9 -family polarfire -noiopad
 
 write_verilog -noexpr reg_c.vm

techlibs/microchip/tests/reg_test/reg_test.ys

@@ -16,6 +16,6 @@
 
 read_verilog reg_test.v
 
-synth_mchp -top reg_test -abc9 -family pf -noiopad
+synth_microchip -top reg_test -abc9 -family polarfire -noiopad
 
 write_verilog -noexpr reg_test.vm

techlibs/microchip/tests/signed_mult/signed_mult.ys

@@ -16,6 +16,6 @@
 
 read_verilog signed_mult.v
 
-synth_mchp -top signed_mult -abc9 -family pf -noiopad
+synth_microchip -top signed_mult -abc9 -family polarfire -noiopad
 
 write_verilog -noexpr signed_mult.vm

techlibs/microchip/tests/simple_ram/simple_ram.ys

@@ -16,6 +16,6 @@
 
 read_verilog simple_ram.v
 
-synth_mchp -top simple_ram -abc9 -family pf -noiopad
+synth_microchip -top simple_ram -abc9 -family polarfire -noiopad
 
 write_verilog -noexpr simple_ram.vm

techlibs/microchip/tests/unsigned_mult/unsigned_mult.ys

@@ -16,6 +16,6 @@
 
 read_verilog unsigned_mult.v
 
-synth_mchp -top unsigned_mult -abc9 -family pf -noiopad
+synth_microchip -top unsigned_mult -abc9 -family polarfire -noiopad
 
 write_verilog -noexpr unsigned_mult.vm

techlibs/microchip/tests/uram_ar/uram_ar.ys

@@ -16,6 +16,6 @@
 
 read_verilog uram_ar.v
 
-synth_mchp -top uram_ar -abc9 -family pf -noiopad
+synth_microchip -top uram_ar -abc9 -family polarfire -noiopad
 
 write_verilog -noexpr uram_ar.vm

techlibs/microchip/tests/uram_sr/uram_sr.ys

@@ -16,6 +16,6 @@
 
 read_verilog uram_sr.v
 
-synth_mchp -top uram_sr -abc9 -family pf -noiopad
+synth_microchip -top uram_sr -abc9 -family polarfire -noiopad
 
 write_verilog -noexpr uram_sr.vm

techlibs/microchip/tests/widemux/widemux.ys

@@ -16,6 +16,6 @@
 
 read_verilog widemux.v
 
-synth_mchp -top widemux -abc9 -family pf -noiopad
+synth_microchip -top widemux -abc9 -family polarfire -noiopad
 
 write_verilog -noexpr widemux.vm