docs: moving code examples

Code now resides in `docs/source/code_examples`.
`CHAPTER_Prog` -> `stubnets`
`APPNOTE_011_Design_Investigation` -> `selections` and `show`
`resources/PRESENTATION_Intro` -> `intro`
`resources/PRESENTATION_ExSyn` -> `synth_flow`
`resources/PRESENTATION_ExAdv` -> `techmap`,  `macc`, and `selections`
`resources/PRESENTATION_ExOth` -> `scrambler` and `axis`

Note that generated images are not yet configured to build from the new code locations.

docs/source/code_examples/show/Makefile

@@ -0,0 +1,23 @@
+PROGRAM_PREFIX :=
+
+YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys
+
+EXAMPLE = example_00 example_01 example_02 example_03
+EXAMPLE_DOTS := $(addsuffix .dot,$(EXAMPLE))
+
+CMOS = cmos_00 cmos_01
+CMOS_DOTS := $(addsuffix .dot,$(CMOS))
+
+all: splice.dot $(EXAMPLE_DOTS) $(CMOS_DOTS)
+
+splice.dot: splice.v
+	$(YOSYS) -p 'proc; opt; show -format dot -prefix splice' splice.v
+
+$(EXAMPLE_DOTS): example.v example.ys
+	$(YOSYS) example.ys
+
+cmos_00.dot: cmos.v
+	$(YOSYS) -p 'read_verilog cmos.v; techmap; abc -liberty ../intro/mycells.lib;; show -format dot -prefix cmos_00'
+
+cmos_01.dot: cmos.v
+	$(YOSYS) -p 'read_verilog cmos.v; techmap; splitnets -ports; abc -liberty ../intro/mycells.lib;; show -lib ../intro/mycells.v -format dot -prefix cmos_01'

docs/source/code_examples/show/cmos.v

@@ -0,0 +1,3 @@
+module cmos_demo(input a, b, output [1:0] y);
+assign y = a + b;
+endmodule

docs/source/code_examples/show/example.v

@@ -0,0 +1,6 @@
+module example(input clk, a, b, c,
+               output reg [1:0] y);
+    always @(posedge clk)
+        if (c)
+            y <= c ? a + b : 2'd0;
+endmodule

docs/source/code_examples/show/example.ys

@@ -0,0 +1,11 @@
+read_verilog example.v
+show -format dot -prefix example_00
+proc
+show -format dot -prefix example_01
+opt
+show -format dot -prefix example_02
+
+cd example
+select t:$add
+show -format dot -prefix example_03
+

docs/source/code_examples/show/splice.v

@@ -0,0 +1,10 @@
+module splice_demo(a, b, c, d, e, f, x, y);
+
+input [1:0] a, b, c, d, e, f;
+output [1:0] x = {a[0], a[1]};
+
+output [11:0] y;
+assign {y[11:4], y[1:0], y[3:2]} =
+                {a, b, -{c, d}, ~{e, f}};
+
+endmodule