yosys/tests/errors/syntax_err08.v at 536ae16c3abcf3fef1dd14df8733bf51fa1bce1a - mirrors/yosys - Libre-Chip.org

mirrors/yosys

mirror of https://github.com/YosysHQ/yosys synced 2025-04-06 01:24:10 +00:00

Udi Finkelstein 536ae16c3a Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,

meaningful info on the error.
Also add 13 compilation examples that triggers each of these messages.

2018-10-25 02:37:56 +03:00

7 lines

64 B

Verilog

Raw Blame History

 module a;
 wire [5:0]x;
 wire [3:0]y;
 assign y = x 55;
 endmodule