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yosys/tests/errors/syntax_err12.v
Udi Finkelstein 536ae16c3a Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,
meaningful info on the error.
Also add 13 compilation examples that triggers each of these messages.
2018-10-25 02:37:56 +03:00

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Verilog

interface iface;
endinterface
module a (
iface x = 1'b0
);
endmodule