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17ca71e1ab · Bump version · Updated 2025-12-24 00:26:02 +00:00

Branches

1c73870f4d · synth_gatemate: add -noconstmult option · Updated 2025-08-07 07:11:06 +00:00

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41dc3e4180 · segfault: init · Updated 2025-07-28 18:01:55 +00:00

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c7df41b24e · log_help: Fix mem leaks · Updated 2025-07-23 00:24:14 +00:00

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b97e37e8e7 · icell_liberty: flops · Updated 2025-07-18 11:32:49 +00:00

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096d4c27ee · fixup! Add flex lib to vcxsrc include dirs · Updated 2025-07-16 01:55:24 +00:00

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9c1ba188b9 · dpicall.cc: Fix sans-plugin function call · Updated 2025-06-24 23:37:40 +00:00

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7b2bf1fe2e · CODEOWNERS: add myself for verilog frontend and ast layer · Updated 2025-06-24 08:54:13 +00:00

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efde8319dc · json: add -wide mode which permits no non-trivial sigspecs · Updated 2025-06-21 14:47:36 +00:00

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09dd419183 · wip · Updated 2025-06-07 01:06:42 +00:00

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6cd5921c2e · hashlib: break dict by reversing the iterator order · Updated 2025-05-30 14:43:55 +00:00

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33376da034 · ConstParser instead of const2ast using global state · Updated 2025-05-26 15:16:24 +00:00

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45452c18b2 · write_verilog: write module ports in order · Updated 2025-05-14 12:34:50 +00:00

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586fa033a6 · design: ensure all_modules outlives pass when building WITH_PYTHON · Updated 2025-05-10 15:19:51 +00:00

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068dd77a14 · check: fix up tests · Updated 2025-05-08 13:30:49 +00:00

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68c11321c0 · remove invalid tests · Updated 2025-05-07 15:52:31 +00:00

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11c846de5c · aiger, xaiger, aiger2: add -no_version · Updated 2025-04-30 17:51:35 +00:00

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ff2a8af545 · quicklogic: workaround for #5069 · Updated 2025-04-28 14:01:12 +00:00

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f0545d5bc1 · simplify: fix another struct wiretype attr memory leak · Updated 2025-04-28 11:18:00 +00:00

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532f9abc72 · opt_clean: hide it behind -x · Updated 2025-04-23 20:41:04 +00:00

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54ea41c40c · Add test to verify that the liberty format is properly parsed. · Updated 2025-04-23 19:41:13 +00:00

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