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main 5d0847f6fb · Bump version · Updated 2025-11-07 00:24:35 +00:00

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backends/verilog/verilog_backend.cc 45452c18b2 · write_verilog: write module ports in order · Updated 2025-05-14 12:34:50 +00:00	1003 1
emil/fix-design-lifetime-with-pyosys 586fa033a6 · design: ensure all_modules outlives pass when building WITH_PYTHON · Updated 2025-05-10 15:19:51 +00:00	1003 1
emil/check-harder 068dd77a14 · check: fix up tests · Updated 2025-05-08 13:30:49 +00:00	1107 6
emil/check-harder-fix-tests 68c11321c0 · remove invalid tests · Updated 2025-05-07 15:52:31 +00:00	1107 3
emil/aiger-no_version 11c846de5c · aiger, xaiger, aiger2: add -no_version · Updated 2025-04-30 17:51:35 +00:00	1034 1
emil/quicklogic-sv-empty-param-workaround ff2a8af545 · quicklogic: workaround for #5069 · Updated 2025-04-28 14:01:12 +00:00	1044 1
emil/fix-dangling-wiretype-2 f0545d5bc1 · simplify: fix another struct wiretype attr memory leak · Updated 2025-04-28 11:18:00 +00:00	1044 1
emil/astnode-gc a5458d21ef · fixup! fixup! fixup! ast: add GC for dev debugging · Updated 2025-04-25 09:10:16 +00:00	1066 6
emil/idstring-modern 272b7fa697 · fixup! rtlil: less sketchy IdString interner lifetime · Updated 2025-04-24 09:42:17 +00:00	1066 2
emil/dump-sorted da22d376bf · dump: sort lhs and rhs in a connection · Updated 2025-04-23 20:46:21 +00:00	1290 2
emil/fix-x-check_opt 532f9abc72 · opt_clean: hide it behind -x · Updated 2025-04-23 20:41:04 +00:00	1290 2
emil/mike-liberty-paren-rebased 54ea41c40c · Add test to verify that the liberty format is properly parsed. · Updated 2025-04-23 19:41:13 +00:00	1072 2
krys/cell_type_selections eb5abf9c12 · test_cell: Add $bweqx, kinda · Updated 2025-03-31 03:39:13 +00:00	1431 13
krys/update_gcc f2d7833b2b · test-compile: gcc-14 as newest · Updated 2025-03-27 21:31:06 +00:00	1243 2
emil/segfault-test-abc aa4d59cdcb · Trigger abc segfault for testing · Updated 2025-03-26 11:20:57 +00:00	1290 1
emil/opt_expr-limit-effort-refactor 95be73467d · opt_expr: chop up the kitchen sink · Updated 2025-03-20 14:58:39 +00:00	1716 7
emil/plugin-dir-fhs 1646bcd474 · WIP · Updated 2025-03-19 17:19:07 +00:00	1290 1
emil/quicklogic-dspv1-extra-fracturable-model 2e31dd3070 · quicklogic: add fracturable full-block dspv1 to keep vendor simulation model unchanged · Updated 2025-03-10 16:12:31 +00:00	1463 18
krys/fix_4927 913ac04764 · hierarchy: Derive abstract cells in top mod · Updated 2025-03-06 21:12:29 +00:00	1373 2
emil/equiv_induct-missing-model-error 5eb46f95c2 · equiv_induct: change missing SAT model warning to error · Updated 2025-03-06 17:15:52 +00:00	1373 1