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https://github.com/YosysHQ/yosys
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verific: replace uses of Const::bits()
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parent
e8f8297e5d
commit
ad8a00c90a
1 changed files with 15 additions and 15 deletions
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@ -1643,13 +1643,13 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
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ascii_initdata++;
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}
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for (int word_idx = 0; word_idx < memory->size; word_idx++) {
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Const initval = Const(State::Sx, memory->width);
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std::vector<State> initval(memory->width, State::Sx);
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bool initval_valid = false;
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for (int bit_idx = memory->width-1; bit_idx >= 0; bit_idx--) {
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if (*ascii_initdata == 0)
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break;
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if (*ascii_initdata == '0' || *ascii_initdata == '1') {
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initval.bits()[bit_idx] = (*ascii_initdata == '0') ? State::S0 : State::S1;
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initval[bit_idx] = (*ascii_initdata == '0') ? State::S0 : State::S1;
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initval_valid = true;
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}
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ascii_initdata++;
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@ -1661,7 +1661,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
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cell->setPort(ID::ADDR, word_idx);
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else
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cell->setPort(ID::ADDR, memory->size - word_idx - 1);
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cell->setPort(ID::DATA, initval);
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cell->setPort(ID::DATA, Const(initval));
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cell->parameters[ID::MEMID] = RTLIL::Const(memory->name.str());
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cell->parameters[ID::ABITS] = 32;
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cell->parameters[ID::WIDTH] = memory->width;
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@ -1760,7 +1760,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
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if (netbus->Size() == 1)
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wire->set_bool_attribute(ID::single_bit_vector);
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RTLIL::Const initval = Const(State::Sx, GetSize(wire));
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std::vector<State> initval(GetSize(wire), State::Sx);
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bool initval_valid = false;
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for (int i = netbus->LeftIndex();; i += netbus->IsUp() ? +1 : -1)
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@ -1773,9 +1773,9 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
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if (init_nets.count(net)) {
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if (init_nets.at(net) == '0')
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initval.bits().at(bitidx) = State::S0;
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initval.at(bitidx) = State::S0;
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if (init_nets.at(net) == '1')
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initval.bits().at(bitidx) = State::S1;
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initval.at(bitidx) = State::S1;
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initval_valid = true;
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init_nets.erase(net);
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}
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@ -1841,20 +1841,20 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
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for (auto it : init_nets)
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{
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Const initval;
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std::vector<State> initval;
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SigBit bit = net_map_at(it.first);
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log_assert(bit.wire);
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if (bit.wire->attributes.count(ID::init))
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initval = bit.wire->attributes.at(ID::init);
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initval = bit.wire->attributes.at(ID::init).to_bits();
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while (GetSize(initval) < GetSize(bit.wire))
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initval.bits().push_back(State::Sx);
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initval.push_back(State::Sx);
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if (it.second == '0')
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initval.bits().at(bit.offset) = State::S0;
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initval.at(bit.offset) = State::S0;
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if (it.second == '1')
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initval.bits().at(bit.offset) = State::S1;
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initval.at(bit.offset) = State::S1;
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bit.wire->attributes[ID::init] = initval;
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}
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@ -2041,7 +2041,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
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}
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Const qx_init = Const(State::S1, width);
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qx_init.bits().resize(2 * width, State::S0);
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qx_init.resize(2 * width, State::S0);
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clocking.addDff(new_verific_id(inst), sig_dx, sig_qx, qx_init);
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module->addXnor(new_verific_id(inst), sig_dx, sig_qx, sig_ox);
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@ -2306,7 +2306,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
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continue;
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if (non_ff_bits.count(SigBit(wire, i)))
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initval.bits()[i] = State::Sx;
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initval.set(i, State::Sx);
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}
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if (wire->port_input) {
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@ -2493,7 +2493,7 @@ Cell *VerificClocking::addDff(IdString name, SigSpec sig_d, SigSpec sig_q, Const
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if (c.wire && c.wire->attributes.count(ID::init)) {
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Const val = c.wire->attributes.at(ID::init);
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for (int i = 0; i < GetSize(c); i++)
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initval.bits()[offset+i] = val[c.offset+i];
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initval.set(offset+i, val[c.offset+i]);
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}
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offset += GetSize(c);
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}
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@ -2564,7 +2564,7 @@ Cell *VerificClocking::addAldff(IdString name, RTLIL::SigSpec sig_aload, RTLIL::
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if (c.wire && c.wire->attributes.count(ID::init)) {
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Const val = c.wire->attributes.at(ID::init);
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for (int i = 0; i < GetSize(c); i++)
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initval.bits()[offset+i] = val[c.offset+i];
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initval.set(offset+i, val[c.offset+i]);
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}
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offset += GetSize(c);
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}
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