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synth_analogdevices: different LUT weights
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1 changed files with 8 additions and 8 deletions
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@ -182,7 +182,7 @@ module INV(
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endspecify
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endmodule
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(* abc9_lut=1 *)
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(* abc9_lut=10 *)
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module LUT1(output O, input I0);
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parameter [1:0] INIT = 0;
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assign O = I0 ? INIT[1] : INIT[0];
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@ -191,7 +191,7 @@ module LUT1(output O, input I0);
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endspecify
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endmodule
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(* abc9_lut=2 *)
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(* abc9_lut=40 *)
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module LUT2(output O, input I0, I1);
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parameter [3:0] INIT = 0;
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wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];
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@ -202,7 +202,7 @@ module LUT2(output O, input I0, I1);
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endspecify
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endmodule
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(* abc9_lut=3 *)
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(* abc9_lut=10 *)
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module LUT3(output O, input I0, I1, I2);
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parameter [7:0] INIT = 0;
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wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];
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@ -215,7 +215,7 @@ module LUT3(output O, input I0, I1, I2);
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endspecify
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endmodule
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(* abc9_lut=4 *)
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(* abc9_lut=0 *)
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module LUT4(output O, input I0, I1, I2, I3);
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parameter [15:0] INIT = 0;
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wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
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@ -230,7 +230,7 @@ module LUT4(output O, input I0, I1, I2, I3);
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endspecify
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endmodule
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(* abc9_lut=5 *)
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(* abc9_lut=10 *)
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module LUT5(output O, input I0, I1, I2, I3, I4);
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parameter [31:0] INIT = 0;
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wire [15: 0] s4 = I4 ? INIT[31:16] : INIT[15: 0];
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@ -247,7 +247,7 @@ module LUT5(output O, input I0, I1, I2, I3, I4);
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endspecify
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endmodule
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(* abc9_lut=6 *)
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(* abc9_lut=10 *)
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module LUT6(output O, input I0, I1, I2, I3, I4, I5);
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parameter [63:0] INIT = 0;
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wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0];
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@ -284,7 +284,7 @@ endmodule
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// This is a placeholder for ABC9 to extract the area/delay
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// cost of 3-input LUTs and is not intended to be instantiated
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(* abc9_lut=12 *)
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(* abc9_lut=40 *)
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module \$__ABC9_LUT7 (output O, input I0, I1, I2, I3, I4, I5, I6);
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`ifndef __ICARUS__
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specify
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@ -301,7 +301,7 @@ endmodule
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// This is a placeholder for ABC9 to extract the area/delay
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// cost of 3-input LUTs and is not intended to be instantiated
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(* abc9_lut=24 *)
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(* abc9_lut=30 *)
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module \$__ABC9_LUT8 (output O, input I0, I1, I2, I3, I4, I5, I6, I7);
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`ifndef __ICARUS__
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specify
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