History

Jacob Lifshay fdc73b5f3b All checks were successful / deps (pull_request) Successful in 15s Details / test (pull_request) Successful in 4m19s Details / deps (push) Successful in 12s Details / test (push) Successful in 4m26s Details add ripple counter test to test simulating alternating circuits and extern modules		2025-03-25 18:56:26 -07:00
..
examples	change register names to end in `_reg` by convention	2024-10-06 18:50:09 -07:00
src	simulator: allow external module generators to wait for value changes and/or clock edges	2025-03-25 18:26:48 -07:00
tests	add ripple counter test to test simulating alternating circuits and extern modules	2025-03-25 18:56:26 -07:00
build.rs	add test for cfgs	2024-12-28 23:39:50 -08:00
Cargo.toml	simulator WIP: use petgraph for topological sort over assignments	2024-11-20 22:53:54 -08:00
LICENSE.md	prep for eventual publishing	2024-07-11 22:39:00 -07:00
Notices.txt	prep for eventual publishing	2024-07-11 22:39:00 -07:00
README.md	prep for eventual publishing	2024-07-11 22:39:00 -07:00
visit_types.json	simplify setting an extern module simulation	2025-03-21 17:08:29 -07:00

README.md

Fayalite

Fayalite is a library for designing digital hardware -- a hardware description language (HDL) embedded in the Rust programming language. Fayalite's semantics are based on FIRRTL as interpreted by LLVM CIRCT.