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Cesar Strauss dcf865caec
Add assertions and debug ports in order for the FIFO to pass induction 
As some proofs involving memories, it is necessary to add more ports to
the queue interface, to sync state. These changes are predicated on the
test environment, so normal use is not affected.

Since some speedup is achieved, use the saved time to test with a deeper
FIFO.
2024-12-29 13:12:58 -03:00
..
examples change register names to end in _reg by convention 2024-10-06 18:50:09 -07:00
src Add assertions and debug ports in order for the FIFO to pass induction 2024-12-29 13:12:58 -03:00
tests fix #[hdl]/#[hdl_module] attributes getting the wrong hygiene when processing #[cfg]s 2024-12-29 00:48:15 -08:00
build.rs add test for cfgs 2024-12-28 23:39:50 -08:00
Cargo.toml simulator WIP: use petgraph for topological sort over assignments 2024-11-20 22:53:54 -08:00
LICENSE.md prep for eventual publishing 2024-07-11 22:39:00 -07:00
Notices.txt prep for eventual publishing 2024-07-11 22:39:00 -07:00
README.md prep for eventual publishing 2024-07-11 22:39:00 -07:00
visit_types.json make ClockDomain and Reg generic over reset type 2024-11-26 20:47:03 -08:00

README.md

Fayalite

Fayalite is a library for designing digital hardware -- a hardware description language (HDL) embedded in the Rust programming language. Fayalite's semantics are based on FIRRTL as interpreted by LLVM CIRCT.