History

Jacob Lifshay 78edfc97b2 All checks were successful / test (push) Successful in 4m32s Details split int::IntCmp into expr::HdlPartialEq and expr::HdlPartialOrd		2024-09-22 17:28:46 -07:00
..
examples	add missing copyright headers	2024-09-22 15:30:05 -07:00
src	split int::IntCmp into expr::HdlPartialEq and expr::HdlPartialOrd	2024-09-22 17:28:46 -07:00
tests	add ty.uninit()	2024-09-22 17:26:23 -07:00
build.rs	WIP: use HdlOption[the_type_var] or UInt[123 + n] for creating types	2024-08-21 22:27:21 -07:00
Cargo.toml	add cli for compiling to verilog	2024-07-23 23:49:39 -07:00
LICENSE.md	prep for eventual publishing	2024-07-11 22:39:00 -07:00
Notices.txt	prep for eventual publishing	2024-07-11 22:39:00 -07:00
README.md	prep for eventual publishing	2024-07-11 22:39:00 -07:00
visit_types.json	add ty.uninit()	2024-09-22 17:26:23 -07:00

README.md

Fayalite

Fayalite is a library for designing digital hardware -- a hardware description language (HDL) embedded in the Rust programming language. Fayalite's semantics are based on FIRRTL as interpreted by LLVM CIRCT.