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fayalite
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Jacob Lifshay
26224abe1c
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sim: properly update all VCD wires when they share simulation state
2026-05-05 21:12:00 -07:00
..
fayalite
sim: properly update all VCD wires when they share simulation state
2026-05-05 21:12:00 -07:00
fayalite-proc-macros
clean up deps and move missed deps to workspace
2024-09-25 01:22:35 -07:00
fayalite-proc-macros-impl
redo #[hdl(sim)] match/let destructuring to support matching values of type Type::SimValue
2026-05-03 23:23:17 -07:00
fayalite-visit-gen
format code after switching to edition 2024
2025-08-24 16:35:21 -07:00