crates/fayalite/src/sim.rs

@@ -1295,10 +1295,16 @@ impl SimulationModuleState {
                 if !self.uninitialized_ios.is_empty() {
                     match which_module {
                         WhichModule::Main => {
-                            panic!("can't read from an output before initializing all inputs");
+                            panic!(
+                                "can't read from an output before initializing all inputs\nuninitialized_ios={:#?}",
+                                SortedSetDebug(&self.uninitialized_ios),
+                            );
                         }
                         WhichModule::Extern { .. } => {
-                            panic!("can't read from an input before initializing all outputs");
+                            panic!(
+                                "can't read from an input before initializing all outputs\nuninitialized_ios={:#?}",
+                                SortedSetDebug(&self.uninitialized_ios),
+                            );
                         }
                     }
                 }

crates/fayalite/src/sim/compiler.rs

@@ -4087,6 +4087,15 @@ impl Compiler {
             let init = self.compiled_expr_to_value(init, reg.source_location());
             (reg.clock_domain().rst, init)
         });
+
+        // next value defaults to current value
+        self.compile_simple_connect(
+            [].intern_slice(),
+            value.into(),
+            value,
+            reg.source_location(),
+        );
+
         self.compile_reg(
             clk,
             reset_and_init,

crates/fayalite/tests/sim.rs

@@ -7,7 +7,7 @@ use fayalite::{
     prelude::*,
     reset::ResetType,
     sim::vcd::VcdWriterDecls,
-    util::RcWriter,
+    util::{RcWriter, ready_valid::queue},
 };
 use std::{collections::BTreeMap, num::NonZeroUsize, rc::Rc};
 
@@ -2495,3 +2495,349 @@ fn test_sim_read_past() {
         panic!();
     }
 }
+
+#[hdl_module(outline_generated)]
+pub fn last_connect() {
+    #[hdl]
+    let inp: HdlOption<Array<Bool, 4>> = m.input();
+    #[hdl]
+    let out: HdlOption<UInt<8>> = m.output();
+    connect(out, HdlNone());
+    #[hdl]
+    if let HdlSome(v) = inp {
+        #[hdl]
+        let w = wire();
+        connect(out, HdlSome(w));
+        connect(w, v.len() as u8);
+        for (i, v) in v.into_iter().enumerate() {
+            #[hdl]
+            if v {
+                connect(w, i as u8);
+            }
+        }
+    }
+}
+
+#[hdl]
+#[test]
+fn test_last_connect() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let mut sim = Simulation::new(last_connect());
+    let mut writer = RcWriter::default();
+    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
+    let bools = [false, true];
+    sim.write(sim.io().inp, HdlNone());
+    sim.advance_time(SimDuration::from_micros(1));
+    let expected: SimValue<HdlOption<UInt<8>>> = #[hdl(sim)]
+    HdlNone();
+    assert_eq!(sim.read(sim.io().out), expected);
+    for a in bools {
+        for b in bools {
+            for c in bools {
+                for d in bools {
+                    let inp = [a, b, c, d];
+                    sim.write(sim.io().inp, HdlSome(inp));
+                    sim.advance_time(SimDuration::from_micros(1));
+                    let mut expected = inp.len() as u8;
+                    for (i, v) in inp.into_iter().enumerate() {
+                        if v {
+                            expected = i as u8;
+                        }
+                    }
+                    let expected: SimValue<HdlOption<UInt<8>>> = #[hdl(sim)]
+                    HdlSome(expected);
+                    let out = sim.read(sim.io().out);
+                    println!("expected={expected:?} out={out:?} inp={inp:?}");
+                    assert_eq!(expected, out);
+                }
+            }
+        }
+    }
+    sim.flush_traces().unwrap();
+    let vcd = String::from_utf8(writer.take()).unwrap();
+    println!("####### VCD:\n{vcd}\n#######");
+    if vcd != include_str!("sim/expected/last_connect.vcd") {
+        panic!();
+    }
+    let sim_debug = format!("{sim:#?}");
+    println!("#######\n{sim_debug}\n#######");
+    if sim_debug != include_str!("sim/expected/last_connect.txt") {
+        panic!();
+    }
+}
+
+#[track_caller]
+#[hdl]
+fn test_queue_helper(
+    capacity: usize,
+    inp_ready_is_comb: bool,
+    out_valid_is_comb: bool,
+    expected_vcd: &str,
+    expected_sim_debug: &str,
+) {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let mut sim = Simulation::new(queue(
+        UInt::<8>::new_static(),
+        NonZeroUsize::new(capacity).expect("capacity should be non-zero"),
+        inp_ready_is_comb,
+        out_valid_is_comb,
+    ));
+    let writer = RcWriter::default();
+    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
+    struct DumpVcdOnDrop {
+        writer: Option<RcWriter>,
+    }
+    impl Drop for DumpVcdOnDrop {
+        fn drop(&mut self) {
+            if let Some(mut writer) = self.writer.take() {
+                let vcd = String::from_utf8(writer.take()).unwrap();
+                println!("####### VCD:\n{vcd}\n#######");
+            }
+        }
+    }
+    let mut writer = DumpVcdOnDrop {
+        writer: Some(writer),
+    };
+    sim.write_clock(sim.io().cd.clk, false);
+    sim.write_reset(sim.io().cd.rst, true);
+    let mut input_value = 0u8;
+    let mut expected_output_value = 0u8;
+    /// deterministic random numbers
+    fn rand(mut v: u32) -> bool {
+        // random 32-bit primes
+        v = v.wrapping_mul(0xF807B7EF).rotate_left(16);
+        v ^= 0xA1E24BBA; // random 32-bit constant
+        v = v.wrapping_mul(0xE9D30017).rotate_left(16);
+        v = v.wrapping_mul(0x3895AFFB).rotate_left(16);
+        v & 1 != 0
+    }
+    for cycle in 0..100u32 {
+        println!("cycle: {cycle}");
+        sim.write(
+            sim.io().inp.data,
+            if rand(cycle) {
+                #[hdl(sim)]
+                HdlSome(input_value)
+            } else {
+                #[hdl(sim)]
+                HdlNone()
+            },
+        );
+        sim.write_bool(sim.io().out.ready, rand(u32::MAX / 2 + cycle));
+        sim.advance_time(SimDuration::from_nanos(500));
+        if !sim.read_reset(sim.io().cd.rst) {
+            let inp_ready = sim.read_bool(sim.io().inp.ready);
+            if inp_ready {
+                #[hdl(sim)]
+                if let HdlSome(v) = sim.read(sim.io().inp.data) {
+                    println!("enqueued {v}, expected {input_value:#x}");
+                    assert_eq!(v.as_int(), input_value);
+                    input_value = input_value.wrapping_add(1);
+                }
+            }
+            let out_valid = #[hdl(sim)]
+            if let HdlSome(v) = sim.read(sim.io().out.data) {
+                if sim.read_bool(sim.io().out.ready) {
+                    println!("dequeued {v}, expected {expected_output_value:#x}");
+                    assert_eq!(v.as_int(), expected_output_value);
+                    expected_output_value = expected_output_value.wrapping_add(1);
+                }
+                true
+            } else {
+                false
+            };
+            assert!(inp_ready || out_valid, "queue isn't making progress");
+        }
+        sim.write_clock(sim.io().cd.clk, true);
+        sim.advance_time(SimDuration::from_nanos(500));
+        sim.write_clock(sim.io().cd.clk, false);
+        sim.write_reset(sim.io().cd.rst, false);
+    }
+    sim.flush_traces().unwrap();
+    let vcd = String::from_utf8(writer.writer.take().unwrap().take()).unwrap();
+    println!("####### VCD:\n{vcd}\n#######");
+    if vcd != expected_vcd {
+        panic!();
+    }
+    let sim_debug = format!("{sim:#?}");
+    println!("#######\n{sim_debug}\n#######");
+    if sim_debug != expected_sim_debug {
+        panic!();
+    }
+}
+
+#[test]
+fn test_queue_1_false_false() {
+    test_queue_helper(
+        1,
+        false,
+        false,
+        include_str!("sim/expected/queue_1_false_false.vcd"),
+        include_str!("sim/expected/queue_1_false_false.txt"),
+    );
+}
+
+#[test]
+fn test_queue_1_false_true() {
+    test_queue_helper(
+        1,
+        false,
+        true,
+        include_str!("sim/expected/queue_1_false_true.vcd"),
+        include_str!("sim/expected/queue_1_false_true.txt"),
+    );
+}
+
+#[test]
+fn test_queue_1_true_false() {
+    test_queue_helper(
+        1,
+        true,
+        false,
+        include_str!("sim/expected/queue_1_true_false.vcd"),
+        include_str!("sim/expected/queue_1_true_false.txt"),
+    );
+}
+
+#[test]
+fn test_queue_1_true_true() {
+    test_queue_helper(
+        1,
+        true,
+        true,
+        include_str!("sim/expected/queue_1_true_true.vcd"),
+        include_str!("sim/expected/queue_1_true_true.txt"),
+    );
+}
+
+#[test]
+fn test_queue_2_false_false() {
+    test_queue_helper(
+        2,
+        false,
+        false,
+        include_str!("sim/expected/queue_2_false_false.vcd"),
+        include_str!("sim/expected/queue_2_false_false.txt"),
+    );
+}
+
+#[test]
+fn test_queue_2_false_true() {
+    test_queue_helper(
+        2,
+        false,
+        true,
+        include_str!("sim/expected/queue_2_false_true.vcd"),
+        include_str!("sim/expected/queue_2_false_true.txt"),
+    );
+}
+
+#[test]
+fn test_queue_2_true_false() {
+    test_queue_helper(
+        2,
+        true,
+        false,
+        include_str!("sim/expected/queue_2_true_false.vcd"),
+        include_str!("sim/expected/queue_2_true_false.txt"),
+    );
+}
+
+#[test]
+fn test_queue_2_true_true() {
+    test_queue_helper(
+        2,
+        true,
+        true,
+        include_str!("sim/expected/queue_2_true_true.vcd"),
+        include_str!("sim/expected/queue_2_true_true.txt"),
+    );
+}
+
+#[test]
+fn test_queue_3_false_false() {
+    test_queue_helper(
+        3,
+        false,
+        false,
+        include_str!("sim/expected/queue_3_false_false.vcd"),
+        include_str!("sim/expected/queue_3_false_false.txt"),
+    );
+}
+
+#[test]
+fn test_queue_3_false_true() {
+    test_queue_helper(
+        3,
+        false,
+        true,
+        include_str!("sim/expected/queue_3_false_true.vcd"),
+        include_str!("sim/expected/queue_3_false_true.txt"),
+    );
+}
+
+#[test]
+fn test_queue_3_true_false() {
+    test_queue_helper(
+        3,
+        true,
+        false,
+        include_str!("sim/expected/queue_3_true_false.vcd"),
+        include_str!("sim/expected/queue_3_true_false.txt"),
+    );
+}
+
+#[test]
+fn test_queue_3_true_true() {
+    test_queue_helper(
+        3,
+        true,
+        true,
+        include_str!("sim/expected/queue_3_true_true.vcd"),
+        include_str!("sim/expected/queue_3_true_true.txt"),
+    );
+}
+
+#[test]
+fn test_queue_4_false_false() {
+    test_queue_helper(
+        4,
+        false,
+        false,
+        include_str!("sim/expected/queue_4_false_false.vcd"),
+        include_str!("sim/expected/queue_4_false_false.txt"),
+    );
+}
+
+#[test]
+fn test_queue_4_false_true() {
+    test_queue_helper(
+        4,
+        false,
+        true,
+        include_str!("sim/expected/queue_4_false_true.vcd"),
+        include_str!("sim/expected/queue_4_false_true.txt"),
+    );
+}
+
+#[test]
+fn test_queue_4_true_false() {
+    test_queue_helper(
+        4,
+        true,
+        false,
+        include_str!("sim/expected/queue_4_true_false.vcd"),
+        include_str!("sim/expected/queue_4_true_false.txt"),
+    );
+}
+
+#[test]
+fn test_queue_4_true_true() {
+    test_queue_helper(
+        4,
+        true,
+        true,
+        include_str!("sim/expected/queue_4_true_true.vcd"),
+        include_str!("sim/expected/queue_4_true_true.txt"),
+    );
+}

crates/fayalite/tests/sim/expected/counter_async.txt

@@ -123,58 +123,62 @@ Simulation {
                     dest: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
                     src: StatePartIndex<BigSlots>(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> },
                 },
+                8: Copy {
+                    dest: StatePartIndex<BigSlots>(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
+                },
                 // at: module-XXXXXXXXXX.rs:1:1
-                8: Add {
+                9: Add {
                     dest: StatePartIndex<BigSlots>(8), // (0x4) SlotDebugData { name: "", ty: UInt<5> },
                     lhs: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
                     rhs: StatePartIndex<BigSlots>(7), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
                 },
-                9: CastToUInt {
+                10: CastToUInt {
                     dest: StatePartIndex<BigSlots>(9), // (0x4) SlotDebugData { name: "", ty: UInt<4> },
                     src: StatePartIndex<BigSlots>(8), // (0x4) SlotDebugData { name: "", ty: UInt<5> },
                     dest_width: 4,
                 },
                 // at: module-XXXXXXXXXX.rs:4:1
-                10: Copy {
+                11: Copy {
                     dest: StatePartIndex<BigSlots>(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
                     src: StatePartIndex<BigSlots>(9), // (0x4) SlotDebugData { name: "", ty: UInt<4> },
                 },
                 // at: module-XXXXXXXXXX.rs:6:1
-                11: Copy {
+                12: Copy {
                     dest: StatePartIndex<BigSlots>(2), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count", ty: UInt<4> },
                     src: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
                 },
                 // at: module-XXXXXXXXXX.rs:3:1
-                12: BranchIfSmallNonZero {
-                    target: 16,
+                13: BranchIfSmallNonZero {
+                    target: 17,
                     value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
-                13: BranchIfSmallZero {
-                    target: 17,
+                14: BranchIfSmallZero {
+                    target: 18,
                     value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
-                14: Copy {
+                15: Copy {
                     dest: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
                     src: StatePartIndex<BigSlots>(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
                 },
-                15: Branch {
-                    target: 17,
+                16: Branch {
+                    target: 18,
                 },
-                16: Copy {
+                17: Copy {
                     dest: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
                     src: StatePartIndex<BigSlots>(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> },
                 },
-                17: XorSmallImmediate {
+                18: XorSmallImmediate {
                     dest: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                     lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
                     rhs: 0x1,
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                18: Return,
+                19: Return,
             ],
             ..
         },
-        pc: 18,
+        pc: 19,
         memory_write_log: [],
         memories: StatePart {
             value: [],

crates/fayalite/tests/sim/expected/counter_sync.txt

@@ -102,61 +102,65 @@ Simulation {
                     src: StatePartIndex<BigSlots>(7), // (0x4) SlotDebugData { name: "", ty: UInt<5> },
                     dest_width: 4,
                 },
-                // at: module-XXXXXXXXXX.rs:4:1
-                4: Copy {
-                    dest: StatePartIndex<BigSlots>(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(8), // (0x4) SlotDebugData { name: "", ty: UInt<4> },
-                },
                 // at: module-XXXXXXXXXX.rs:3:1
-                5: IsNonZeroDestIsSmall {
+                4: IsNonZeroDestIsSmall {
                     dest: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                     src: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: SyncReset },
                 },
-                6: IsNonZeroDestIsSmall {
+                5: IsNonZeroDestIsSmall {
                     dest: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
                     src: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock },
                 },
-                7: AndSmall {
+                6: AndSmall {
                     dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                     lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
                     rhs: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
+                7: Copy {
+                    dest: StatePartIndex<BigSlots>(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
+                },
+                // at: module-XXXXXXXXXX.rs:4:1
+                8: Copy {
+                    dest: StatePartIndex<BigSlots>(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(8), // (0x4) SlotDebugData { name: "", ty: UInt<4> },
+                },
                 // at: module-XXXXXXXXXX.rs:1:1
-                8: Const {
+                9: Const {
                     dest: StatePartIndex<BigSlots>(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> },
                     value: 0x3,
                 },
                 // at: module-XXXXXXXXXX.rs:3:1
-                9: BranchIfSmallZero {
-                    target: 14,
+                10: BranchIfSmallZero {
+                    target: 15,
                     value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
-                10: BranchIfSmallNonZero {
-                    target: 13,
+                11: BranchIfSmallNonZero {
+                    target: 14,
                     value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
-                11: Copy {
+                12: Copy {
                     dest: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
                     src: StatePartIndex<BigSlots>(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
                 },
-                12: Branch {
-                    target: 14,
+                13: Branch {
+                    target: 15,
                 },
-                13: Copy {
+                14: Copy {
                     dest: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
                     src: StatePartIndex<BigSlots>(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> },
                 },
-                14: XorSmallImmediate {
+                15: XorSmallImmediate {
                     dest: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                     lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
                     rhs: 0x1,
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                15: Return,
+                16: Return,
             ],
             ..
         },
-        pc: 15,
+        pc: 16,
         memory_write_log: [],
         memories: StatePart {
             value: [],

crates/fayalite/tests/sim/expected/enums.txt

@@ -1012,173 +1012,177 @@ Simulation {
                     lhs: StatePartIndex<SmallSlots>(4), // (0x1 1) SlotDebugData { name: "", ty: Bool },
                     rhs: StatePartIndex<SmallSlots>(2), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
+                99: Copy {
+                    dest: StatePartIndex<BigSlots>(24), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    src: StatePartIndex<BigSlots>(23), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                },
                 // at: module-XXXXXXXXXX.rs:1:1
-                99: Const {
+                100: Const {
                     dest: StatePartIndex<BigSlots>(25), // (0x0) SlotDebugData { name: "", ty: UInt<6> },
                     value: 0x0,
                 },
-                100: Copy {
+                101: Copy {
                     dest: StatePartIndex<BigSlots>(26), // (0x0) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
                     src: StatePartIndex<BigSlots>(25), // (0x0) SlotDebugData { name: "", ty: UInt<6> },
                 },
                 // at: module-XXXXXXXXXX.rs:12:1
-                101: BranchIfZero {
-                    target: 109,
+                102: BranchIfZero {
+                    target: 110,
                     value: StatePartIndex<BigSlots>(2), // (0x1) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::en", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:13:1
-                102: BranchIfZero {
-                    target: 104,
+                103: BranchIfZero {
+                    target: 105,
                     value: StatePartIndex<BigSlots>(46), // (0x0) SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:14:1
-                103: Copy {
+                104: Copy {
                     dest: StatePartIndex<BigSlots>(24), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
                     src: StatePartIndex<BigSlots>(26), // (0x0) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
                 },
                 // at: module-XXXXXXXXXX.rs:13:1
-                104: BranchIfNonZero {
-                    target: 109,
+                105: BranchIfNonZero {
+                    target: 110,
                     value: StatePartIndex<BigSlots>(46), // (0x0) SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:15:1
-                105: BranchIfZero {
-                    target: 107,
+                106: BranchIfZero {
+                    target: 108,
                     value: StatePartIndex<BigSlots>(48), // (0x0) SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:16:1
-                106: Copy {
+                107: Copy {
                     dest: StatePartIndex<BigSlots>(24), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
                     src: StatePartIndex<BigSlots>(65), // (0xd) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
                 },
                 // at: module-XXXXXXXXXX.rs:15:1
-                107: BranchIfNonZero {
-                    target: 109,
+                108: BranchIfNonZero {
+                    target: 110,
                     value: StatePartIndex<BigSlots>(48), // (0x0) SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:17:1
-                108: Copy {
+                109: Copy {
                     dest: StatePartIndex<BigSlots>(24), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
                     src: StatePartIndex<BigSlots>(87), // (0x3e) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
                 },
                 // at: module-XXXXXXXXXX.rs:10:1
-                109: Copy {
+                110: Copy {
                     dest: StatePartIndex<BigSlots>(15), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b2_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
                     src: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                110: Copy {
+                111: Copy {
                     dest: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
                     src: StatePartIndex<BigSlots>(15), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b2_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
                 },
-                111: SliceInt {
+                112: SliceInt {
                     dest: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
                     src: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
                     start: 1,
                     len: 2,
                 },
-                112: SliceInt {
+                113: SliceInt {
                     dest: StatePartIndex<BigSlots>(20), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
                     src: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
                     start: 0,
                     len: 1,
                 },
-                113: SliceInt {
+                114: SliceInt {
                     dest: StatePartIndex<BigSlots>(21), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
                     src: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
                     start: 1,
                     len: 1,
                 },
-                114: Copy {
+                115: Copy {
                     dest: StatePartIndex<BigSlots>(22), // (0x0) SlotDebugData { name: "", ty: Bool },
                     src: StatePartIndex<BigSlots>(21), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
                 },
-                115: Copy {
+                116: Copy {
                     dest: StatePartIndex<BigSlots>(16), // (0x0) SlotDebugData { name: ".0", ty: UInt<1> },
                     src: StatePartIndex<BigSlots>(20), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
                 },
-                116: Copy {
+                117: Copy {
                     dest: StatePartIndex<BigSlots>(17), // (0x0) SlotDebugData { name: ".1", ty: Bool },
                     src: StatePartIndex<BigSlots>(22), // (0x0) SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:9:1
-                117: AndBigWithSmallImmediate {
+                118: AndBigWithSmallImmediate {
                     dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} },
                     lhs: StatePartIndex<BigSlots>(15), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b2_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
                     rhs: 0x1,
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                118: Copy {
+                119: Copy {
                     dest: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
                     src: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
                 },
-                119: SliceInt {
+                120: SliceInt {
                     dest: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
                     src: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
                     start: 1,
                     len: 2,
                 },
-                120: SliceInt {
+                121: SliceInt {
                     dest: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
                     src: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
                     start: 0,
                     len: 1,
                 },
-                121: SliceInt {
+                122: SliceInt {
                     dest: StatePartIndex<BigSlots>(13), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
                     src: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
                     start: 1,
                     len: 1,
                 },
-                122: Copy {
+                123: Copy {
                     dest: StatePartIndex<BigSlots>(14), // (0x0) SlotDebugData { name: "", ty: Bool },
                     src: StatePartIndex<BigSlots>(13), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
                 },
-                123: Copy {
+                124: Copy {
                     dest: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: ".0", ty: UInt<1> },
                     src: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
                 },
-                124: Copy {
+                125: Copy {
                     dest: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: ".1", ty: Bool },
                     src: StatePartIndex<BigSlots>(14), // (0x0) SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:8:1
-                125: AndBigWithSmallImmediate {
+                126: AndBigWithSmallImmediate {
                     dest: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} },
                     lhs: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
                     rhs: 0x1,
                 },
                 // at: module-XXXXXXXXXX.rs:11:1
-                126: BranchIfSmallZero {
-                    target: 131,
+                127: BranchIfSmallZero {
+                    target: 132,
                     value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
-                127: BranchIfSmallNonZero {
-                    target: 130,
+                128: BranchIfSmallNonZero {
+                    target: 131,
                     value: StatePartIndex<SmallSlots>(5), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
-                128: Copy {
+                129: Copy {
                     dest: StatePartIndex<BigSlots>(23), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
                     src: StatePartIndex<BigSlots>(24), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
                 },
-                129: Branch {
-                    target: 131,
+                130: Branch {
+                    target: 132,
                 },
-                130: Copy {
+                131: Copy {
                     dest: StatePartIndex<BigSlots>(23), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
                     src: StatePartIndex<BigSlots>(26), // (0x0) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
                 },
-                131: XorSmallImmediate {
+                132: XorSmallImmediate {
                     dest: StatePartIndex<SmallSlots>(2), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                     lhs: StatePartIndex<SmallSlots>(4), // (0x1 1) SlotDebugData { name: "", ty: Bool },
                     rhs: 0x1,
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                132: Return,
+                133: Return,
             ],
             ..
         },
-        pc: 132,
+        pc: 133,
         memory_write_log: [],
         memories: StatePart {
             value: [],

crates/fayalite/tests/sim/expected/last_connect.txt

@@ -0,0 +1,701 @@
+Simulation {
+    state: State {
+        insns: Insns {
+            state_layout: StateLayout {
+                ty: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 2,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Enum {
+                                    HdlNone,
+                                    HdlSome,
+                                },
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Enum {
+                                    HdlNone,
+                                    HdlSome,
+                                },
+                            },
+                        ],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 33,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(last_connect: last_connect).last_connect::inp",
+                                ty: Enum {
+                                    HdlNone,
+                                    HdlSome(Array<Bool, 4>),
+                                },
+                            },
+                            SlotDebugData {
+                                name: "[0]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "[1]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "[2]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "[3]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<5>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(last_connect: last_connect).last_connect::out",
+                                ty: Enum {
+                                    HdlNone,
+                                    HdlSome(UInt<8>),
+                                },
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<9>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<9>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Enum {
+                                    HdlNone,
+                                    HdlSome(UInt<8>),
+                                },
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(last_connect: last_connect).last_connect::w",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: ".0",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: ".1",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<9>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<9>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<9>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Enum {
+                                    HdlNone,
+                                    HdlSome(UInt<8>),
+                                },
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                    sim_only_slots: StatePartLayout<SimOnlySlots> {
+                        len: 0,
+                        debug_data: [],
+                        layout_data: [],
+                        ..
+                    },
+                },
+                memories: StatePartLayout<Memories> {
+                    len: 0,
+                    debug_data: [],
+                    layout_data: [],
+                    ..
+                },
+            },
+            insns: [
+                // at: module-XXXXXXXXXX.rs:1:1
+                0: Const {
+                    dest: StatePartIndex<BigSlots>(32), // (0x3) SlotDebugData { name: "", ty: UInt<8> },
+                    value: 0x3,
+                },
+                1: Const {
+                    dest: StatePartIndex<BigSlots>(31), // (0x2) SlotDebugData { name: "", ty: UInt<8> },
+                    value: 0x2,
+                },
+                2: Const {
+                    dest: StatePartIndex<BigSlots>(30), // (0x1) SlotDebugData { name: "", ty: UInt<8> },
+                    value: 0x1,
+                },
+                3: Const {
+                    dest: StatePartIndex<BigSlots>(29), // (0x0) SlotDebugData { name: "", ty: UInt<8> },
+                    value: 0x0,
+                },
+                4: Const {
+                    dest: StatePartIndex<BigSlots>(28), // (0x4) SlotDebugData { name: "", ty: UInt<8> },
+                    value: 0x4,
+                },
+                // at: module-XXXXXXXXXX.rs:8:1
+                5: Copy {
+                    dest: StatePartIndex<BigSlots>(20), // (0x3) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::w", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(28), // (0x4) SlotDebugData { name: "", ty: UInt<8> },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                6: Const {
+                    dest: StatePartIndex<BigSlots>(23), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    value: 0x1,
+                },
+                7: Const {
+                    dest: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "", ty: UInt<9> },
+                    value: 0x0,
+                },
+                8: Copy {
+                    dest: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} },
+                    src: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "", ty: UInt<9> },
+                },
+                // at: module-XXXXXXXXXX.rs:4:1
+                9: Copy {
+                    dest: StatePartIndex<BigSlots>(15), // (0x7) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::out", ty: Enum {HdlNone, HdlSome(UInt<8>)} },
+                    src: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                10: Copy {
+                    dest: StatePartIndex<BigSlots>(5), // (0x1f) SlotDebugData { name: "", ty: UInt<5> },
+                    src: StatePartIndex<BigSlots>(0), // (0x1f) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::inp", ty: Enum {HdlNone, HdlSome(Array<Bool, 4>)} },
+                },
+                11: SliceInt {
+                    dest: StatePartIndex<BigSlots>(6), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(5), // (0x1f) SlotDebugData { name: "", ty: UInt<5> },
+                    start: 1,
+                    len: 4,
+                },
+                12: SliceInt {
+                    dest: StatePartIndex<BigSlots>(7), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(6), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
+                    start: 0,
+                    len: 1,
+                },
+                13: Copy {
+                    dest: StatePartIndex<BigSlots>(8), // (0x1) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(7), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                },
+                14: SliceInt {
+                    dest: StatePartIndex<BigSlots>(9), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(6), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
+                    start: 1,
+                    len: 1,
+                },
+                15: Copy {
+                    dest: StatePartIndex<BigSlots>(10), // (0x1) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(9), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                },
+                16: SliceInt {
+                    dest: StatePartIndex<BigSlots>(11), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(6), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
+                    start: 2,
+                    len: 1,
+                },
+                17: Copy {
+                    dest: StatePartIndex<BigSlots>(12), // (0x1) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(11), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                },
+                18: SliceInt {
+                    dest: StatePartIndex<BigSlots>(13), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(6), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
+                    start: 3,
+                    len: 1,
+                },
+                19: Copy {
+                    dest: StatePartIndex<BigSlots>(14), // (0x1) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(13), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                },
+                20: Copy {
+                    dest: StatePartIndex<BigSlots>(1), // (0x1) SlotDebugData { name: "[0]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(8), // (0x1) SlotDebugData { name: "", ty: Bool },
+                },
+                21: Copy {
+                    dest: StatePartIndex<BigSlots>(2), // (0x1) SlotDebugData { name: "[1]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(10), // (0x1) SlotDebugData { name: "", ty: Bool },
+                },
+                22: Copy {
+                    dest: StatePartIndex<BigSlots>(3), // (0x1) SlotDebugData { name: "[2]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(12), // (0x1) SlotDebugData { name: "", ty: Bool },
+                },
+                23: Copy {
+                    dest: StatePartIndex<BigSlots>(4), // (0x1) SlotDebugData { name: "[3]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(14), // (0x1) SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:9:1
+                24: BranchIfZero {
+                    target: 26,
+                    value: StatePartIndex<BigSlots>(1), // (0x1) SlotDebugData { name: "[0]", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:10:1
+                25: Copy {
+                    dest: StatePartIndex<BigSlots>(20), // (0x3) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::w", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(29), // (0x0) SlotDebugData { name: "", ty: UInt<8> },
+                },
+                // at: module-XXXXXXXXXX.rs:9:1
+                26: BranchIfZero {
+                    target: 28,
+                    value: StatePartIndex<BigSlots>(2), // (0x1) SlotDebugData { name: "[1]", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:10:1
+                27: Copy {
+                    dest: StatePartIndex<BigSlots>(20), // (0x3) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::w", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(30), // (0x1) SlotDebugData { name: "", ty: UInt<8> },
+                },
+                // at: module-XXXXXXXXXX.rs:9:1
+                28: BranchIfZero {
+                    target: 30,
+                    value: StatePartIndex<BigSlots>(3), // (0x1) SlotDebugData { name: "[2]", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:10:1
+                29: Copy {
+                    dest: StatePartIndex<BigSlots>(20), // (0x3) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::w", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(31), // (0x2) SlotDebugData { name: "", ty: UInt<8> },
+                },
+                // at: module-XXXXXXXXXX.rs:9:1
+                30: BranchIfZero {
+                    target: 32,
+                    value: StatePartIndex<BigSlots>(4), // (0x1) SlotDebugData { name: "[3]", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:10:1
+                31: Copy {
+                    dest: StatePartIndex<BigSlots>(20), // (0x3) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::w", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(32), // (0x3) SlotDebugData { name: "", ty: UInt<8> },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                32: Copy {
+                    dest: StatePartIndex<BigSlots>(21), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(23), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                },
+                33: Copy {
+                    dest: StatePartIndex<BigSlots>(22), // (0x3) SlotDebugData { name: ".1", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(20), // (0x3) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::w", ty: UInt<8> },
+                },
+                34: Shl {
+                    dest: StatePartIndex<BigSlots>(24), // (0x6) SlotDebugData { name: "", ty: UInt<9> },
+                    lhs: StatePartIndex<BigSlots>(22), // (0x3) SlotDebugData { name: ".1", ty: UInt<8> },
+                    rhs: 1,
+                },
+                35: Or {
+                    dest: StatePartIndex<BigSlots>(25), // (0x7) SlotDebugData { name: "", ty: UInt<9> },
+                    lhs: StatePartIndex<BigSlots>(21), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
+                    rhs: StatePartIndex<BigSlots>(24), // (0x6) SlotDebugData { name: "", ty: UInt<9> },
+                },
+                36: CastToUInt {
+                    dest: StatePartIndex<BigSlots>(26), // (0x7) SlotDebugData { name: "", ty: UInt<9> },
+                    src: StatePartIndex<BigSlots>(25), // (0x7) SlotDebugData { name: "", ty: UInt<9> },
+                    dest_width: 9,
+                },
+                37: Copy {
+                    dest: StatePartIndex<BigSlots>(27), // (0x7) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} },
+                    src: StatePartIndex<BigSlots>(26), // (0x7) SlotDebugData { name: "", ty: UInt<9> },
+                },
+                // at: module-XXXXXXXXXX.rs:2:1
+                38: AndBigWithSmallImmediate {
+                    dest: StatePartIndex<SmallSlots>(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} },
+                    lhs: StatePartIndex<BigSlots>(0), // (0x1f) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::inp", ty: Enum {HdlNone, HdlSome(Array<Bool, 4>)} },
+                    rhs: 0x1,
+                },
+                // at: module-XXXXXXXXXX.rs:5:1
+                39: BranchIfSmallNeImmediate {
+                    target: 41,
+                    lhs: StatePartIndex<SmallSlots>(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} },
+                    rhs: 0x1,
+                },
+                // at: module-XXXXXXXXXX.rs:7:1
+                40: Copy {
+                    dest: StatePartIndex<BigSlots>(15), // (0x7) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::out", ty: Enum {HdlNone, HdlSome(UInt<8>)} },
+                    src: StatePartIndex<BigSlots>(27), // (0x7) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} },
+                },
+                // at: module-XXXXXXXXXX.rs:3:1
+                41: AndBigWithSmallImmediate {
+                    dest: StatePartIndex<SmallSlots>(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} },
+                    lhs: StatePartIndex<BigSlots>(15), // (0x7) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::out", ty: Enum {HdlNone, HdlSome(UInt<8>)} },
+                    rhs: 0x1,
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                42: Copy {
+                    dest: StatePartIndex<BigSlots>(16), // (0x7) SlotDebugData { name: "", ty: UInt<9> },
+                    src: StatePartIndex<BigSlots>(15), // (0x7) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::out", ty: Enum {HdlNone, HdlSome(UInt<8>)} },
+                },
+                43: SliceInt {
+                    dest: StatePartIndex<BigSlots>(17), // (0x3) SlotDebugData { name: "", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(16), // (0x7) SlotDebugData { name: "", ty: UInt<9> },
+                    start: 1,
+                    len: 8,
+                },
+                44: Return,
+            ],
+            ..
+        },
+        pc: 44,
+        memory_write_log: [],
+        memories: StatePart {
+            value: [],
+        },
+        small_slots: StatePart {
+            value: [
+                1,
+                1,
+            ],
+        },
+        big_slots: StatePart {
+            value: [
+                31,
+                1,
+                1,
+                1,
+                1,
+                31,
+                15,
+                1,
+                1,
+                1,
+                1,
+                1,
+                1,
+                1,
+                1,
+                7,
+                7,
+                3,
+                0,
+                0,
+                3,
+                1,
+                3,
+                1,
+                6,
+                7,
+                7,
+                7,
+                4,
+                0,
+                1,
+                2,
+                3,
+            ],
+        },
+        sim_only_slots: StatePart {
+            value: [],
+        },
+    },
+    io: Instance {
+        name: <simulator>::last_connect,
+        instantiated: Module {
+            name: last_connect,
+            ..
+        },
+    },
+    main_module: SimulationModuleState {
+        base_targets: [
+            Instance {
+                name: <simulator>::last_connect,
+                instantiated: Module {
+                    name: last_connect,
+                    ..
+                },
+            }.inp,
+            Instance {
+                name: <simulator>::last_connect,
+                instantiated: Module {
+                    name: last_connect,
+                    ..
+                },
+            }.out,
+        ],
+        uninitialized_ios: {},
+        io_targets: {
+            Instance {
+                name: <simulator>::last_connect,
+                instantiated: Module {
+                    name: last_connect,
+                    ..
+                },
+            }.inp,
+            Instance {
+                name: <simulator>::last_connect,
+                instantiated: Module {
+                    name: last_connect,
+                    ..
+                },
+            }.out,
+        },
+        did_initial_settle: true,
+        clocks_for_past: {},
+    },
+    extern_modules: [],
+    trace_decls: TraceModule {
+        name: "last_connect",
+        children: [
+            TraceModuleIO {
+                name: "inp",
+                child: TraceEnumWithFields {
+                    name: "inp",
+                    discriminant: TraceEnumDiscriminant {
+                        location: TraceScalarId(0),
+                        name: "$tag",
+                        ty: Enum {
+                            HdlNone,
+                            HdlSome(Array<Bool, 4>),
+                        },
+                        flow: Source,
+                    },
+                    non_empty_fields: [
+                        TraceArray {
+                            name: "HdlSome",
+                            elements: [
+                                TraceBool {
+                                    location: TraceScalarId(1),
+                                    name: "[0]",
+                                    flow: Source,
+                                },
+                                TraceBool {
+                                    location: TraceScalarId(2),
+                                    name: "[1]",
+                                    flow: Source,
+                                },
+                                TraceBool {
+                                    location: TraceScalarId(3),
+                                    name: "[2]",
+                                    flow: Source,
+                                },
+                                TraceBool {
+                                    location: TraceScalarId(4),
+                                    name: "[3]",
+                                    flow: Source,
+                                },
+                            ],
+                            ty: Array<Bool, 4>,
+                            flow: Source,
+                        },
+                    ],
+                    ty: Enum {
+                        HdlNone,
+                        HdlSome(Array<Bool, 4>),
+                    },
+                    flow: Source,
+                },
+                ty: Enum {
+                    HdlNone,
+                    HdlSome(Array<Bool, 4>),
+                },
+                flow: Source,
+            },
+            TraceModuleIO {
+                name: "out",
+                child: TraceEnumWithFields {
+                    name: "out",
+                    discriminant: TraceEnumDiscriminant {
+                        location: TraceScalarId(5),
+                        name: "$tag",
+                        ty: Enum {
+                            HdlNone,
+                            HdlSome(UInt<8>),
+                        },
+                        flow: Sink,
+                    },
+                    non_empty_fields: [
+                        TraceUInt {
+                            location: TraceScalarId(6),
+                            name: "HdlSome",
+                            ty: UInt<8>,
+                            flow: Source,
+                        },
+                    ],
+                    ty: Enum {
+                        HdlNone,
+                        HdlSome(UInt<8>),
+                    },
+                    flow: Sink,
+                },
+                ty: Enum {
+                    HdlNone,
+                    HdlSome(UInt<8>),
+                },
+                flow: Sink,
+            },
+            TraceWire {
+                name: "w",
+                child: TraceUInt {
+                    location: TraceScalarId(7),
+                    name: "w",
+                    ty: UInt<8>,
+                    flow: Duplex,
+                },
+                ty: UInt<8>,
+            },
+        ],
+    },
+    traces: [
+        SimTrace {
+            id: TraceScalarId(0),
+            kind: EnumDiscriminant {
+                index: StatePartIndex<SmallSlots>(0),
+                ty: Enum {
+                    HdlNone,
+                    HdlSome(Array<Bool, 4>),
+                },
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(1),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(1),
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(2),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(2),
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(3),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(3),
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(4),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(4),
+            },
+            state: 0x1,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(5),
+            kind: EnumDiscriminant {
+                index: StatePartIndex<SmallSlots>(1),
+                ty: Enum {
+                    HdlNone,
+                    HdlSome(UInt<8>),
+                },
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(6),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(17),
+                ty: UInt<8>,
+            },
+            state: 0x03,
+            last_state: 0x02,
+        },
+        SimTrace {
+            id: TraceScalarId(7),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(20),
+                ty: UInt<8>,
+            },
+            state: 0x03,
+            last_state: 0x02,
+        },
+    ],
+    trace_memories: {},
+    trace_writers: [
+        Running(
+            VcdWriter {
+                finished_init: true,
+                timescale: 1 ps,
+                ..
+            },
+        ),
+    ],
+    clocks_triggered: [],
+    event_queue: EventQueue(EventQueueData {
+        instant: 17 μs,
+        events: {},
+    }),
+    waiting_sensitivity_sets_by_address: {},
+    waiting_sensitivity_sets_by_compiled_value: {},
+    ..
+}

crates/fayalite/tests/sim/expected/last_connect.vcd

@@ -0,0 +1,104 @@
+$timescale 1 ps $end
+$scope module last_connect $end
+$scope struct inp $end
+$var string 1 !C&}* \$tag $end
+$scope struct HdlSome $end
+$var wire 1 D_viZ \[0] $end
+$var wire 1 b5gFK \[1] $end
+$var wire 1 xUBRH \[2] $end
+$var wire 1 Gp7Xm \[3] $end
+$upscope $end
+$upscope $end
+$scope struct out $end
+$var string 1 ^Z_p3 \$tag $end
+$var wire 8 rz~), HdlSome $end
+$upscope $end
+$var wire 8 dlea> w $end
+$upscope $end
+$enddefinitions $end
+$dumpvars
+sHdlNone\x20(0) !C&}*
+0D_viZ
+0b5gFK
+0xUBRH
+0Gp7Xm
+sHdlNone\x20(0) ^Z_p3
+b0 rz~),
+b100 dlea>
+$end
+#1000000
+sHdlSome\x20(1) !C&}*
+sHdlSome\x20(1) ^Z_p3
+b100 rz~),
+#2000000
+1Gp7Xm
+b11 rz~),
+b11 dlea>
+#3000000
+1xUBRH
+0Gp7Xm
+b10 rz~),
+b10 dlea>
+#4000000
+1Gp7Xm
+b11 rz~),
+b11 dlea>
+#5000000
+1b5gFK
+0xUBRH
+0Gp7Xm
+b1 rz~),
+b1 dlea>
+#6000000
+1Gp7Xm
+b11 rz~),
+b11 dlea>
+#7000000
+1xUBRH
+0Gp7Xm
+b10 rz~),
+b10 dlea>
+#8000000
+1Gp7Xm
+b11 rz~),
+b11 dlea>
+#9000000
+1D_viZ
+0b5gFK
+0xUBRH
+0Gp7Xm
+b0 rz~),
+b0 dlea>
+#10000000
+1Gp7Xm
+b11 rz~),
+b11 dlea>
+#11000000
+1xUBRH
+0Gp7Xm
+b10 rz~),
+b10 dlea>
+#12000000
+1Gp7Xm
+b11 rz~),
+b11 dlea>
+#13000000
+1b5gFK
+0xUBRH
+0Gp7Xm
+b1 rz~),
+b1 dlea>
+#14000000
+1Gp7Xm
+b11 rz~),
+b11 dlea>
+#15000000
+1xUBRH
+0Gp7Xm
+b10 rz~),
+b10 dlea>
+#16000000
+1Gp7Xm
+b11 rz~),
+b11 dlea>
+#17000000

crates/fayalite/tests/sim/expected/ripple_counter.txt

@@ -314,55 +314,56 @@ Simulation {
                     src: StatePartIndex<BigSlots>(47), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4", ty: Bool },
                     width: 1,
                 },
-                // at: module-XXXXXXXXXX.rs:8:1
-                3: Copy {
-                    dest: StatePartIndex<BigSlots>(48), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4$next", ty: Bool },
-                    src: StatePartIndex<BigSlots>(52), // (0x1) SlotDebugData { name: "", ty: Bool },
-                },
                 // at: module-XXXXXXXXXX.rs:7:1
-                4: Copy {
+                3: Copy {
                     dest: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[4]", ty: Bool },
                     src: StatePartIndex<BigSlots>(47), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                5: Copy {
+                4: Copy {
                     dest: StatePartIndex<BigSlots>(57), // (0x0) SlotDebugData { name: "", ty: Clock },
                     src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[4]", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:10:1
-                6: Copy {
+                5: Copy {
                     dest: StatePartIndex<BigSlots>(53), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_5.clk", ty: Clock },
                     src: StatePartIndex<BigSlots>(57), // (0x0) SlotDebugData { name: "", ty: Clock },
                 },
                 // at: module-XXXXXXXXXX.rs:9:1
-                7: Copy {
+                6: Copy {
                     dest: StatePartIndex<BigSlots>(55), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_5: sw_reg).sw_reg::clk", ty: Clock },
                     src: StatePartIndex<BigSlots>(53), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_5.clk", ty: Clock },
                 },
+                // at: module-XXXXXXXXXX.rs:6:1
+                7: Copy {
+                    dest: StatePartIndex<BigSlots>(48), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4$next", ty: Bool },
+                    src: StatePartIndex<BigSlots>(47), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:8:1
                 8: Copy {
+                    dest: StatePartIndex<BigSlots>(48), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4$next", ty: Bool },
+                    src: StatePartIndex<BigSlots>(52), // (0x1) SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:9:1
+                9: Copy {
                     dest: StatePartIndex<BigSlots>(43), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_3.o", ty: Bool },
                     src: StatePartIndex<BigSlots>(45), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_3: sw_reg).sw_reg::o", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:11:1
-                9: Copy {
+                10: Copy {
                     dest: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[3]", ty: Bool },
                     src: StatePartIndex<BigSlots>(43), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_3.o", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                10: Copy {
+                11: Copy {
                     dest: StatePartIndex<BigSlots>(51), // (0x0) SlotDebugData { name: "", ty: Clock },
                     src: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[3]", ty: Bool },
                 },
-                11: NotU {
+                12: NotU {
                     dest: StatePartIndex<BigSlots>(41), // (0x1) SlotDebugData { name: "", ty: Bool },
                     src: StatePartIndex<BigSlots>(36), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2", ty: Bool },
                     width: 1,
                 },
-                // at: module-XXXXXXXXXX.rs:8:1
-                12: Copy {
-                    dest: StatePartIndex<BigSlots>(37), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2$next", ty: Bool },
-                    src: StatePartIndex<BigSlots>(41), // (0x1) SlotDebugData { name: "", ty: Bool },
-                },
                 // at: module-XXXXXXXXXX.rs:7:1
                 13: Copy {
                     dest: StatePartIndex<BigSlots>(4), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[2]", ty: Bool },
@@ -383,241 +384,257 @@ Simulation {
                     dest: StatePartIndex<BigSlots>(44), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_3: sw_reg).sw_reg::clk", ty: Clock },
                     src: StatePartIndex<BigSlots>(42), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_3.clk", ty: Clock },
                 },
+                // at: module-XXXXXXXXXX.rs:6:1
                 17: Copy {
+                    dest: StatePartIndex<BigSlots>(37), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2$next", ty: Bool },
+                    src: StatePartIndex<BigSlots>(36), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:8:1
+                18: Copy {
+                    dest: StatePartIndex<BigSlots>(37), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2$next", ty: Bool },
+                    src: StatePartIndex<BigSlots>(41), // (0x1) SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:9:1
+                19: Copy {
                     dest: StatePartIndex<BigSlots>(32), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_1.o", ty: Bool },
                     src: StatePartIndex<BigSlots>(34), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_1: sw_reg).sw_reg::o", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:11:1
-                18: Copy {
+                20: Copy {
                     dest: StatePartIndex<BigSlots>(3), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[1]", ty: Bool },
                     src: StatePartIndex<BigSlots>(32), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_1.o", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                19: Copy {
+                21: Copy {
                     dest: StatePartIndex<BigSlots>(40), // (0x0) SlotDebugData { name: "", ty: Clock },
                     src: StatePartIndex<BigSlots>(3), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[1]", ty: Bool },
                 },
-                20: NotU {
+                22: NotU {
                     dest: StatePartIndex<BigSlots>(30), // (0x1) SlotDebugData { name: "", ty: Bool },
                     src: StatePartIndex<BigSlots>(24), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0", ty: Bool },
                     width: 1,
                 },
-                // at: module-XXXXXXXXXX.rs:8:1
-                21: Copy {
-                    dest: StatePartIndex<BigSlots>(25), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0$next", ty: Bool },
-                    src: StatePartIndex<BigSlots>(30), // (0x1) SlotDebugData { name: "", ty: Bool },
-                },
                 // at: module-XXXXXXXXXX.rs:7:1
-                22: Copy {
+                23: Copy {
                     dest: StatePartIndex<BigSlots>(2), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[0]", ty: Bool },
                     src: StatePartIndex<BigSlots>(24), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                23: Copy {
+                24: Copy {
                     dest: StatePartIndex<BigSlots>(35), // (0x0) SlotDebugData { name: "", ty: Clock },
                     src: StatePartIndex<BigSlots>(2), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[0]", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:10:1
-                24: Copy {
+                25: Copy {
                     dest: StatePartIndex<BigSlots>(31), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_1.clk", ty: Clock },
                     src: StatePartIndex<BigSlots>(35), // (0x0) SlotDebugData { name: "", ty: Clock },
                 },
                 // at: module-XXXXXXXXXX.rs:9:1
-                25: Copy {
+                26: Copy {
                     dest: StatePartIndex<BigSlots>(33), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_1: sw_reg).sw_reg::clk", ty: Clock },
                     src: StatePartIndex<BigSlots>(31), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_1.clk", ty: Clock },
                 },
+                // at: module-XXXXXXXXXX.rs:6:1
+                27: Copy {
+                    dest: StatePartIndex<BigSlots>(25), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0$next", ty: Bool },
+                    src: StatePartIndex<BigSlots>(24), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:8:1
+                28: Copy {
+                    dest: StatePartIndex<BigSlots>(25), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0$next", ty: Bool },
+                    src: StatePartIndex<BigSlots>(30), // (0x1) SlotDebugData { name: "", ty: Bool },
+                },
                 // at: module-XXXXXXXXXX.rs:1:1
-                26: Const {
+                29: Const {
                     dest: StatePartIndex<BigSlots>(28), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
                     value: 0x0,
                 },
-                27: Copy {
+                30: Copy {
                     dest: StatePartIndex<BigSlots>(29), // (0x0) SlotDebugData { name: "", ty: SyncReset },
                     src: StatePartIndex<BigSlots>(28), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
                 },
-                28: Copy {
+                31: Copy {
                     dest: StatePartIndex<BigSlots>(26), // (0x1) SlotDebugData { name: ".clk", ty: Clock },
                     src: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::clk", ty: Clock },
                 },
-                29: Copy {
+                32: Copy {
                     dest: StatePartIndex<BigSlots>(27), // (0x0) SlotDebugData { name: ".rst", ty: SyncReset },
                     src: StatePartIndex<BigSlots>(29), // (0x0) SlotDebugData { name: "", ty: SyncReset },
                 },
                 // at: module-XXXXXXXXXX.rs:6:1
-                30: IsNonZeroDestIsSmall {
+                33: IsNonZeroDestIsSmall {
                     dest: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
                     src: StatePartIndex<BigSlots>(26), // (0x1) SlotDebugData { name: ".clk", ty: Clock },
                 },
-                31: AndSmall {
+                34: AndSmall {
                     dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                     lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
                     rhs: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                32: Copy {
+                35: Copy {
                     dest: StatePartIndex<BigSlots>(38), // (0x0) SlotDebugData { name: ".clk", ty: Clock },
                     src: StatePartIndex<BigSlots>(40), // (0x0) SlotDebugData { name: "", ty: Clock },
                 },
-                33: Copy {
+                36: Copy {
                     dest: StatePartIndex<BigSlots>(39), // (0x0) SlotDebugData { name: ".rst", ty: SyncReset },
                     src: StatePartIndex<BigSlots>(29), // (0x0) SlotDebugData { name: "", ty: SyncReset },
                 },
                 // at: module-XXXXXXXXXX.rs:6:1
-                34: IsNonZeroDestIsSmall {
+                37: IsNonZeroDestIsSmall {
                     dest: StatePartIndex<SmallSlots>(5), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                     src: StatePartIndex<BigSlots>(38), // (0x0) SlotDebugData { name: ".clk", ty: Clock },
                 },
-                35: AndSmall {
+                38: AndSmall {
                     dest: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                     lhs: StatePartIndex<SmallSlots>(5), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                     rhs: StatePartIndex<SmallSlots>(3), // (0x1 1) SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                36: Copy {
+                39: Copy {
                     dest: StatePartIndex<BigSlots>(49), // (0x0) SlotDebugData { name: ".clk", ty: Clock },
                     src: StatePartIndex<BigSlots>(51), // (0x0) SlotDebugData { name: "", ty: Clock },
                 },
-                37: Copy {
+                40: Copy {
                     dest: StatePartIndex<BigSlots>(50), // (0x0) SlotDebugData { name: ".rst", ty: SyncReset },
                     src: StatePartIndex<BigSlots>(29), // (0x0) SlotDebugData { name: "", ty: SyncReset },
                 },
                 // at: module-XXXXXXXXXX.rs:6:1
-                38: IsNonZeroDestIsSmall {
+                41: IsNonZeroDestIsSmall {
                     dest: StatePartIndex<SmallSlots>(8), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                     src: StatePartIndex<BigSlots>(49), // (0x0) SlotDebugData { name: ".clk", ty: Clock },
                 },
-                39: AndSmall {
+                42: AndSmall {
                     dest: StatePartIndex<SmallSlots>(7), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                     lhs: StatePartIndex<SmallSlots>(8), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                     rhs: StatePartIndex<SmallSlots>(6), // (0x1 1) SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                40: Copy {
+                43: Copy {
                     dest: StatePartIndex<BigSlots>(21), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
                     src: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[5]", ty: Bool },
                 },
-                41: Shl {
+                44: Shl {
                     dest: StatePartIndex<BigSlots>(22), // (0x0) SlotDebugData { name: "", ty: UInt<6> },
                     lhs: StatePartIndex<BigSlots>(21), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
                     rhs: 5,
                 },
-                42: Copy {
+                45: Copy {
                     dest: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
                     src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[4]", ty: Bool },
                 },
-                43: Shl {
+                46: Shl {
                     dest: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "", ty: UInt<5> },
                     lhs: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
                     rhs: 4,
                 },
-                44: Copy {
+                47: Copy {
                     dest: StatePartIndex<BigSlots>(15), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
                     src: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[3]", ty: Bool },
                 },
-                45: Shl {
+                48: Shl {
                     dest: StatePartIndex<BigSlots>(16), // (0x0) SlotDebugData { name: "", ty: UInt<4> },
                     lhs: StatePartIndex<BigSlots>(15), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
                     rhs: 3,
                 },
-                46: Copy {
+                49: Copy {
                     dest: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
                     src: StatePartIndex<BigSlots>(4), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[2]", ty: Bool },
                 },
-                47: Shl {
+                50: Shl {
                     dest: StatePartIndex<BigSlots>(13), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
                     lhs: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
                     rhs: 2,
                 },
-                48: Copy {
+                51: Copy {
                     dest: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
                     src: StatePartIndex<BigSlots>(3), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[1]", ty: Bool },
                 },
-                49: Shl {
+                52: Shl {
                     dest: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
                     lhs: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
                     rhs: 1,
                 },
-                50: Copy {
+                53: Copy {
                     dest: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
                     src: StatePartIndex<BigSlots>(2), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[0]", ty: Bool },
                 },
-                51: Or {
+                54: Or {
                     dest: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
                     lhs: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
                     rhs: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
                 },
-                52: Or {
+                55: Or {
                     dest: StatePartIndex<BigSlots>(14), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
                     lhs: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
                     rhs: StatePartIndex<BigSlots>(13), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
                 },
-                53: Or {
+                56: Or {
                     dest: StatePartIndex<BigSlots>(17), // (0x0) SlotDebugData { name: "", ty: UInt<4> },
                     lhs: StatePartIndex<BigSlots>(14), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
                     rhs: StatePartIndex<BigSlots>(16), // (0x0) SlotDebugData { name: "", ty: UInt<4> },
                 },
-                54: Or {
+                57: Or {
                     dest: StatePartIndex<BigSlots>(20), // (0x0) SlotDebugData { name: "", ty: UInt<5> },
                     lhs: StatePartIndex<BigSlots>(17), // (0x0) SlotDebugData { name: "", ty: UInt<4> },
                     rhs: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "", ty: UInt<5> },
                 },
-                55: Or {
+                58: Or {
                     dest: StatePartIndex<BigSlots>(23), // (0x0) SlotDebugData { name: "", ty: UInt<6> },
                     lhs: StatePartIndex<BigSlots>(20), // (0x0) SlotDebugData { name: "", ty: UInt<5> },
                     rhs: StatePartIndex<BigSlots>(22), // (0x0) SlotDebugData { name: "", ty: UInt<6> },
                 },
                 // at: module-XXXXXXXXXX.rs:5:1
-                56: Copy {
+                59: Copy {
                     dest: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::o", ty: UInt<6> },
                     src: StatePartIndex<BigSlots>(23), // (0x0) SlotDebugData { name: "", ty: UInt<6> },
                 },
                 // at: module-XXXXXXXXXX.rs:6:1
-                57: BranchIfSmallZero {
-                    target: 59,
+                60: BranchIfSmallZero {
+                    target: 62,
                     value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
-                58: Copy {
+                61: Copy {
                     dest: StatePartIndex<BigSlots>(24), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0", ty: Bool },
                     src: StatePartIndex<BigSlots>(25), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0$next", ty: Bool },
                 },
-                59: BranchIfSmallZero {
-                    target: 61,
+                62: BranchIfSmallZero {
+                    target: 64,
                     value: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
-                60: Copy {
+                63: Copy {
                     dest: StatePartIndex<BigSlots>(36), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2", ty: Bool },
                     src: StatePartIndex<BigSlots>(37), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2$next", ty: Bool },
                 },
-                61: BranchIfSmallZero {
-                    target: 63,
+                64: BranchIfSmallZero {
+                    target: 66,
                     value: StatePartIndex<SmallSlots>(7), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
-                62: Copy {
+                65: Copy {
                     dest: StatePartIndex<BigSlots>(47), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4", ty: Bool },
                     src: StatePartIndex<BigSlots>(48), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4$next", ty: Bool },
                 },
-                63: XorSmallImmediate {
+                66: XorSmallImmediate {
                     dest: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                     lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
                     rhs: 0x1,
                 },
-                64: XorSmallImmediate {
+                67: XorSmallImmediate {
                     dest: StatePartIndex<SmallSlots>(3), // (0x1 1) SlotDebugData { name: "", ty: Bool },
                     lhs: StatePartIndex<SmallSlots>(5), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                     rhs: 0x1,
                 },
-                65: XorSmallImmediate {
+                68: XorSmallImmediate {
                     dest: StatePartIndex<SmallSlots>(6), // (0x1 1) SlotDebugData { name: "", ty: Bool },
                     lhs: StatePartIndex<SmallSlots>(8), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                     rhs: 0x1,
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                66: Return,
+                69: Return,
             ],
             ..
         },
-        pc: 66,
+        pc: 69,
         memory_write_log: [],
         memories: StatePart {
             value: [],

crates/fayalite/tests/sim/expected/shift_register.txt

@@ -103,137 +103,156 @@ Simulation {
                     dest: StatePartIndex<BigSlots>(3), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::q", ty: Bool },
                     src: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
                 },
-                // at: module-XXXXXXXXXX.rs:12:1
+                // at: module-XXXXXXXXXX.rs:11:1
                 1: Copy {
+                    dest: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool },
+                    src: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:12:1
+                2: Copy {
                     dest: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool },
                     src: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
                 },
+                // at: module-XXXXXXXXXX.rs:9:1
+                3: Copy {
+                    dest: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool },
+                    src: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
+                },
                 // at: module-XXXXXXXXXX.rs:10:1
-                2: Copy {
+                4: Copy {
                     dest: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool },
                     src: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
                 },
+                // at: module-XXXXXXXXXX.rs:7:1
+                5: Copy {
+                    dest: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool },
+                    src: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
+                },
                 // at: module-XXXXXXXXXX.rs:8:1
-                3: Copy {
+                6: Copy {
                     dest: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool },
                     src: StatePartIndex<BigSlots>(4), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
                 },
-                // at: module-XXXXXXXXXX.rs:6:1
-                4: Copy {
-                    dest: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool },
-                    src: StatePartIndex<BigSlots>(2), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::d", ty: Bool },
-                },
                 // at: module-XXXXXXXXXX.rs:5:1
-                5: IsNonZeroDestIsSmall {
+                7: IsNonZeroDestIsSmall {
                     dest: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                     src: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst", ty: SyncReset },
                 },
-                6: IsNonZeroDestIsSmall {
+                8: IsNonZeroDestIsSmall {
                     dest: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
                     src: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk", ty: Clock },
                 },
-                7: AndSmall {
+                9: AndSmall {
                     dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                     lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
                     rhs: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
+                10: Copy {
+                    dest: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool },
+                    src: StatePartIndex<BigSlots>(4), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:6:1
+                11: Copy {
+                    dest: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool },
+                    src: StatePartIndex<BigSlots>(2), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::d", ty: Bool },
+                },
                 // at: module-XXXXXXXXXX.rs:1:1
-                8: Const {
+                12: Const {
                     dest: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "", ty: Bool },
                     value: 0x0,
                 },
                 // at: module-XXXXXXXXXX.rs:5:1
-                9: BranchIfSmallZero {
-                    target: 14,
+                13: BranchIfSmallZero {
+                    target: 18,
                     value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
-                10: BranchIfSmallNonZero {
-                    target: 13,
+                14: BranchIfSmallNonZero {
+                    target: 17,
                     value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
-                11: Copy {
+                15: Copy {
                     dest: StatePartIndex<BigSlots>(4), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
                     src: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool },
                 },
-                12: Branch {
-                    target: 14,
+                16: Branch {
+                    target: 18,
                 },
-                13: Copy {
+                17: Copy {
                     dest: StatePartIndex<BigSlots>(4), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
                     src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:7:1
-                14: BranchIfSmallZero {
-                    target: 19,
+                18: BranchIfSmallZero {
+                    target: 23,
                     value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
-                15: BranchIfSmallNonZero {
-                    target: 18,
+                19: BranchIfSmallNonZero {
+                    target: 22,
                     value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
-                16: Copy {
+                20: Copy {
                     dest: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
                     src: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool },
                 },
-                17: Branch {
-                    target: 19,
+                21: Branch {
+                    target: 23,
                 },
-                18: Copy {
+                22: Copy {
                     dest: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
                     src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:9:1
-                19: BranchIfSmallZero {
-                    target: 24,
+                23: BranchIfSmallZero {
+                    target: 28,
                     value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
-                20: BranchIfSmallNonZero {
-                    target: 23,
+                24: BranchIfSmallNonZero {
+                    target: 27,
                     value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
-                21: Copy {
+                25: Copy {
                     dest: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
                     src: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool },
                 },
-                22: Branch {
-                    target: 24,
+                26: Branch {
+                    target: 28,
                 },
-                23: Copy {
+                27: Copy {
                     dest: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
                     src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:11:1
-                24: BranchIfSmallZero {
-                    target: 29,
+                28: BranchIfSmallZero {
+                    target: 33,
                     value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
-                25: BranchIfSmallNonZero {
-                    target: 28,
+                29: BranchIfSmallNonZero {
+                    target: 32,
                     value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
-                26: Copy {
+                30: Copy {
                     dest: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
                     src: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool },
                 },
-                27: Branch {
-                    target: 29,
+                31: Branch {
+                    target: 33,
                 },
-                28: Copy {
+                32: Copy {
                     dest: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
                     src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:5:1
-                29: XorSmallImmediate {
+                33: XorSmallImmediate {
                     dest: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                     lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
                     rhs: 0x1,
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                30: Return,
+                34: Return,
             ],
             ..
         },
-        pc: 30,
+        pc: 34,
         memory_write_log: [],
         memories: StatePart {
             value: [],

crates/fayalite/tests/sim/expected/sim_only_connects.txt

@@ -212,55 +212,55 @@ Simulation {
                     dest: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "", ty: Bool },
                     value: 0x0,
                 },
-                // at: module-XXXXXXXXXX.rs:17:1
-                7: Copy {
-                    dest: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty$next", ty: Bool },
-                    src: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX.rs:16:1
-                8: CloneSimOnly {
-                    dest: StatePartIndex<SimOnlySlots>(9), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1$next", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
-                    src: StatePartIndex<SimOnlySlots>(0), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::inp", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
-                },
                 // at: module-XXXXXXXXXX.rs:12:1
-                9: CloneSimOnly {
+                7: CloneSimOnly {
                     dest: StatePartIndex<SimOnlySlots>(1), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::out1", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
                     src: StatePartIndex<SimOnlySlots>(8), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
                 },
                 // at: module-XXXXXXXXXX.rs:13:1
-                10: BranchIfZero {
-                    target: 12,
+                8: BranchIfZero {
+                    target: 10,
                     value: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:15:1
-                11: CloneSimOnly {
+                9: CloneSimOnly {
                     dest: StatePartIndex<SimOnlySlots>(1), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::out1", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
                     src: StatePartIndex<SimOnlySlots>(0), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::inp", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
                 },
                 // at: module-XXXXXXXXXX.rs:11:1
-                12: CloneSimOnly {
+                10: CloneSimOnly {
                     dest: StatePartIndex<SimOnlySlots>(4), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.inp", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
                     src: StatePartIndex<SimOnlySlots>(8), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
                 },
                 // at: module-XXXXXXXXXX.rs:13:1
-                13: BranchIfZero {
-                    target: 15,
+                11: BranchIfZero {
+                    target: 13,
                     value: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:14:1
-                14: CloneSimOnly {
+                12: CloneSimOnly {
                     dest: StatePartIndex<SimOnlySlots>(4), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.inp", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
                     src: StatePartIndex<SimOnlySlots>(0), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::inp", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
                 },
                 // at: module-XXXXXXXXXX.rs:10:1
-                15: Copy {
+                13: Copy {
                     dest: StatePartIndex<BigSlots>(2), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.cd.clk", ty: Clock },
                     src: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::cd.clk", ty: Clock },
                 },
-                16: Copy {
+                14: Copy {
                     dest: StatePartIndex<BigSlots>(3), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.cd.rst", ty: SyncReset },
                     src: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::cd.rst", ty: SyncReset },
                 },
+                // at: module-XXXXXXXXXX.rs:9:1
+                15: Copy {
+                    dest: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty$next", ty: Bool },
+                    src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:17:1
+                16: Copy {
+                    dest: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty$next", ty: Bool },
+                    src: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "", ty: Bool },
+                },
                 // at: module-XXXXXXXXXX.rs:1:1
                 17: Const {
                     dest: StatePartIndex<BigSlots>(8), // (0x1) SlotDebugData { name: "", ty: Bool },
@@ -280,91 +280,100 @@ Simulation {
                     lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
                     rhs: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
-                // at: module-XXXXXXXXXX.rs:7:1
                 21: CloneSimOnly {
+                    dest: StatePartIndex<SimOnlySlots>(9), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1$next", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
+                    src: StatePartIndex<SimOnlySlots>(8), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
+                },
+                // at: module-XXXXXXXXXX.rs:16:1
+                22: CloneSimOnly {
+                    dest: StatePartIndex<SimOnlySlots>(9), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1$next", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
+                    src: StatePartIndex<SimOnlySlots>(0), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::inp", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
+                },
+                // at: module-XXXXXXXXXX.rs:7:1
+                23: CloneSimOnly {
                     dest: StatePartIndex<SimOnlySlots>(5), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.out", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
                     src: StatePartIndex<SimOnlySlots>(7), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects.helper1: sim_only_connects_helper).sim_only_connects_helper::out", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
                 },
                 // at: module-XXXXXXXXXX.rs:18:1
-                22: CloneSimOnly {
+                24: CloneSimOnly {
                     dest: StatePartIndex<SimOnlySlots>(2), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::out2", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
                     src: StatePartIndex<SimOnlySlots>(5), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.out", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
                 },
                 // at: module-XXXXXXXXXX.rs:21:1
-                23: CloneSimOnly {
+                25: CloneSimOnly {
                     dest: StatePartIndex<SimOnlySlots>(11), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper2.inp", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
                     src: StatePartIndex<SimOnlySlots>(2), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::out2", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
                 },
                 // at: module-XXXXXXXXXX.rs:19:1
-                24: CloneSimOnly {
+                26: CloneSimOnly {
                     dest: StatePartIndex<SimOnlySlots>(13), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects.helper2: sim_only_connects_helper).sim_only_connects_helper::inp", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
                     src: StatePartIndex<SimOnlySlots>(11), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper2.inp", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
                 },
                 // at: module-XXXXXXXXXX.rs:7:1
-                25: CloneSimOnly {
+                27: CloneSimOnly {
                     dest: StatePartIndex<SimOnlySlots>(6), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects.helper1: sim_only_connects_helper).sim_only_connects_helper::inp", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
                     src: StatePartIndex<SimOnlySlots>(4), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.inp", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
                 },
-                26: Copy {
+                28: Copy {
                     dest: StatePartIndex<BigSlots>(4), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_only_connects.helper1: sim_only_connects_helper).sim_only_connects_helper::cd.clk", ty: Clock },
                     src: StatePartIndex<BigSlots>(2), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.cd.clk", ty: Clock },
                 },
-                27: Copy {
+                29: Copy {
                     dest: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects.helper1: sim_only_connects_helper).sim_only_connects_helper::cd.rst", ty: SyncReset },
                     src: StatePartIndex<BigSlots>(3), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.cd.rst", ty: SyncReset },
                 },
                 // at: module-XXXXXXXXXX.rs:8:1
-                28: BranchIfSmallZero {
-                    target: 33,
+                30: BranchIfSmallZero {
+                    target: 35,
                     value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
-                29: BranchIfSmallNonZero {
-                    target: 32,
+                31: BranchIfSmallNonZero {
+                    target: 34,
                     value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
-                30: CloneSimOnly {
+                32: CloneSimOnly {
                     dest: StatePartIndex<SimOnlySlots>(8), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
                     src: StatePartIndex<SimOnlySlots>(9), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1$next", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
                 },
-                31: Branch {
-                    target: 33,
+                33: Branch {
+                    target: 35,
                 },
-                32: CloneSimOnly {
+                34: CloneSimOnly {
                     dest: StatePartIndex<SimOnlySlots>(8), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
                     src: StatePartIndex<SimOnlySlots>(10), // ({}) SlotDebugData { name: "", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
                 },
                 // at: module-XXXXXXXXXX.rs:9:1
-                33: BranchIfSmallZero {
-                    target: 38,
+                35: BranchIfSmallZero {
+                    target: 40,
                     value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
-                34: BranchIfSmallNonZero {
-                    target: 37,
+                36: BranchIfSmallNonZero {
+                    target: 39,
                     value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
-                35: Copy {
+                37: Copy {
                     dest: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty", ty: Bool },
                     src: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty$next", ty: Bool },
                 },
-                36: Branch {
-                    target: 38,
+                38: Branch {
+                    target: 40,
                 },
-                37: Copy {
+                39: Copy {
                     dest: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty", ty: Bool },
                     src: StatePartIndex<BigSlots>(8), // (0x1) SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:8:1
-                38: XorSmallImmediate {
+                40: XorSmallImmediate {
                     dest: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                     lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
                     rhs: 0x1,
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                39: Return,
+                41: Return,
             ],
             ..
         },
-        pc: 39,
+        pc: 41,
         memory_write_log: [],
         memories: StatePart {
             value: [],