diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs index 002161e..45691ea 100644 --- a/crates/fayalite/src/sim.rs +++ b/crates/fayalite/src/sim.rs @@ -1295,10 +1295,16 @@ impl SimulationModuleState { if !self.uninitialized_ios.is_empty() { match which_module { WhichModule::Main => { - panic!("can't read from an output before initializing all inputs"); + panic!( + "can't read from an output before initializing all inputs\nuninitialized_ios={:#?}", + SortedSetDebug(&self.uninitialized_ios), + ); } WhichModule::Extern { .. } => { - panic!("can't read from an input before initializing all outputs"); + panic!( + "can't read from an input before initializing all outputs\nuninitialized_ios={:#?}", + SortedSetDebug(&self.uninitialized_ios), + ); } } } diff --git a/crates/fayalite/src/sim/compiler.rs b/crates/fayalite/src/sim/compiler.rs index 07621c5..e85ff0f 100644 --- a/crates/fayalite/src/sim/compiler.rs +++ b/crates/fayalite/src/sim/compiler.rs @@ -4087,6 +4087,15 @@ impl Compiler { let init = self.compiled_expr_to_value(init, reg.source_location()); (reg.clock_domain().rst, init) }); + + // next value defaults to current value + self.compile_simple_connect( + [].intern_slice(), + value.into(), + value, + reg.source_location(), + ); + self.compile_reg( clk, reset_and_init, diff --git a/crates/fayalite/tests/sim.rs b/crates/fayalite/tests/sim.rs index cbe0b58..e57c064 100644 --- a/crates/fayalite/tests/sim.rs +++ b/crates/fayalite/tests/sim.rs @@ -7,7 +7,7 @@ use fayalite::{ prelude::*, reset::ResetType, sim::vcd::VcdWriterDecls, - util::RcWriter, + util::{RcWriter, ready_valid::queue}, }; use std::{collections::BTreeMap, num::NonZeroUsize, rc::Rc}; @@ -2495,3 +2495,349 @@ fn test_sim_read_past() { panic!(); } } + +#[hdl_module(outline_generated)] +pub fn last_connect() { + #[hdl] + let inp: HdlOption> = m.input(); + #[hdl] + let out: HdlOption> = m.output(); + connect(out, HdlNone()); + #[hdl] + if let HdlSome(v) = inp { + #[hdl] + let w = wire(); + connect(out, HdlSome(w)); + connect(w, v.len() as u8); + for (i, v) in v.into_iter().enumerate() { + #[hdl] + if v { + connect(w, i as u8); + } + } + } +} + +#[hdl] +#[test] +fn test_last_connect() { + let _n = SourceLocation::normalize_files_for_tests(); + let mut sim = Simulation::new(last_connect()); + let mut writer = RcWriter::default(); + sim.add_trace_writer(VcdWriterDecls::new(writer.clone())); + let bools = [false, true]; + sim.write(sim.io().inp, HdlNone()); + sim.advance_time(SimDuration::from_micros(1)); + let expected: SimValue>> = #[hdl(sim)] + HdlNone(); + assert_eq!(sim.read(sim.io().out), expected); + for a in bools { + for b in bools { + for c in bools { + for d in bools { + let inp = [a, b, c, d]; + sim.write(sim.io().inp, HdlSome(inp)); + sim.advance_time(SimDuration::from_micros(1)); + let mut expected = inp.len() as u8; + for (i, v) in inp.into_iter().enumerate() { + if v { + expected = i as u8; + } + } + let expected: SimValue>> = #[hdl(sim)] + HdlSome(expected); + let out = sim.read(sim.io().out); + println!("expected={expected:?} out={out:?} inp={inp:?}"); + assert_eq!(expected, out); + } + } + } + } + sim.flush_traces().unwrap(); + let vcd = String::from_utf8(writer.take()).unwrap(); + println!("####### VCD:\n{vcd}\n#######"); + if vcd != include_str!("sim/expected/last_connect.vcd") { + panic!(); + } + let sim_debug = format!("{sim:#?}"); + println!("#######\n{sim_debug}\n#######"); + if sim_debug != include_str!("sim/expected/last_connect.txt") { + panic!(); + } +} + +#[track_caller] +#[hdl] +fn test_queue_helper( + capacity: usize, + inp_ready_is_comb: bool, + out_valid_is_comb: bool, + expected_vcd: &str, + expected_sim_debug: &str, +) { + let _n = SourceLocation::normalize_files_for_tests(); + let mut sim = Simulation::new(queue( + UInt::<8>::new_static(), + NonZeroUsize::new(capacity).expect("capacity should be non-zero"), + inp_ready_is_comb, + out_valid_is_comb, + )); + let writer = RcWriter::default(); + sim.add_trace_writer(VcdWriterDecls::new(writer.clone())); + struct DumpVcdOnDrop { + writer: Option, + } + impl Drop for DumpVcdOnDrop { + fn drop(&mut self) { + if let Some(mut writer) = self.writer.take() { + let vcd = String::from_utf8(writer.take()).unwrap(); + println!("####### VCD:\n{vcd}\n#######"); + } + } + } + let mut writer = DumpVcdOnDrop { + writer: Some(writer), + }; + sim.write_clock(sim.io().cd.clk, false); + sim.write_reset(sim.io().cd.rst, true); + let mut input_value = 0u8; + let mut expected_output_value = 0u8; + /// deterministic random numbers + fn rand(mut v: u32) -> bool { + // random 32-bit primes + v = v.wrapping_mul(0xF807B7EF).rotate_left(16); + v ^= 0xA1E24BBA; // random 32-bit constant + v = v.wrapping_mul(0xE9D30017).rotate_left(16); + v = v.wrapping_mul(0x3895AFFB).rotate_left(16); + v & 1 != 0 + } + for cycle in 0..100u32 { + println!("cycle: {cycle}"); + sim.write( + sim.io().inp.data, + if rand(cycle) { + #[hdl(sim)] + HdlSome(input_value) + } else { + #[hdl(sim)] + HdlNone() + }, + ); + sim.write_bool(sim.io().out.ready, rand(u32::MAX / 2 + cycle)); + sim.advance_time(SimDuration::from_nanos(500)); + if !sim.read_reset(sim.io().cd.rst) { + let inp_ready = sim.read_bool(sim.io().inp.ready); + if inp_ready { + #[hdl(sim)] + if let HdlSome(v) = sim.read(sim.io().inp.data) { + println!("enqueued {v}, expected {input_value:#x}"); + assert_eq!(v.as_int(), input_value); + input_value = input_value.wrapping_add(1); + } + } + let out_valid = #[hdl(sim)] + if let HdlSome(v) = sim.read(sim.io().out.data) { + if sim.read_bool(sim.io().out.ready) { + println!("dequeued {v}, expected {expected_output_value:#x}"); + assert_eq!(v.as_int(), expected_output_value); + expected_output_value = expected_output_value.wrapping_add(1); + } + true + } else { + false + }; + assert!(inp_ready || out_valid, "queue isn't making progress"); + } + sim.write_clock(sim.io().cd.clk, true); + sim.advance_time(SimDuration::from_nanos(500)); + sim.write_clock(sim.io().cd.clk, false); + sim.write_reset(sim.io().cd.rst, false); + } + sim.flush_traces().unwrap(); + let vcd = String::from_utf8(writer.writer.take().unwrap().take()).unwrap(); + println!("####### VCD:\n{vcd}\n#######"); + if vcd != expected_vcd { + panic!(); + } + let sim_debug = format!("{sim:#?}"); + println!("#######\n{sim_debug}\n#######"); + if sim_debug != expected_sim_debug { + panic!(); + } +} + +#[test] +fn test_queue_1_false_false() { + test_queue_helper( + 1, + false, + false, + include_str!("sim/expected/queue_1_false_false.vcd"), + include_str!("sim/expected/queue_1_false_false.txt"), + ); +} + +#[test] +fn test_queue_1_false_true() { + test_queue_helper( + 1, + false, + true, + include_str!("sim/expected/queue_1_false_true.vcd"), + include_str!("sim/expected/queue_1_false_true.txt"), + ); +} + +#[test] +fn test_queue_1_true_false() { + test_queue_helper( + 1, + true, + false, + include_str!("sim/expected/queue_1_true_false.vcd"), + include_str!("sim/expected/queue_1_true_false.txt"), + ); +} + +#[test] +fn test_queue_1_true_true() { + test_queue_helper( + 1, + true, + true, + include_str!("sim/expected/queue_1_true_true.vcd"), + include_str!("sim/expected/queue_1_true_true.txt"), + ); +} + +#[test] +fn test_queue_2_false_false() { + test_queue_helper( + 2, + false, + false, + include_str!("sim/expected/queue_2_false_false.vcd"), + include_str!("sim/expected/queue_2_false_false.txt"), + ); +} + +#[test] +fn test_queue_2_false_true() { + test_queue_helper( + 2, + false, + true, + include_str!("sim/expected/queue_2_false_true.vcd"), + include_str!("sim/expected/queue_2_false_true.txt"), + ); +} + +#[test] +fn test_queue_2_true_false() { + test_queue_helper( + 2, + true, + false, + include_str!("sim/expected/queue_2_true_false.vcd"), + include_str!("sim/expected/queue_2_true_false.txt"), + ); +} + +#[test] +fn test_queue_2_true_true() { + test_queue_helper( + 2, + true, + true, + include_str!("sim/expected/queue_2_true_true.vcd"), + include_str!("sim/expected/queue_2_true_true.txt"), + ); +} + +#[test] +fn test_queue_3_false_false() { + test_queue_helper( + 3, + false, + false, + include_str!("sim/expected/queue_3_false_false.vcd"), + include_str!("sim/expected/queue_3_false_false.txt"), + ); +} + +#[test] +fn test_queue_3_false_true() { + test_queue_helper( + 3, + false, + true, + include_str!("sim/expected/queue_3_false_true.vcd"), + include_str!("sim/expected/queue_3_false_true.txt"), + ); +} + +#[test] +fn test_queue_3_true_false() { + test_queue_helper( + 3, + true, + false, + include_str!("sim/expected/queue_3_true_false.vcd"), + include_str!("sim/expected/queue_3_true_false.txt"), + ); +} + +#[test] +fn test_queue_3_true_true() { + test_queue_helper( + 3, + true, + true, + include_str!("sim/expected/queue_3_true_true.vcd"), + include_str!("sim/expected/queue_3_true_true.txt"), + ); +} + +#[test] +fn test_queue_4_false_false() { + test_queue_helper( + 4, + false, + false, + include_str!("sim/expected/queue_4_false_false.vcd"), + include_str!("sim/expected/queue_4_false_false.txt"), + ); +} + +#[test] +fn test_queue_4_false_true() { + test_queue_helper( + 4, + false, + true, + include_str!("sim/expected/queue_4_false_true.vcd"), + include_str!("sim/expected/queue_4_false_true.txt"), + ); +} + +#[test] +fn test_queue_4_true_false() { + test_queue_helper( + 4, + true, + false, + include_str!("sim/expected/queue_4_true_false.vcd"), + include_str!("sim/expected/queue_4_true_false.txt"), + ); +} + +#[test] +fn test_queue_4_true_true() { + test_queue_helper( + 4, + true, + true, + include_str!("sim/expected/queue_4_true_true.vcd"), + include_str!("sim/expected/queue_4_true_true.txt"), + ); +} diff --git a/crates/fayalite/tests/sim/expected/counter_async.txt b/crates/fayalite/tests/sim/expected/counter_async.txt index 86bde88..2bdd665 100644 --- a/crates/fayalite/tests/sim/expected/counter_async.txt +++ b/crates/fayalite/tests/sim/expected/counter_async.txt @@ -123,58 +123,62 @@ Simulation { dest: StatePartIndex(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, src: StatePartIndex(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> }, }, + 8: Copy { + dest: StatePartIndex(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> }, + src: StatePartIndex(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, + }, // at: module-XXXXXXXXXX.rs:1:1 - 8: Add { + 9: Add { dest: StatePartIndex(8), // (0x4) SlotDebugData { name: "", ty: UInt<5> }, lhs: StatePartIndex(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, rhs: StatePartIndex(7), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, }, - 9: CastToUInt { + 10: CastToUInt { dest: StatePartIndex(9), // (0x4) SlotDebugData { name: "", ty: UInt<4> }, src: StatePartIndex(8), // (0x4) SlotDebugData { name: "", ty: UInt<5> }, dest_width: 4, }, // at: module-XXXXXXXXXX.rs:4:1 - 10: Copy { + 11: Copy { dest: StatePartIndex(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> }, src: StatePartIndex(9), // (0x4) SlotDebugData { name: "", ty: UInt<4> }, }, // at: module-XXXXXXXXXX.rs:6:1 - 11: Copy { + 12: Copy { dest: StatePartIndex(2), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count", ty: UInt<4> }, src: StatePartIndex(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, }, // at: module-XXXXXXXXXX.rs:3:1 - 12: BranchIfSmallNonZero { - target: 16, + 13: BranchIfSmallNonZero { + target: 17, value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 13: BranchIfSmallZero { - target: 17, + 14: BranchIfSmallZero { + target: 18, value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 14: Copy { + 15: Copy { dest: StatePartIndex(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, src: StatePartIndex(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> }, }, - 15: Branch { - target: 17, + 16: Branch { + target: 18, }, - 16: Copy { + 17: Copy { dest: StatePartIndex(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, src: StatePartIndex(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> }, }, - 17: XorSmallImmediate { + 18: XorSmallImmediate { dest: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, rhs: 0x1, }, // at: module-XXXXXXXXXX.rs:1:1 - 18: Return, + 19: Return, ], .. }, - pc: 18, + pc: 19, memory_write_log: [], memories: StatePart { value: [], diff --git a/crates/fayalite/tests/sim/expected/counter_sync.txt b/crates/fayalite/tests/sim/expected/counter_sync.txt index 0a7517e..87c2098 100644 --- a/crates/fayalite/tests/sim/expected/counter_sync.txt +++ b/crates/fayalite/tests/sim/expected/counter_sync.txt @@ -102,61 +102,65 @@ Simulation { src: StatePartIndex(7), // (0x4) SlotDebugData { name: "", ty: UInt<5> }, dest_width: 4, }, - // at: module-XXXXXXXXXX.rs:4:1 - 4: Copy { - dest: StatePartIndex(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> }, - src: StatePartIndex(8), // (0x4) SlotDebugData { name: "", ty: UInt<4> }, - }, // at: module-XXXXXXXXXX.rs:3:1 - 5: IsNonZeroDestIsSmall { + 4: IsNonZeroDestIsSmall { dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: SyncReset }, }, - 6: IsNonZeroDestIsSmall { + 5: IsNonZeroDestIsSmall { dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(0), // (0x1) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock }, }, - 7: AndSmall { + 6: AndSmall { dest: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, rhs: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, + 7: Copy { + dest: StatePartIndex(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> }, + src: StatePartIndex(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, + }, + // at: module-XXXXXXXXXX.rs:4:1 + 8: Copy { + dest: StatePartIndex(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> }, + src: StatePartIndex(8), // (0x4) SlotDebugData { name: "", ty: UInt<4> }, + }, // at: module-XXXXXXXXXX.rs:1:1 - 8: Const { + 9: Const { dest: StatePartIndex(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> }, value: 0x3, }, // at: module-XXXXXXXXXX.rs:3:1 - 9: BranchIfSmallZero { - target: 14, + 10: BranchIfSmallZero { + target: 15, value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 10: BranchIfSmallNonZero { - target: 13, + 11: BranchIfSmallNonZero { + target: 14, value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 11: Copy { + 12: Copy { dest: StatePartIndex(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, src: StatePartIndex(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> }, }, - 12: Branch { - target: 14, + 13: Branch { + target: 15, }, - 13: Copy { + 14: Copy { dest: StatePartIndex(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, src: StatePartIndex(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> }, }, - 14: XorSmallImmediate { + 15: XorSmallImmediate { dest: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, rhs: 0x1, }, // at: module-XXXXXXXXXX.rs:1:1 - 15: Return, + 16: Return, ], .. }, - pc: 15, + pc: 16, memory_write_log: [], memories: StatePart { value: [], diff --git a/crates/fayalite/tests/sim/expected/enums.txt b/crates/fayalite/tests/sim/expected/enums.txt index a193e92..a3a52cb 100644 --- a/crates/fayalite/tests/sim/expected/enums.txt +++ b/crates/fayalite/tests/sim/expected/enums.txt @@ -1012,173 +1012,177 @@ Simulation { lhs: StatePartIndex(4), // (0x1 1) SlotDebugData { name: "", ty: Bool }, rhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, + 99: Copy { + dest: StatePartIndex(24), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, + src: StatePartIndex(23), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, + }, // at: module-XXXXXXXXXX.rs:1:1 - 99: Const { + 100: Const { dest: StatePartIndex(25), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, value: 0x0, }, - 100: Copy { + 101: Copy { dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, src: StatePartIndex(25), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, }, // at: module-XXXXXXXXXX.rs:12:1 - 101: BranchIfZero { - target: 109, + 102: BranchIfZero { + target: 110, value: StatePartIndex(2), // (0x1) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::en", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:13:1 - 102: BranchIfZero { - target: 104, + 103: BranchIfZero { + target: 105, value: StatePartIndex(46), // (0x0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:14:1 - 103: Copy { + 104: Copy { dest: StatePartIndex(24), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, src: StatePartIndex(26), // (0x0) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, }, // at: module-XXXXXXXXXX.rs:13:1 - 104: BranchIfNonZero { - target: 109, + 105: BranchIfNonZero { + target: 110, value: StatePartIndex(46), // (0x0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:15:1 - 105: BranchIfZero { - target: 107, + 106: BranchIfZero { + target: 108, value: StatePartIndex(48), // (0x0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:16:1 - 106: Copy { + 107: Copy { dest: StatePartIndex(24), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, src: StatePartIndex(65), // (0xd) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, }, // at: module-XXXXXXXXXX.rs:15:1 - 107: BranchIfNonZero { - target: 109, + 108: BranchIfNonZero { + target: 110, value: StatePartIndex(48), // (0x0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:17:1 - 108: Copy { + 109: Copy { dest: StatePartIndex(24), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, src: StatePartIndex(87), // (0x3e) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, }, // at: module-XXXXXXXXXX.rs:10:1 - 109: Copy { + 110: Copy { dest: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b2_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} }, src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} }, }, // at: module-XXXXXXXXXX.rs:1:1 - 110: Copy { + 111: Copy { dest: StatePartIndex(18), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, src: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b2_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} }, }, - 111: SliceInt { + 112: SliceInt { dest: StatePartIndex(19), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, src: StatePartIndex(18), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, start: 1, len: 2, }, - 112: SliceInt { + 113: SliceInt { dest: StatePartIndex(20), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, src: StatePartIndex(19), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, start: 0, len: 1, }, - 113: SliceInt { + 114: SliceInt { dest: StatePartIndex(21), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, src: StatePartIndex(19), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, start: 1, len: 1, }, - 114: Copy { + 115: Copy { dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(21), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, }, - 115: Copy { + 116: Copy { dest: StatePartIndex(16), // (0x0) SlotDebugData { name: ".0", ty: UInt<1> }, src: StatePartIndex(20), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, }, - 116: Copy { + 117: Copy { dest: StatePartIndex(17), // (0x0) SlotDebugData { name: ".1", ty: Bool }, src: StatePartIndex(22), // (0x0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:9:1 - 117: AndBigWithSmallImmediate { + 118: AndBigWithSmallImmediate { dest: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, lhs: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b2_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} }, rhs: 0x1, }, // at: module-XXXXXXXXXX.rs:1:1 - 118: Copy { + 119: Copy { dest: StatePartIndex(10), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} }, }, - 119: SliceInt { + 120: SliceInt { dest: StatePartIndex(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, src: StatePartIndex(10), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, start: 1, len: 2, }, - 120: SliceInt { + 121: SliceInt { dest: StatePartIndex(12), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, src: StatePartIndex(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, start: 0, len: 1, }, - 121: SliceInt { + 122: SliceInt { dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, src: StatePartIndex(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, start: 1, len: 1, }, - 122: Copy { + 123: Copy { dest: StatePartIndex(14), // (0x0) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(13), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, }, - 123: Copy { + 124: Copy { dest: StatePartIndex(8), // (0x0) SlotDebugData { name: ".0", ty: UInt<1> }, src: StatePartIndex(12), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, }, - 124: Copy { + 125: Copy { dest: StatePartIndex(9), // (0x0) SlotDebugData { name: ".1", ty: Bool }, src: StatePartIndex(14), // (0x0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:8:1 - 125: AndBigWithSmallImmediate { + 126: AndBigWithSmallImmediate { dest: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, lhs: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} }, rhs: 0x1, }, // at: module-XXXXXXXXXX.rs:11:1 - 126: BranchIfSmallZero { - target: 131, + 127: BranchIfSmallZero { + target: 132, value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 127: BranchIfSmallNonZero { - target: 130, + 128: BranchIfSmallNonZero { + target: 131, value: StatePartIndex(5), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 128: Copy { + 129: Copy { dest: StatePartIndex(23), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, src: StatePartIndex(24), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, }, - 129: Branch { - target: 131, + 130: Branch { + target: 132, }, - 130: Copy { + 131: Copy { dest: StatePartIndex(23), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, src: StatePartIndex(26), // (0x0) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, }, - 131: XorSmallImmediate { + 132: XorSmallImmediate { dest: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Bool }, lhs: StatePartIndex(4), // (0x1 1) SlotDebugData { name: "", ty: Bool }, rhs: 0x1, }, // at: module-XXXXXXXXXX.rs:1:1 - 132: Return, + 133: Return, ], .. }, - pc: 132, + pc: 133, memory_write_log: [], memories: StatePart { value: [], diff --git a/crates/fayalite/tests/sim/expected/last_connect.txt b/crates/fayalite/tests/sim/expected/last_connect.txt new file mode 100644 index 0000000..6a43497 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/last_connect.txt @@ -0,0 +1,701 @@ +Simulation { + state: State { + insns: Insns { + state_layout: StateLayout { + ty: TypeLayout { + small_slots: StatePartLayout { + len: 2, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 33, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(last_connect: last_connect).last_connect::inp", + ty: Enum { + HdlNone, + HdlSome(Array), + }, + }, + SlotDebugData { + name: "[0]", + ty: Bool, + }, + SlotDebugData { + name: "[1]", + ty: Bool, + }, + SlotDebugData { + name: "[2]", + ty: Bool, + }, + SlotDebugData { + name: "[3]", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<5>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(last_connect: last_connect).last_connect::out", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(last_connect: last_connect).last_connect::w", + ty: UInt<8>, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + insns: [ + // at: module-XXXXXXXXXX.rs:1:1 + 0: Const { + dest: StatePartIndex(32), // (0x3) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x3, + }, + 1: Const { + dest: StatePartIndex(31), // (0x2) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x2, + }, + 2: Const { + dest: StatePartIndex(30), // (0x1) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x1, + }, + 3: Const { + dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + 4: Const { + dest: StatePartIndex(28), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x4, + }, + // at: module-XXXXXXXXXX.rs:8:1 + 5: Copy { + dest: StatePartIndex(20), // (0x3) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::w", ty: UInt<8> }, + src: StatePartIndex(28), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: module-XXXXXXXXXX.rs:1:1 + 6: Const { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 7: Const { + dest: StatePartIndex(18), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + value: 0x0, + }, + 8: Copy { + dest: StatePartIndex(19), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(18), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: module-XXXXXXXXXX.rs:4:1 + 9: Copy { + dest: StatePartIndex(15), // (0x7) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::out", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(19), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: module-XXXXXXXXXX.rs:1:1 + 10: Copy { + dest: StatePartIndex(5), // (0x1f) SlotDebugData { name: "", ty: UInt<5> }, + src: StatePartIndex(0), // (0x1f) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::inp", ty: Enum {HdlNone, HdlSome(Array)} }, + }, + 11: SliceInt { + dest: StatePartIndex(6), // (0xf) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(5), // (0x1f) SlotDebugData { name: "", ty: UInt<5> }, + start: 1, + len: 4, + }, + 12: SliceInt { + dest: StatePartIndex(7), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(6), // (0xf) SlotDebugData { name: "", ty: UInt<4> }, + start: 0, + len: 1, + }, + 13: Copy { + dest: StatePartIndex(8), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(7), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 14: SliceInt { + dest: StatePartIndex(9), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(6), // (0xf) SlotDebugData { name: "", ty: UInt<4> }, + start: 1, + len: 1, + }, + 15: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(9), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 16: SliceInt { + dest: StatePartIndex(11), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(6), // (0xf) SlotDebugData { name: "", ty: UInt<4> }, + start: 2, + len: 1, + }, + 17: Copy { + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(11), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 18: SliceInt { + dest: StatePartIndex(13), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(6), // (0xf) SlotDebugData { name: "", ty: UInt<4> }, + start: 3, + len: 1, + }, + 19: Copy { + dest: StatePartIndex(14), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(13), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 20: Copy { + dest: StatePartIndex(1), // (0x1) SlotDebugData { name: "[0]", ty: Bool }, + src: StatePartIndex(8), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 21: Copy { + dest: StatePartIndex(2), // (0x1) SlotDebugData { name: "[1]", ty: Bool }, + src: StatePartIndex(10), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 22: Copy { + dest: StatePartIndex(3), // (0x1) SlotDebugData { name: "[2]", ty: Bool }, + src: StatePartIndex(12), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 23: Copy { + dest: StatePartIndex(4), // (0x1) SlotDebugData { name: "[3]", ty: Bool }, + src: StatePartIndex(14), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:9:1 + 24: BranchIfZero { + target: 26, + value: StatePartIndex(1), // (0x1) SlotDebugData { name: "[0]", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:10:1 + 25: Copy { + dest: StatePartIndex(20), // (0x3) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::w", ty: UInt<8> }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: module-XXXXXXXXXX.rs:9:1 + 26: BranchIfZero { + target: 28, + value: StatePartIndex(2), // (0x1) SlotDebugData { name: "[1]", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:10:1 + 27: Copy { + dest: StatePartIndex(20), // (0x3) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::w", ty: UInt<8> }, + src: StatePartIndex(30), // (0x1) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: module-XXXXXXXXXX.rs:9:1 + 28: BranchIfZero { + target: 30, + value: StatePartIndex(3), // (0x1) SlotDebugData { name: "[2]", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:10:1 + 29: Copy { + dest: StatePartIndex(20), // (0x3) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::w", ty: UInt<8> }, + src: StatePartIndex(31), // (0x2) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: module-XXXXXXXXXX.rs:9:1 + 30: BranchIfZero { + target: 32, + value: StatePartIndex(4), // (0x1) SlotDebugData { name: "[3]", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:10:1 + 31: Copy { + dest: StatePartIndex(20), // (0x3) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::w", ty: UInt<8> }, + src: StatePartIndex(32), // (0x3) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: module-XXXXXXXXXX.rs:1:1 + 32: Copy { + dest: StatePartIndex(21), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(23), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 33: Copy { + dest: StatePartIndex(22), // (0x3) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(20), // (0x3) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::w", ty: UInt<8> }, + }, + 34: Shl { + dest: StatePartIndex(24), // (0x6) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(22), // (0x3) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 1, + }, + 35: Or { + dest: StatePartIndex(25), // (0x7) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(21), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(24), // (0x6) SlotDebugData { name: "", ty: UInt<9> }, + }, + 36: CastToUInt { + dest: StatePartIndex(26), // (0x7) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(25), // (0x7) SlotDebugData { name: "", ty: UInt<9> }, + dest_width: 9, + }, + 37: Copy { + dest: StatePartIndex(27), // (0x7) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(26), // (0x7) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: module-XXXXXXXXXX.rs:2:1 + 38: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(0), // (0x1f) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::inp", ty: Enum {HdlNone, HdlSome(Array)} }, + rhs: 0x1, + }, + // at: module-XXXXXXXXXX.rs:5:1 + 39: BranchIfSmallNeImmediate { + target: 41, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: module-XXXXXXXXXX.rs:7:1 + 40: Copy { + dest: StatePartIndex(15), // (0x7) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::out", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(27), // (0x7) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: module-XXXXXXXXXX.rs:3:1 + 41: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(15), // (0x7) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::out", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: module-XXXXXXXXXX.rs:1:1 + 42: Copy { + dest: StatePartIndex(16), // (0x7) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(15), // (0x7) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::out", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 43: SliceInt { + dest: StatePartIndex(17), // (0x3) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(16), // (0x7) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + 44: Return, + ], + .. + }, + pc: 44, + memory_write_log: [], + memories: StatePart { + value: [], + }, + small_slots: StatePart { + value: [ + 1, + 1, + ], + }, + big_slots: StatePart { + value: [ + 31, + 1, + 1, + 1, + 1, + 31, + 15, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 7, + 7, + 3, + 0, + 0, + 3, + 1, + 3, + 1, + 6, + 7, + 7, + 7, + 4, + 0, + 1, + 2, + 3, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::last_connect, + instantiated: Module { + name: last_connect, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::last_connect, + instantiated: Module { + name: last_connect, + .. + }, + }.inp, + Instance { + name: ::last_connect, + instantiated: Module { + name: last_connect, + .. + }, + }.out, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::last_connect, + instantiated: Module { + name: last_connect, + .. + }, + }.inp, + Instance { + name: ::last_connect, + instantiated: Module { + name: last_connect, + .. + }, + }.out, + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "last_connect", + children: [ + TraceModuleIO { + name: "inp", + child: TraceEnumWithFields { + name: "inp", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(0), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Array), + }, + flow: Source, + }, + non_empty_fields: [ + TraceArray { + name: "HdlSome", + elements: [ + TraceBool { + location: TraceScalarId(1), + name: "[0]", + flow: Source, + }, + TraceBool { + location: TraceScalarId(2), + name: "[1]", + flow: Source, + }, + TraceBool { + location: TraceScalarId(3), + name: "[2]", + flow: Source, + }, + TraceBool { + location: TraceScalarId(4), + name: "[3]", + flow: Source, + }, + ], + ty: Array, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Array), + }, + flow: Source, + }, + ty: Enum { + HdlNone, + HdlSome(Array), + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceEnumWithFields { + name: "out", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(5), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(6), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + TraceWire { + name: "w", + child: TraceUInt { + location: TraceScalarId(7), + name: "w", + ty: UInt<8>, + flow: Duplex, + }, + ty: UInt<8>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + HdlNone, + HdlSome(Array), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigBool { + index: StatePartIndex(1), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(2), + kind: BigBool { + index: StatePartIndex(2), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigBool { + index: StatePartIndex(3), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigBool { + index: StatePartIndex(4), + }, + state: 0x1, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(5), + kind: EnumDiscriminant { + index: StatePartIndex(1), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(17), + ty: UInt<8>, + }, + state: 0x03, + last_state: 0x02, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigUInt { + index: StatePartIndex(20), + ty: UInt<8>, + }, + state: 0x03, + last_state: 0x02, + }, + ], + trace_memories: {}, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [], + event_queue: EventQueue(EventQueueData { + instant: 17 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/last_connect.vcd b/crates/fayalite/tests/sim/expected/last_connect.vcd new file mode 100644 index 0000000..b8b2f56 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/last_connect.vcd @@ -0,0 +1,104 @@ +$timescale 1 ps $end +$scope module last_connect $end +$scope struct inp $end +$var string 1 !C&}* \$tag $end +$scope struct HdlSome $end +$var wire 1 D_viZ \[0] $end +$var wire 1 b5gFK \[1] $end +$var wire 1 xUBRH \[2] $end +$var wire 1 Gp7Xm \[3] $end +$upscope $end +$upscope $end +$scope struct out $end +$var string 1 ^Z_p3 \$tag $end +$var wire 8 rz~), HdlSome $end +$upscope $end +$var wire 8 dlea> w $end +$upscope $end +$enddefinitions $end +$dumpvars +sHdlNone\x20(0) !C&}* +0D_viZ +0b5gFK +0xUBRH +0Gp7Xm +sHdlNone\x20(0) ^Z_p3 +b0 rz~), +b100 dlea> +$end +#1000000 +sHdlSome\x20(1) !C&}* +sHdlSome\x20(1) ^Z_p3 +b100 rz~), +#2000000 +1Gp7Xm +b11 rz~), +b11 dlea> +#3000000 +1xUBRH +0Gp7Xm +b10 rz~), +b10 dlea> +#4000000 +1Gp7Xm +b11 rz~), +b11 dlea> +#5000000 +1b5gFK +0xUBRH +0Gp7Xm +b1 rz~), +b1 dlea> +#6000000 +1Gp7Xm +b11 rz~), +b11 dlea> +#7000000 +1xUBRH +0Gp7Xm +b10 rz~), +b10 dlea> +#8000000 +1Gp7Xm +b11 rz~), +b11 dlea> +#9000000 +1D_viZ +0b5gFK +0xUBRH +0Gp7Xm +b0 rz~), +b0 dlea> +#10000000 +1Gp7Xm +b11 rz~), +b11 dlea> +#11000000 +1xUBRH +0Gp7Xm +b10 rz~), +b10 dlea> +#12000000 +1Gp7Xm +b11 rz~), +b11 dlea> +#13000000 +1b5gFK +0xUBRH +0Gp7Xm +b1 rz~), +b1 dlea> +#14000000 +1Gp7Xm +b11 rz~), +b11 dlea> +#15000000 +1xUBRH +0Gp7Xm +b10 rz~), +b10 dlea> +#16000000 +1Gp7Xm +b11 rz~), +b11 dlea> +#17000000 diff --git a/crates/fayalite/tests/sim/expected/queue_1_false_false.txt b/crates/fayalite/tests/sim/expected/queue_1_false_false.txt new file mode 100644 index 0000000..570c08d --- /dev/null +++ b/crates/fayalite/tests/sim/expected/queue_1_false_false.txt @@ -0,0 +1,2134 @@ +Simulation { + state: State { + insns: Insns { + state_layout: StateLayout { + ty: TypeLayout { + small_slots: StatePartLayout { + len: 18, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 70, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::indexes_equal", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::empty", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::full", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count_lower", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 1, + debug_data: [ + (), + ], + layout_data: [ + MemoryData { + array_type: Array, 1>, + data: [ + // len = 0x1 + [0x0]: 0x00, + ], + }, + ], + .. + }, + }, + insns: [ + // at: ready_valid.rs:64:1 + 0: SubU { + dest: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + dest_width: 1, + }, + 1: CastToUInt { + dest: StatePartIndex(68), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 0, + }, + // at: ready_valid.rs:178:13 + 2: Copy { + dest: StatePartIndex(66), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<0> }, + src: StatePartIndex(68), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:64:1 + 3: CastToUInt { + dest: StatePartIndex(69), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(66), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<0> }, + dest_width: 1, + }, + 4: Const { + dest: StatePartIndex(63), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x1, + }, + 5: CastToUInt { + dest: StatePartIndex(64), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(63), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + dest_width: 1, + }, + 6: Const { + dest: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x0, + }, + 7: CmpEq { + dest: StatePartIndex(57), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + }, + 8: CmpEq { + dest: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + }, + 9: Const { + dest: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + value: 0x0, + }, + 10: Copy { + dest: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + }, + 11: Const { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 12: Add { + dest: StatePartIndex(58), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 13: CastToUInt { + dest: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(58), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 0, + }, + 14: Add { + dest: StatePartIndex(61), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 15: CastToUInt { + dest: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(61), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 0, + }, + 16: Const { + dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:118:30 + 17: Copy { + dest: StatePartIndex(42), // (0x19) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:117:5 + 18: Copy { + dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:115:5 + 19: Copy { + dest: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<0> }, + src: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:114:5 + 20: Copy { + dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:64:1 + 21: Const { + dest: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + value: 0x1, + }, + // at: ready_valid.rs:113:5 + 22: Copy { + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:119:5 + 23: Copy { + dest: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:112:5 + 24: Copy { + dest: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<0> }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:64:1 + 25: NotU { + dest: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + width: 1, + }, + 26: CmpEq { + dest: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:104:5 + 27: Copy { + dest: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + src: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 28: And { + dest: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:107:5 + 29: Copy { + dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + src: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 30: NotU { + dest: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + width: 1, + }, + 31: And { + dest: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:110:5 + 32: Copy { + dest: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + src: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 33: NotU { + dest: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + width: 1, + }, + // at: ready_valid.rs:121:5 + 34: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:166:5 + 35: BranchIfZero { + target: 38, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 36: BranchIfZero { + target: 38, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:169:13 + 37: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<1> }, + src: StatePartIndex(64), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:88:26 + 38: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 39: Const { + dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, + }, + // at: ready_valid.rs:86:25 + 40: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:84:31 + 41: IsNonZeroDestIsSmall { + dest: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.rst", ty: SyncReset }, + }, + 42: IsNonZeroDestIsSmall { + dest: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + 43: AndSmall { + dest: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 44: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:64:1 + 45: Const { + dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + value: 0x0, + }, + 46: CastToUInt { + dest: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 1, + }, + // at: ready_valid.rs:166:5 + 47: BranchIfZero { + target: 50, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 48: BranchIfNonZero { + target: 50, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:171:13 + 49: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<1> }, + src: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:166:5 + 50: BranchIfNonZero { + target: 52, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:182:13 + 51: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<1> }, + src: StatePartIndex(69), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:91:19 + 52: CastBigToArrayIndex { + dest: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<0> }, + }, + 53: IsNonZeroDestIsSmall { + dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + }, + 54: AndSmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 55: CastBigToArrayIndex { + dest: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<0> }, + }, + 56: IsNonZeroDestIsSmall { + dest: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + }, + 57: BranchIfSmallZero { + target: 60, + value: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 58: MemoryReadUInt { + dest: StatePartIndex(14), // (0x19) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 1>, + // data: [ + // // len = 0x1 + // [0x0]: 0x19, + // ], + // }) (), + addr: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + stride: 8, + start: 0, + width: 8, + }, + 59: Branch { + target: 61, + }, + 60: Const { + dest: StatePartIndex(14), // (0x19) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:64:1 + 61: Copy { + dest: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 62: Copy { + dest: StatePartIndex(47), // (0x19) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(14), // (0x19) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + }, + 63: Shl { + dest: StatePartIndex(49), // (0x32) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(47), // (0x19) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 1, + }, + 64: Or { + dest: StatePartIndex(50), // (0x33) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(49), // (0x32) SlotDebugData { name: "", ty: UInt<9> }, + }, + 65: CastToUInt { + dest: StatePartIndex(51), // (0x33) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(50), // (0x33) SlotDebugData { name: "", ty: UInt<9> }, + dest_width: 9, + }, + 66: Copy { + dest: StatePartIndex(52), // (0x33) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(51), // (0x33) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: ready_valid.rs:130:5 + 67: BranchIfZero { + target: 69, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:131:9 + 68: Copy { + dest: StatePartIndex(6), // (0x33) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(52), // (0x33) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:130:5 + 69: BranchIfNonZero { + target: 71, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:136:13 + 70: Copy { + dest: StatePartIndex(6), // (0x33) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:91:19 + 71: IsNonZeroDestIsSmall { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + }, + 72: AndSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 73: Copy { + dest: StatePartIndex(8), // (0x33) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(6), // (0x33) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 74: SliceInt { + dest: StatePartIndex(9), // (0x19) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(8), // (0x33) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:79:32 + 75: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(6), // (0x33) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 76: BranchIfSmallNeImmediate { + target: 78, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 77: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 78: BranchIfSmallNeImmediate { + target: 80, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 79: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:101:5 + 80: Copy { + dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + src: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:156:5 + 81: BranchIfZero { + target: 86, + value: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:158:9 + 82: BranchIfZero { + target: 84, + value: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:159:13 + 83: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:158:9 + 84: BranchIfNonZero { + target: 86, + value: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:161:13 + 85: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:64:1 + 86: Copy { + dest: StatePartIndex(4), // (0x33) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(2), // (0x33) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 87: SliceInt { + dest: StatePartIndex(5), // (0x19) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(4), // (0x33) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:77:32 + 88: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2), // (0x33) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 89: BranchIfSmallNeImmediate { + target: 91, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 90: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 91: BranchIfSmallNeImmediate { + target: 93, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 92: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + }, + // at: ready_valid.rs:98:5 + 93: Copy { + dest: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + src: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:116:5 + 94: Copy { + dest: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 95: IsNonZeroDestIsSmall { + dest: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 96: CmpNe { + dest: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + rhs: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:141:5 + 97: BranchIfZero { + target: 99, + value: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:142:9 + 98: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:146:5 + 99: BranchIfZero { + target: 104, + value: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:148:9 + 100: BranchIfZero { + target: 102, + value: StatePartIndex(57), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:149:13 + 101: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:148:9 + 102: BranchIfNonZero { + target: 104, + value: StatePartIndex(57), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:151:13 + 103: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:118:30 + 104: BranchIfSmallNeImmediate { + target: 106, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + 105: Copy { + dest: StatePartIndex(42), // (0x19) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(5), // (0x19) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:118:5 + 106: Copy { + dest: StatePartIndex(18), // (0x19) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + src: StatePartIndex(42), // (0x19) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + }, + // at: ready_valid.rs:84:31 + 107: BranchIfSmallZero { + target: 112, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 108: BranchIfSmallNonZero { + target: 111, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 109: Copy { + dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + src: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<0> }, + }, + 110: Branch { + target: 112, + }, + 111: Copy { + dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:86:25 + 112: BranchIfSmallZero { + target: 117, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 113: BranchIfSmallNonZero { + target: 116, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 114: Copy { + dest: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + src: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<0> }, + }, + 115: Branch { + target: 117, + }, + 116: Copy { + dest: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:88:26 + 117: BranchIfSmallZero { + target: 122, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 118: BranchIfSmallNonZero { + target: 121, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 119: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + }, + 120: Branch { + target: 122, + }, + 121: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 122: BranchIfSmallZero { + target: 123, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 123: BranchIfSmallZero { + target: 131, + value: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 124: CopySmall { + dest: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + }, + 125: CopySmall { + dest: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 126: Copy { + dest: StatePartIndex(20), // (0x19) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(18), // (0x19) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + }, + 127: Copy { + dest: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + }, + 128: BranchIfSmallZero { + target: 131, + value: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 129: BranchIfZero { + target: 131, + value: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 130: MemoryWriteUInt { + value: StatePartIndex(20), // (0x19) SlotDebugData { name: "", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 1>, + // data: [ + // // len = 0x1 + // [0x0]: 0x19, + // ], + // }) (), + addr: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + stride: 8, + start: 0, + width: 8, + }, + 131: XorSmallImmediate { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 132: XorSmallImmediate { + dest: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:84:31 + 133: XorSmallImmediate { + dest: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:64:1 + 134: Return, + ], + .. + }, + pc: 134, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array, 1>, + data: [ + // len = 0x1 + [0x0]: 0x19, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 1, + 1, + 1, + 0, + 0, + 1, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 51, + 0, + 51, + 25, + 51, + 0, + 51, + 25, + 1, + 0, + 1, + 0, + 25, + 0, + 0, + 0, + 25, + 1, + 25, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 1, + 1, + 1, + 25, + 0, + 0, + 1, + 1, + 25, + 1, + 50, + 51, + 51, + 51, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 1, + 1, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.clk, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.rst, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.ready, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.ready, + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "queue", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "inp", + child: TraceBundle { + name: "inp", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(2), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(3), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(4), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceBundle { + name: "out", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(5), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(6), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(7), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + TraceModuleIO { + name: "count", + child: TraceUInt { + location: TraceScalarId(8), + name: "count", + ty: UInt<1>, + flow: Sink, + }, + ty: UInt<1>, + flow: Sink, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 1, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<0>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + #[hdl(flip)] /* offset = 2 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + #[hdl(flip)] /* offset = 2 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<0>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + /* offset = 2 */ + data: UInt<8>, + /* offset = 10 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + /* offset = 2 */ + data: UInt<8>, + /* offset = 10 */ + mask: Bool, + }, + }, + ], + array_type: Array, 1>, + }, + TraceReg { + name: "inp_index_reg", + child: TraceUInt { + location: TraceScalarId(18), + name: "inp_index_reg", + ty: UInt<0>, + flow: Duplex, + }, + ty: UInt<0>, + }, + TraceReg { + name: "out_index_reg", + child: TraceUInt { + location: TraceScalarId(19), + name: "out_index_reg", + ty: UInt<0>, + flow: Duplex, + }, + ty: UInt<0>, + }, + TraceReg { + name: "maybe_full_reg", + child: TraceBool { + location: TraceScalarId(20), + name: "maybe_full_reg", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "inp_firing", + child: TraceBool { + location: TraceScalarId(21), + name: "inp_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(22), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "out_firing", + child: TraceBool { + location: TraceScalarId(23), + name: "out_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(24), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "indexes_equal", + child: TraceBool { + location: TraceScalarId(25), + name: "indexes_equal", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "empty", + child: TraceBool { + location: TraceScalarId(26), + name: "empty", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "full", + child: TraceBool { + location: TraceScalarId(27), + name: "full", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "unwrap_or_else_out", + child: TraceUInt { + location: TraceScalarId(28), + name: "unwrap_or_else_out", + ty: UInt<8>, + flow: Duplex, + }, + ty: UInt<8>, + }, + TraceWire { + name: "count_lower", + child: TraceUInt { + location: TraceScalarId(29), + name: "count_lower", + ty: UInt<0>, + flow: Duplex, + }, + ty: UInt<0>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSyncReset { + index: StatePartIndex(1), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<8>, + }, + state: 0x19, + last_state: 0x19, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigBool { + index: StatePartIndex(3), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(5), + kind: EnumDiscriminant { + index: StatePartIndex(1), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(9), + ty: UInt<8>, + }, + state: 0x19, + last_state: 0x19, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigBool { + index: StatePartIndex(7), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigUInt { + index: StatePartIndex(10), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigUInt { + index: StatePartIndex(11), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigBool { + index: StatePartIndex(12), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigClock { + index: StatePartIndex(13), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(12), + kind: BigUInt { + index: StatePartIndex(14), + ty: UInt<8>, + }, + state: 0x19, + last_state: 0x19, + }, + SimTrace { + id: TraceScalarId(13), + kind: BigUInt { + index: StatePartIndex(15), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigBool { + index: StatePartIndex(16), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(15), + kind: BigClock { + index: StatePartIndex(17), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(16), + kind: BigUInt { + index: StatePartIndex(18), + ty: UInt<8>, + }, + state: 0x19, + last_state: 0x19, + }, + SimTrace { + id: TraceScalarId(17), + kind: BigBool { + index: StatePartIndex(19), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigUInt { + index: StatePartIndex(22), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigUInt { + index: StatePartIndex(25), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(20), + kind: BigBool { + index: StatePartIndex(27), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(21), + kind: BigBool { + index: StatePartIndex(30), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(22), + kind: BigBool { + index: StatePartIndex(31), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(23), + kind: BigBool { + index: StatePartIndex(32), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(24), + kind: BigBool { + index: StatePartIndex(33), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(25), + kind: BigBool { + index: StatePartIndex(34), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(26), + kind: BigBool { + index: StatePartIndex(36), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(27), + kind: BigBool { + index: StatePartIndex(39), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(28), + kind: BigUInt { + index: StatePartIndex(42), + ty: UInt<8>, + }, + state: 0x19, + last_state: 0x19, + }, + SimTrace { + id: TraceScalarId(29), + kind: BigUInt { + index: StatePartIndex(66), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 1, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<0>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + #[hdl(flip)] /* offset = 2 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + #[hdl(flip)] /* offset = 2 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<0>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + /* offset = 2 */ + data: UInt<8>, + /* offset = 10 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + /* offset = 2 */ + data: UInt<8>, + /* offset = 10 */ + mask: Bool, + }, + }, + ], + array_type: Array, 1>, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [ + StatePartIndex(3), + StatePartIndex(8), + StatePartIndex(15), + ], + event_queue: EventQueue(EventQueueData { + instant: 100 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_1_false_false.vcd b/crates/fayalite/tests/sim/expected/queue_1_false_false.vcd new file mode 100644 index 0000000..30dbbec --- /dev/null +++ b/crates/fayalite/tests/sim/expected/queue_1_false_false.vcd @@ -0,0 +1,1916 @@ +$timescale 1 ps $end +$scope module queue $end +$scope struct cd $end +$var wire 1 11z(a clk $end +$var wire 1 q1t|f rst $end +$upscope $end +$scope struct inp $end +$scope struct data $end +$var string 1 j|a-9 \$tag $end +$var wire 8 pjN&T HdlSome $end +$upscope $end +$var wire 1 *x8M* ready $end +$upscope $end +$scope struct out $end +$scope struct data $end +$var string 1 'Aa8} \$tag $end +$var wire 8 1b%.O HdlSome $end +$upscope $end +$var wire 1 vZD*c ready $end +$upscope $end +$var wire 1 rf7Xh count $end +$scope struct mem $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 8 (.Juw mem $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var string 0 K]Dkr addr $end +$var wire 1 P|=HX en $end +$var wire 1 z+ft% clk $end +$var wire 8 m+9ec data $end +$upscope $end +$scope struct w1 $end +$var string 0 8Oa@o addr $end +$var wire 1 VaM[2 en $end +$var wire 1 aH[{] clk $end +$var wire 8 8|1uZ data $end +$var wire 1 DYq.y mask $end +$upscope $end +$upscope $end +$var string 0 Xk?#v inp_index_reg $end +$var string 0 p19yW out_index_reg $end +$var reg 1 kEQiI maybe_full_reg $end +$var wire 1 *gdL1 inp_firing $end +$var wire 1 ;HWUJ firing $end +$var wire 1 Ph#@^ out_firing $end +$var wire 1 ;HWUJ" firing_2 $end +$var wire 1 i[~ { + len: 18, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 68, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::indexes_equal", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::empty", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::full", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count_lower", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 1, + debug_data: [ + (), + ], + layout_data: [ + MemoryData { + array_type: Array, 1>, + data: [ + // len = 0x1 + [0x0]: 0x00, + ], + }, + ], + .. + }, + }, + insns: [ + // at: ready_valid.rs:64:1 + 0: SubU { + dest: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + dest_width: 1, + }, + 1: CastToUInt { + dest: StatePartIndex(66), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 0, + }, + // at: ready_valid.rs:178:13 + 2: Copy { + dest: StatePartIndex(64), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<0> }, + src: StatePartIndex(66), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:64:1 + 3: CastToUInt { + dest: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(64), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<0> }, + dest_width: 1, + }, + 4: Const { + dest: StatePartIndex(61), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x1, + }, + 5: CastToUInt { + dest: StatePartIndex(62), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(61), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + dest_width: 1, + }, + 6: Const { + dest: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x0, + }, + 7: CmpEq { + dest: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + }, + 8: CmpEq { + dest: StatePartIndex(58), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + }, + 9: Const { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 10: Add { + dest: StatePartIndex(56), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 11: CastToUInt { + dest: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(56), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 0, + }, + 12: Add { + dest: StatePartIndex(59), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 13: CastToUInt { + dest: StatePartIndex(60), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(59), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 0, + }, + 14: Const { + dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:118:30 + 15: Copy { + dest: StatePartIndex(42), // (0x1f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:117:5 + 16: Copy { + dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:115:5 + 17: Copy { + dest: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<0> }, + src: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:114:5 + 18: Copy { + dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:64:1 + 19: Const { + dest: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + value: 0x1, + }, + // at: ready_valid.rs:113:5 + 20: Copy { + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:119:5 + 21: Copy { + dest: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:112:5 + 22: Copy { + dest: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<0> }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:64:1 + 23: NotU { + dest: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + width: 1, + }, + 24: CmpEq { + dest: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:104:5 + 25: Copy { + dest: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + src: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 26: And { + dest: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:107:5 + 27: Copy { + dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + src: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 28: NotU { + dest: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + width: 1, + }, + 29: And { + dest: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:110:5 + 30: Copy { + dest: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + src: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 31: NotU { + dest: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + width: 1, + }, + // at: ready_valid.rs:121:5 + 32: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:166:5 + 33: BranchIfZero { + target: 36, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 34: BranchIfZero { + target: 36, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:169:13 + 35: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<1> }, + src: StatePartIndex(62), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:88:26 + 36: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 37: Const { + dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, + }, + // at: ready_valid.rs:86:25 + 38: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:84:31 + 39: IsNonZeroDestIsSmall { + dest: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.rst", ty: SyncReset }, + }, + 40: IsNonZeroDestIsSmall { + dest: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + 41: AndSmall { + dest: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 42: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:64:1 + 43: Const { + dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + value: 0x0, + }, + 44: CastToUInt { + dest: StatePartIndex(63), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 1, + }, + // at: ready_valid.rs:166:5 + 45: BranchIfZero { + target: 48, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 46: BranchIfNonZero { + target: 48, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:171:13 + 47: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<1> }, + src: StatePartIndex(63), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:166:5 + 48: BranchIfNonZero { + target: 50, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:182:13 + 49: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<1> }, + src: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:91:19 + 50: CastBigToArrayIndex { + dest: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<0> }, + }, + 51: IsNonZeroDestIsSmall { + dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + }, + 52: AndSmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 53: CastBigToArrayIndex { + dest: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<0> }, + }, + 54: IsNonZeroDestIsSmall { + dest: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + }, + 55: BranchIfSmallZero { + target: 58, + value: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 56: MemoryReadUInt { + dest: StatePartIndex(14), // (0x1f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 1>, + // data: [ + // // len = 0x1 + // [0x0]: 0x1f, + // ], + // }) (), + addr: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + stride: 8, + start: 0, + width: 8, + }, + 57: Branch { + target: 59, + }, + 58: Const { + dest: StatePartIndex(14), // (0x1f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:64:1 + 59: Copy { + dest: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 60: Copy { + dest: StatePartIndex(47), // (0x1f) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(14), // (0x1f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + }, + 61: Shl { + dest: StatePartIndex(49), // (0x3e) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(47), // (0x1f) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 1, + }, + 62: Or { + dest: StatePartIndex(50), // (0x3f) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(49), // (0x3e) SlotDebugData { name: "", ty: UInt<9> }, + }, + 63: CastToUInt { + dest: StatePartIndex(51), // (0x3f) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(50), // (0x3f) SlotDebugData { name: "", ty: UInt<9> }, + dest_width: 9, + }, + 64: Copy { + dest: StatePartIndex(52), // (0x3f) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(51), // (0x3f) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: ready_valid.rs:130:5 + 65: BranchIfZero { + target: 67, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:131:9 + 66: Copy { + dest: StatePartIndex(6), // (0x3f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(52), // (0x3f) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:130:5 + 67: BranchIfNonZero { + target: 69, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:134:13 + 68: Copy { + dest: StatePartIndex(6), // (0x3f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(2), // (0x3f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:91:19 + 69: IsNonZeroDestIsSmall { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + }, + 70: AndSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 71: Copy { + dest: StatePartIndex(8), // (0x3f) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(6), // (0x3f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 72: SliceInt { + dest: StatePartIndex(9), // (0x1f) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(8), // (0x3f) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:79:32 + 73: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(6), // (0x3f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 74: BranchIfSmallNeImmediate { + target: 76, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 75: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 76: BranchIfSmallNeImmediate { + target: 78, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 77: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:101:5 + 78: Copy { + dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + src: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:156:5 + 79: BranchIfZero { + target: 84, + value: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:158:9 + 80: BranchIfZero { + target: 82, + value: StatePartIndex(58), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:159:13 + 81: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:158:9 + 82: BranchIfNonZero { + target: 84, + value: StatePartIndex(58), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:161:13 + 83: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(60), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:64:1 + 84: Copy { + dest: StatePartIndex(4), // (0x3f) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(2), // (0x3f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 85: SliceInt { + dest: StatePartIndex(5), // (0x1f) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(4), // (0x3f) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:77:32 + 86: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2), // (0x3f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 87: BranchIfSmallNeImmediate { + target: 89, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 88: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 89: BranchIfSmallNeImmediate { + target: 91, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 90: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + }, + // at: ready_valid.rs:98:5 + 91: Copy { + dest: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + src: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:116:5 + 92: Copy { + dest: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 93: IsNonZeroDestIsSmall { + dest: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 94: CmpNe { + dest: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + rhs: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:141:5 + 95: BranchIfZero { + target: 97, + value: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:142:9 + 96: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:146:5 + 97: BranchIfZero { + target: 102, + value: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:148:9 + 98: BranchIfZero { + target: 100, + value: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:149:13 + 99: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:148:9 + 100: BranchIfNonZero { + target: 102, + value: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:151:13 + 101: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:118:30 + 102: BranchIfSmallNeImmediate { + target: 104, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + 103: Copy { + dest: StatePartIndex(42), // (0x1f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(5), // (0x1f) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:118:5 + 104: Copy { + dest: StatePartIndex(18), // (0x1f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + src: StatePartIndex(42), // (0x1f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + }, + // at: ready_valid.rs:84:31 + 105: BranchIfSmallZero { + target: 110, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 106: BranchIfSmallNonZero { + target: 109, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 107: Copy { + dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + src: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<0> }, + }, + 108: Branch { + target: 110, + }, + 109: Copy { + dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:86:25 + 110: BranchIfSmallZero { + target: 115, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 111: BranchIfSmallNonZero { + target: 114, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 112: Copy { + dest: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + src: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<0> }, + }, + 113: Branch { + target: 115, + }, + 114: Copy { + dest: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:88:26 + 115: BranchIfSmallZero { + target: 120, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 116: BranchIfSmallNonZero { + target: 119, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 117: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + }, + 118: Branch { + target: 120, + }, + 119: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 120: BranchIfSmallZero { + target: 121, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 121: BranchIfSmallZero { + target: 129, + value: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 122: CopySmall { + dest: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + }, + 123: CopySmall { + dest: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 124: Copy { + dest: StatePartIndex(20), // (0x1f) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(18), // (0x1f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + }, + 125: Copy { + dest: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + }, + 126: BranchIfSmallZero { + target: 129, + value: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 127: BranchIfZero { + target: 129, + value: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 128: MemoryWriteUInt { + value: StatePartIndex(20), // (0x1f) SlotDebugData { name: "", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 1>, + // data: [ + // // len = 0x1 + // [0x0]: 0x1f, + // ], + // }) (), + addr: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + stride: 8, + start: 0, + width: 8, + }, + 129: XorSmallImmediate { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 130: XorSmallImmediate { + dest: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:84:31 + 131: XorSmallImmediate { + dest: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:64:1 + 132: Return, + ], + .. + }, + pc: 132, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array, 1>, + data: [ + // len = 0x1 + [0x0]: 0x1f, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 1, + 1, + 1, + 0, + 0, + 1, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 63, + 0, + 63, + 31, + 63, + 0, + 63, + 31, + 1, + 0, + 1, + 0, + 31, + 0, + 0, + 0, + 31, + 1, + 31, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 1, + 1, + 1, + 31, + 0, + 0, + 1, + 1, + 31, + 1, + 62, + 63, + 63, + 63, + 0, + 0, + 1, + 1, + 0, + 1, + 1, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.clk, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.rst, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.ready, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.ready, + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "queue", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "inp", + child: TraceBundle { + name: "inp", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(2), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(3), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(4), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceBundle { + name: "out", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(5), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(6), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(7), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + TraceModuleIO { + name: "count", + child: TraceUInt { + location: TraceScalarId(8), + name: "count", + ty: UInt<1>, + flow: Sink, + }, + ty: UInt<1>, + flow: Sink, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 1, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<0>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + #[hdl(flip)] /* offset = 2 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + #[hdl(flip)] /* offset = 2 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<0>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + /* offset = 2 */ + data: UInt<8>, + /* offset = 10 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + /* offset = 2 */ + data: UInt<8>, + /* offset = 10 */ + mask: Bool, + }, + }, + ], + array_type: Array, 1>, + }, + TraceReg { + name: "inp_index_reg", + child: TraceUInt { + location: TraceScalarId(18), + name: "inp_index_reg", + ty: UInt<0>, + flow: Duplex, + }, + ty: UInt<0>, + }, + TraceReg { + name: "out_index_reg", + child: TraceUInt { + location: TraceScalarId(19), + name: "out_index_reg", + ty: UInt<0>, + flow: Duplex, + }, + ty: UInt<0>, + }, + TraceReg { + name: "maybe_full_reg", + child: TraceBool { + location: TraceScalarId(20), + name: "maybe_full_reg", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "inp_firing", + child: TraceBool { + location: TraceScalarId(21), + name: "inp_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(22), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "out_firing", + child: TraceBool { + location: TraceScalarId(23), + name: "out_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(24), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "indexes_equal", + child: TraceBool { + location: TraceScalarId(25), + name: "indexes_equal", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "empty", + child: TraceBool { + location: TraceScalarId(26), + name: "empty", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "full", + child: TraceBool { + location: TraceScalarId(27), + name: "full", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "unwrap_or_else_out", + child: TraceUInt { + location: TraceScalarId(28), + name: "unwrap_or_else_out", + ty: UInt<8>, + flow: Duplex, + }, + ty: UInt<8>, + }, + TraceWire { + name: "count_lower", + child: TraceUInt { + location: TraceScalarId(29), + name: "count_lower", + ty: UInt<0>, + flow: Duplex, + }, + ty: UInt<0>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSyncReset { + index: StatePartIndex(1), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<8>, + }, + state: 0x1f, + last_state: 0x1f, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigBool { + index: StatePartIndex(3), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(5), + kind: EnumDiscriminant { + index: StatePartIndex(1), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(9), + ty: UInt<8>, + }, + state: 0x1f, + last_state: 0x1f, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigBool { + index: StatePartIndex(7), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigUInt { + index: StatePartIndex(10), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigUInt { + index: StatePartIndex(11), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigBool { + index: StatePartIndex(12), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigClock { + index: StatePartIndex(13), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(12), + kind: BigUInt { + index: StatePartIndex(14), + ty: UInt<8>, + }, + state: 0x1f, + last_state: 0x1f, + }, + SimTrace { + id: TraceScalarId(13), + kind: BigUInt { + index: StatePartIndex(15), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigBool { + index: StatePartIndex(16), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(15), + kind: BigClock { + index: StatePartIndex(17), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(16), + kind: BigUInt { + index: StatePartIndex(18), + ty: UInt<8>, + }, + state: 0x1f, + last_state: 0x1f, + }, + SimTrace { + id: TraceScalarId(17), + kind: BigBool { + index: StatePartIndex(19), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigUInt { + index: StatePartIndex(22), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigUInt { + index: StatePartIndex(25), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(20), + kind: BigBool { + index: StatePartIndex(27), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(21), + kind: BigBool { + index: StatePartIndex(30), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(22), + kind: BigBool { + index: StatePartIndex(31), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(23), + kind: BigBool { + index: StatePartIndex(32), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(24), + kind: BigBool { + index: StatePartIndex(33), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(25), + kind: BigBool { + index: StatePartIndex(34), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(26), + kind: BigBool { + index: StatePartIndex(36), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(27), + kind: BigBool { + index: StatePartIndex(39), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(28), + kind: BigUInt { + index: StatePartIndex(42), + ty: UInt<8>, + }, + state: 0x1f, + last_state: 0x1f, + }, + SimTrace { + id: TraceScalarId(29), + kind: BigUInt { + index: StatePartIndex(64), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 1, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<0>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + #[hdl(flip)] /* offset = 2 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + #[hdl(flip)] /* offset = 2 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<0>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + /* offset = 2 */ + data: UInt<8>, + /* offset = 10 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + /* offset = 2 */ + data: UInt<8>, + /* offset = 10 */ + mask: Bool, + }, + }, + ], + array_type: Array, 1>, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [ + StatePartIndex(3), + StatePartIndex(8), + StatePartIndex(15), + ], + event_queue: EventQueue(EventQueueData { + instant: 100 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_1_false_true.vcd b/crates/fayalite/tests/sim/expected/queue_1_false_true.vcd new file mode 100644 index 0000000..cc36d02 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/queue_1_false_true.vcd @@ -0,0 +1,1836 @@ +$timescale 1 ps $end +$scope module queue $end +$scope struct cd $end +$var wire 1 11z(a clk $end +$var wire 1 q1t|f rst $end +$upscope $end +$scope struct inp $end +$scope struct data $end +$var string 1 j|a-9 \$tag $end +$var wire 8 pjN&T HdlSome $end +$upscope $end +$var wire 1 *x8M* ready $end +$upscope $end +$scope struct out $end +$scope struct data $end +$var string 1 'Aa8} \$tag $end +$var wire 8 1b%.O HdlSome $end +$upscope $end +$var wire 1 vZD*c ready $end +$upscope $end +$var wire 1 rf7Xh count $end +$scope struct mem $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 8 (.Juw mem $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var string 0 K]Dkr addr $end +$var wire 1 P|=HX en $end +$var wire 1 z+ft% clk $end +$var wire 8 m+9ec data $end +$upscope $end +$scope struct w1 $end +$var string 0 8Oa@o addr $end +$var wire 1 VaM[2 en $end +$var wire 1 aH[{] clk $end +$var wire 8 8|1uZ data $end +$var wire 1 DYq.y mask $end +$upscope $end +$upscope $end +$var string 0 Xk?#v inp_index_reg $end +$var string 0 p19yW out_index_reg $end +$var reg 1 kEQiI maybe_full_reg $end +$var wire 1 *gdL1 inp_firing $end +$var wire 1 ;HWUJ firing $end +$var wire 1 Ph#@^ out_firing $end +$var wire 1 ;HWUJ" firing_2 $end +$var wire 1 i[~ { + len: 18, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 70, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::indexes_equal", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::empty", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::full", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count_lower", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 1, + debug_data: [ + (), + ], + layout_data: [ + MemoryData { + array_type: Array, 1>, + data: [ + // len = 0x1 + [0x0]: 0x00, + ], + }, + ], + .. + }, + }, + insns: [ + // at: ready_valid.rs:64:1 + 0: SubU { + dest: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + dest_width: 1, + }, + 1: CastToUInt { + dest: StatePartIndex(68), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 0, + }, + // at: ready_valid.rs:178:13 + 2: Copy { + dest: StatePartIndex(66), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<0> }, + src: StatePartIndex(68), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:64:1 + 3: CastToUInt { + dest: StatePartIndex(69), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(66), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<0> }, + dest_width: 1, + }, + 4: Const { + dest: StatePartIndex(63), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x1, + }, + 5: CastToUInt { + dest: StatePartIndex(64), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(63), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + dest_width: 1, + }, + 6: Const { + dest: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x0, + }, + 7: CmpEq { + dest: StatePartIndex(57), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + }, + 8: CmpEq { + dest: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + }, + 9: Const { + dest: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + value: 0x0, + }, + 10: Copy { + dest: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + }, + 11: Const { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 12: Add { + dest: StatePartIndex(58), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 13: CastToUInt { + dest: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(58), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 0, + }, + 14: Add { + dest: StatePartIndex(61), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 15: CastToUInt { + dest: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(61), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 0, + }, + 16: Const { + dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:118:30 + 17: Copy { + dest: StatePartIndex(42), // (0x1f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:117:5 + 18: Copy { + dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:115:5 + 19: Copy { + dest: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<0> }, + src: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:114:5 + 20: Copy { + dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:64:1 + 21: Const { + dest: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + value: 0x1, + }, + // at: ready_valid.rs:113:5 + 22: Copy { + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:119:5 + 23: Copy { + dest: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:112:5 + 24: Copy { + dest: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<0> }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:64:1 + 25: NotU { + dest: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + width: 1, + }, + 26: CmpEq { + dest: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:104:5 + 27: Copy { + dest: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + src: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 28: And { + dest: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:107:5 + 29: Copy { + dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + src: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 30: NotU { + dest: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + width: 1, + }, + 31: And { + dest: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:110:5 + 32: Copy { + dest: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + src: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 33: NotU { + dest: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + width: 1, + }, + // at: ready_valid.rs:121:5 + 34: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:124:9 + 35: BranchIfZero { + target: 37, + value: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:125:13 + 36: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:166:5 + 37: BranchIfZero { + target: 40, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 38: BranchIfZero { + target: 40, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:169:13 + 39: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<1> }, + src: StatePartIndex(64), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:88:26 + 40: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 41: Const { + dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, + }, + // at: ready_valid.rs:86:25 + 42: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:84:31 + 43: IsNonZeroDestIsSmall { + dest: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.rst", ty: SyncReset }, + }, + 44: IsNonZeroDestIsSmall { + dest: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + 45: AndSmall { + dest: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 46: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:64:1 + 47: Const { + dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + value: 0x0, + }, + 48: CastToUInt { + dest: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 1, + }, + // at: ready_valid.rs:166:5 + 49: BranchIfZero { + target: 52, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 50: BranchIfNonZero { + target: 52, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:171:13 + 51: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<1> }, + src: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:166:5 + 52: BranchIfNonZero { + target: 54, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:182:13 + 53: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<1> }, + src: StatePartIndex(69), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:91:19 + 54: CastBigToArrayIndex { + dest: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<0> }, + }, + 55: IsNonZeroDestIsSmall { + dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + }, + 56: AndSmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 57: CastBigToArrayIndex { + dest: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<0> }, + }, + 58: IsNonZeroDestIsSmall { + dest: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + }, + 59: BranchIfSmallZero { + target: 62, + value: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 60: MemoryReadUInt { + dest: StatePartIndex(14), // (0x1f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 1>, + // data: [ + // // len = 0x1 + // [0x0]: 0x1f, + // ], + // }) (), + addr: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + stride: 8, + start: 0, + width: 8, + }, + 61: Branch { + target: 63, + }, + 62: Const { + dest: StatePartIndex(14), // (0x1f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:64:1 + 63: Copy { + dest: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 64: Copy { + dest: StatePartIndex(47), // (0x1f) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(14), // (0x1f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + }, + 65: Shl { + dest: StatePartIndex(49), // (0x3e) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(47), // (0x1f) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 1, + }, + 66: Or { + dest: StatePartIndex(50), // (0x3f) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(49), // (0x3e) SlotDebugData { name: "", ty: UInt<9> }, + }, + 67: CastToUInt { + dest: StatePartIndex(51), // (0x3f) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(50), // (0x3f) SlotDebugData { name: "", ty: UInt<9> }, + dest_width: 9, + }, + 68: Copy { + dest: StatePartIndex(52), // (0x3f) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(51), // (0x3f) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: ready_valid.rs:130:5 + 69: BranchIfZero { + target: 71, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:131:9 + 70: Copy { + dest: StatePartIndex(6), // (0x3f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(52), // (0x3f) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:130:5 + 71: BranchIfNonZero { + target: 73, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:136:13 + 72: Copy { + dest: StatePartIndex(6), // (0x3f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:91:19 + 73: IsNonZeroDestIsSmall { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + }, + 74: AndSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 75: Copy { + dest: StatePartIndex(8), // (0x3f) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(6), // (0x3f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 76: SliceInt { + dest: StatePartIndex(9), // (0x1f) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(8), // (0x3f) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:79:32 + 77: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(6), // (0x3f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 78: BranchIfSmallNeImmediate { + target: 80, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 79: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 80: BranchIfSmallNeImmediate { + target: 82, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 81: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:101:5 + 82: Copy { + dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + src: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:156:5 + 83: BranchIfZero { + target: 88, + value: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:158:9 + 84: BranchIfZero { + target: 86, + value: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:159:13 + 85: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:158:9 + 86: BranchIfNonZero { + target: 88, + value: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:161:13 + 87: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:64:1 + 88: Copy { + dest: StatePartIndex(4), // (0x3f) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(2), // (0x3f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 89: SliceInt { + dest: StatePartIndex(5), // (0x1f) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(4), // (0x3f) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:77:32 + 90: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2), // (0x3f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 91: BranchIfSmallNeImmediate { + target: 93, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 92: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 93: BranchIfSmallNeImmediate { + target: 95, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 94: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + }, + // at: ready_valid.rs:98:5 + 95: Copy { + dest: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + src: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:116:5 + 96: Copy { + dest: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 97: IsNonZeroDestIsSmall { + dest: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 98: CmpNe { + dest: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + rhs: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:141:5 + 99: BranchIfZero { + target: 101, + value: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:142:9 + 100: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:146:5 + 101: BranchIfZero { + target: 106, + value: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:148:9 + 102: BranchIfZero { + target: 104, + value: StatePartIndex(57), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:149:13 + 103: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:148:9 + 104: BranchIfNonZero { + target: 106, + value: StatePartIndex(57), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:151:13 + 105: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:118:30 + 106: BranchIfSmallNeImmediate { + target: 108, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + 107: Copy { + dest: StatePartIndex(42), // (0x1f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(5), // (0x1f) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:118:5 + 108: Copy { + dest: StatePartIndex(18), // (0x1f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + src: StatePartIndex(42), // (0x1f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + }, + // at: ready_valid.rs:84:31 + 109: BranchIfSmallZero { + target: 114, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 110: BranchIfSmallNonZero { + target: 113, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 111: Copy { + dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + src: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<0> }, + }, + 112: Branch { + target: 114, + }, + 113: Copy { + dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:86:25 + 114: BranchIfSmallZero { + target: 119, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 115: BranchIfSmallNonZero { + target: 118, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 116: Copy { + dest: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + src: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<0> }, + }, + 117: Branch { + target: 119, + }, + 118: Copy { + dest: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:88:26 + 119: BranchIfSmallZero { + target: 124, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 120: BranchIfSmallNonZero { + target: 123, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 121: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + }, + 122: Branch { + target: 124, + }, + 123: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 124: BranchIfSmallZero { + target: 125, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 125: BranchIfSmallZero { + target: 133, + value: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 126: CopySmall { + dest: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + }, + 127: CopySmall { + dest: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 128: Copy { + dest: StatePartIndex(20), // (0x1f) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(18), // (0x1f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + }, + 129: Copy { + dest: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + }, + 130: BranchIfSmallZero { + target: 133, + value: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 131: BranchIfZero { + target: 133, + value: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 132: MemoryWriteUInt { + value: StatePartIndex(20), // (0x1f) SlotDebugData { name: "", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 1>, + // data: [ + // // len = 0x1 + // [0x0]: 0x1f, + // ], + // }) (), + addr: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + stride: 8, + start: 0, + width: 8, + }, + 133: XorSmallImmediate { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 134: XorSmallImmediate { + dest: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:84:31 + 135: XorSmallImmediate { + dest: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:64:1 + 136: Return, + ], + .. + }, + pc: 136, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array, 1>, + data: [ + // len = 0x1 + [0x0]: 0x1f, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 1, + 1, + 1, + 0, + 0, + 1, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 63, + 0, + 63, + 31, + 63, + 0, + 63, + 31, + 1, + 0, + 1, + 0, + 31, + 0, + 0, + 0, + 31, + 1, + 31, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 1, + 1, + 1, + 31, + 0, + 0, + 1, + 1, + 31, + 1, + 62, + 63, + 63, + 63, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 1, + 1, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.clk, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.rst, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.ready, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.ready, + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "queue", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "inp", + child: TraceBundle { + name: "inp", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(2), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(3), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(4), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceBundle { + name: "out", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(5), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(6), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(7), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + TraceModuleIO { + name: "count", + child: TraceUInt { + location: TraceScalarId(8), + name: "count", + ty: UInt<1>, + flow: Sink, + }, + ty: UInt<1>, + flow: Sink, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 1, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<0>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + #[hdl(flip)] /* offset = 2 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + #[hdl(flip)] /* offset = 2 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<0>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + /* offset = 2 */ + data: UInt<8>, + /* offset = 10 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + /* offset = 2 */ + data: UInt<8>, + /* offset = 10 */ + mask: Bool, + }, + }, + ], + array_type: Array, 1>, + }, + TraceReg { + name: "inp_index_reg", + child: TraceUInt { + location: TraceScalarId(18), + name: "inp_index_reg", + ty: UInt<0>, + flow: Duplex, + }, + ty: UInt<0>, + }, + TraceReg { + name: "out_index_reg", + child: TraceUInt { + location: TraceScalarId(19), + name: "out_index_reg", + ty: UInt<0>, + flow: Duplex, + }, + ty: UInt<0>, + }, + TraceReg { + name: "maybe_full_reg", + child: TraceBool { + location: TraceScalarId(20), + name: "maybe_full_reg", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "inp_firing", + child: TraceBool { + location: TraceScalarId(21), + name: "inp_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(22), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "out_firing", + child: TraceBool { + location: TraceScalarId(23), + name: "out_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(24), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "indexes_equal", + child: TraceBool { + location: TraceScalarId(25), + name: "indexes_equal", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "empty", + child: TraceBool { + location: TraceScalarId(26), + name: "empty", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "full", + child: TraceBool { + location: TraceScalarId(27), + name: "full", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "unwrap_or_else_out", + child: TraceUInt { + location: TraceScalarId(28), + name: "unwrap_or_else_out", + ty: UInt<8>, + flow: Duplex, + }, + ty: UInt<8>, + }, + TraceWire { + name: "count_lower", + child: TraceUInt { + location: TraceScalarId(29), + name: "count_lower", + ty: UInt<0>, + flow: Duplex, + }, + ty: UInt<0>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSyncReset { + index: StatePartIndex(1), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<8>, + }, + state: 0x1f, + last_state: 0x1f, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigBool { + index: StatePartIndex(3), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(5), + kind: EnumDiscriminant { + index: StatePartIndex(1), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(9), + ty: UInt<8>, + }, + state: 0x1f, + last_state: 0x1f, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigBool { + index: StatePartIndex(7), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigUInt { + index: StatePartIndex(10), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigUInt { + index: StatePartIndex(11), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigBool { + index: StatePartIndex(12), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigClock { + index: StatePartIndex(13), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(12), + kind: BigUInt { + index: StatePartIndex(14), + ty: UInt<8>, + }, + state: 0x1f, + last_state: 0x1f, + }, + SimTrace { + id: TraceScalarId(13), + kind: BigUInt { + index: StatePartIndex(15), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigBool { + index: StatePartIndex(16), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(15), + kind: BigClock { + index: StatePartIndex(17), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(16), + kind: BigUInt { + index: StatePartIndex(18), + ty: UInt<8>, + }, + state: 0x1f, + last_state: 0x1f, + }, + SimTrace { + id: TraceScalarId(17), + kind: BigBool { + index: StatePartIndex(19), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigUInt { + index: StatePartIndex(22), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigUInt { + index: StatePartIndex(25), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(20), + kind: BigBool { + index: StatePartIndex(27), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(21), + kind: BigBool { + index: StatePartIndex(30), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(22), + kind: BigBool { + index: StatePartIndex(31), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(23), + kind: BigBool { + index: StatePartIndex(32), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(24), + kind: BigBool { + index: StatePartIndex(33), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(25), + kind: BigBool { + index: StatePartIndex(34), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(26), + kind: BigBool { + index: StatePartIndex(36), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(27), + kind: BigBool { + index: StatePartIndex(39), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(28), + kind: BigUInt { + index: StatePartIndex(42), + ty: UInt<8>, + }, + state: 0x1f, + last_state: 0x1f, + }, + SimTrace { + id: TraceScalarId(29), + kind: BigUInt { + index: StatePartIndex(66), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 1, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<0>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + #[hdl(flip)] /* offset = 2 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + #[hdl(flip)] /* offset = 2 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<0>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + /* offset = 2 */ + data: UInt<8>, + /* offset = 10 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + /* offset = 2 */ + data: UInt<8>, + /* offset = 10 */ + mask: Bool, + }, + }, + ], + array_type: Array, 1>, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [ + StatePartIndex(3), + StatePartIndex(8), + StatePartIndex(15), + ], + event_queue: EventQueue(EventQueueData { + instant: 100 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_1_true_false.vcd b/crates/fayalite/tests/sim/expected/queue_1_true_false.vcd new file mode 100644 index 0000000..0ddf51e --- /dev/null +++ b/crates/fayalite/tests/sim/expected/queue_1_true_false.vcd @@ -0,0 +1,1821 @@ +$timescale 1 ps $end +$scope module queue $end +$scope struct cd $end +$var wire 1 11z(a clk $end +$var wire 1 q1t|f rst $end +$upscope $end +$scope struct inp $end +$scope struct data $end +$var string 1 j|a-9 \$tag $end +$var wire 8 pjN&T HdlSome $end +$upscope $end +$var wire 1 *x8M* ready $end +$upscope $end +$scope struct out $end +$scope struct data $end +$var string 1 'Aa8} \$tag $end +$var wire 8 1b%.O HdlSome $end +$upscope $end +$var wire 1 vZD*c ready $end +$upscope $end +$var wire 1 rf7Xh count $end +$scope struct mem $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 8 (.Juw mem $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var string 0 K]Dkr addr $end +$var wire 1 P|=HX en $end +$var wire 1 z+ft% clk $end +$var wire 8 m+9ec data $end +$upscope $end +$scope struct w1 $end +$var string 0 8Oa@o addr $end +$var wire 1 VaM[2 en $end +$var wire 1 aH[{] clk $end +$var wire 8 8|1uZ data $end +$var wire 1 DYq.y mask $end +$upscope $end +$upscope $end +$var string 0 Xk?#v inp_index_reg $end +$var string 0 p19yW out_index_reg $end +$var reg 1 kEQiI maybe_full_reg $end +$var wire 1 *gdL1 inp_firing $end +$var wire 1 ;HWUJ firing $end +$var wire 1 Ph#@^ out_firing $end +$var wire 1 ;HWUJ" firing_2 $end +$var wire 1 i[~ { + len: 18, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 68, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::indexes_equal", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::empty", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::full", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count_lower", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 1, + debug_data: [ + (), + ], + layout_data: [ + MemoryData { + array_type: Array, 1>, + data: [ + // len = 0x1 + [0x0]: 0x00, + ], + }, + ], + .. + }, + }, + insns: [ + // at: ready_valid.rs:64:1 + 0: SubU { + dest: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + dest_width: 1, + }, + 1: CastToUInt { + dest: StatePartIndex(66), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 0, + }, + // at: ready_valid.rs:178:13 + 2: Copy { + dest: StatePartIndex(64), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<0> }, + src: StatePartIndex(66), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:64:1 + 3: CastToUInt { + dest: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(64), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<0> }, + dest_width: 1, + }, + 4: Const { + dest: StatePartIndex(61), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x1, + }, + 5: CastToUInt { + dest: StatePartIndex(62), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(61), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + dest_width: 1, + }, + 6: Const { + dest: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x0, + }, + 7: CmpEq { + dest: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + }, + 8: CmpEq { + dest: StatePartIndex(58), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + }, + 9: Const { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 10: Add { + dest: StatePartIndex(56), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 11: CastToUInt { + dest: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(56), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 0, + }, + 12: Add { + dest: StatePartIndex(59), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 13: CastToUInt { + dest: StatePartIndex(60), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(59), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 0, + }, + 14: Const { + dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:118:30 + 15: Copy { + dest: StatePartIndex(42), // (0x23) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:117:5 + 16: Copy { + dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:115:5 + 17: Copy { + dest: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<0> }, + src: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:114:5 + 18: Copy { + dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:64:1 + 19: Const { + dest: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + value: 0x1, + }, + // at: ready_valid.rs:113:5 + 20: Copy { + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:119:5 + 21: Copy { + dest: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:112:5 + 22: Copy { + dest: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<0> }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:64:1 + 23: NotU { + dest: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + width: 1, + }, + 24: CmpEq { + dest: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:104:5 + 25: Copy { + dest: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + src: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 26: And { + dest: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:107:5 + 27: Copy { + dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + src: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 28: NotU { + dest: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + width: 1, + }, + 29: And { + dest: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:110:5 + 30: Copy { + dest: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + src: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 31: NotU { + dest: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + width: 1, + }, + // at: ready_valid.rs:121:5 + 32: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:124:9 + 33: BranchIfZero { + target: 35, + value: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:125:13 + 34: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:166:5 + 35: BranchIfZero { + target: 38, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 36: BranchIfZero { + target: 38, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:169:13 + 37: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<1> }, + src: StatePartIndex(62), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:88:26 + 38: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 39: Const { + dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, + }, + // at: ready_valid.rs:86:25 + 40: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:84:31 + 41: IsNonZeroDestIsSmall { + dest: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.rst", ty: SyncReset }, + }, + 42: IsNonZeroDestIsSmall { + dest: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + 43: AndSmall { + dest: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 44: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:64:1 + 45: Const { + dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + value: 0x0, + }, + 46: CastToUInt { + dest: StatePartIndex(63), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 1, + }, + // at: ready_valid.rs:166:5 + 47: BranchIfZero { + target: 50, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 48: BranchIfNonZero { + target: 50, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:171:13 + 49: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<1> }, + src: StatePartIndex(63), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:166:5 + 50: BranchIfNonZero { + target: 52, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:182:13 + 51: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<1> }, + src: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:91:19 + 52: CastBigToArrayIndex { + dest: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<0> }, + }, + 53: IsNonZeroDestIsSmall { + dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + }, + 54: AndSmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 55: CastBigToArrayIndex { + dest: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<0> }, + }, + 56: IsNonZeroDestIsSmall { + dest: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + }, + 57: BranchIfSmallZero { + target: 60, + value: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 58: MemoryReadUInt { + dest: StatePartIndex(14), // (0x23) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 1>, + // data: [ + // // len = 0x1 + // [0x0]: 0x23, + // ], + // }) (), + addr: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + stride: 8, + start: 0, + width: 8, + }, + 59: Branch { + target: 61, + }, + 60: Const { + dest: StatePartIndex(14), // (0x23) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:64:1 + 61: Copy { + dest: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 62: Copy { + dest: StatePartIndex(47), // (0x23) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(14), // (0x23) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + }, + 63: Shl { + dest: StatePartIndex(49), // (0x46) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(47), // (0x23) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 1, + }, + 64: Or { + dest: StatePartIndex(50), // (0x47) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(49), // (0x46) SlotDebugData { name: "", ty: UInt<9> }, + }, + 65: CastToUInt { + dest: StatePartIndex(51), // (0x47) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(50), // (0x47) SlotDebugData { name: "", ty: UInt<9> }, + dest_width: 9, + }, + 66: Copy { + dest: StatePartIndex(52), // (0x47) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(51), // (0x47) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: ready_valid.rs:130:5 + 67: BranchIfZero { + target: 69, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:131:9 + 68: Copy { + dest: StatePartIndex(6), // (0x47) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(52), // (0x47) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:130:5 + 69: BranchIfNonZero { + target: 71, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:134:13 + 70: Copy { + dest: StatePartIndex(6), // (0x47) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(2), // (0x47) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:91:19 + 71: IsNonZeroDestIsSmall { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + }, + 72: AndSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 73: Copy { + dest: StatePartIndex(8), // (0x47) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(6), // (0x47) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 74: SliceInt { + dest: StatePartIndex(9), // (0x23) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(8), // (0x47) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:79:32 + 75: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(6), // (0x47) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 76: BranchIfSmallNeImmediate { + target: 78, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 77: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 78: BranchIfSmallNeImmediate { + target: 80, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 79: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:101:5 + 80: Copy { + dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + src: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:156:5 + 81: BranchIfZero { + target: 86, + value: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:158:9 + 82: BranchIfZero { + target: 84, + value: StatePartIndex(58), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:159:13 + 83: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:158:9 + 84: BranchIfNonZero { + target: 86, + value: StatePartIndex(58), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:161:13 + 85: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(60), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:64:1 + 86: Copy { + dest: StatePartIndex(4), // (0x47) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(2), // (0x47) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 87: SliceInt { + dest: StatePartIndex(5), // (0x23) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(4), // (0x47) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:77:32 + 88: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2), // (0x47) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 89: BranchIfSmallNeImmediate { + target: 91, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 90: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 91: BranchIfSmallNeImmediate { + target: 93, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 92: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + }, + // at: ready_valid.rs:98:5 + 93: Copy { + dest: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + src: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:116:5 + 94: Copy { + dest: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 95: IsNonZeroDestIsSmall { + dest: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 96: CmpNe { + dest: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + rhs: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:141:5 + 97: BranchIfZero { + target: 99, + value: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:142:9 + 98: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:146:5 + 99: BranchIfZero { + target: 104, + value: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:148:9 + 100: BranchIfZero { + target: 102, + value: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:149:13 + 101: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:148:9 + 102: BranchIfNonZero { + target: 104, + value: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:151:13 + 103: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:118:30 + 104: BranchIfSmallNeImmediate { + target: 106, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + 105: Copy { + dest: StatePartIndex(42), // (0x23) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(5), // (0x23) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:118:5 + 106: Copy { + dest: StatePartIndex(18), // (0x23) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + src: StatePartIndex(42), // (0x23) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + }, + // at: ready_valid.rs:84:31 + 107: BranchIfSmallZero { + target: 112, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 108: BranchIfSmallNonZero { + target: 111, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 109: Copy { + dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + src: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<0> }, + }, + 110: Branch { + target: 112, + }, + 111: Copy { + dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:86:25 + 112: BranchIfSmallZero { + target: 117, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 113: BranchIfSmallNonZero { + target: 116, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 114: Copy { + dest: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + src: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<0> }, + }, + 115: Branch { + target: 117, + }, + 116: Copy { + dest: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:88:26 + 117: BranchIfSmallZero { + target: 122, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 118: BranchIfSmallNonZero { + target: 121, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 119: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + }, + 120: Branch { + target: 122, + }, + 121: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 122: BranchIfSmallZero { + target: 123, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 123: BranchIfSmallZero { + target: 131, + value: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 124: CopySmall { + dest: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + }, + 125: CopySmall { + dest: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 126: Copy { + dest: StatePartIndex(20), // (0x23) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(18), // (0x23) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + }, + 127: Copy { + dest: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + }, + 128: BranchIfSmallZero { + target: 131, + value: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 129: BranchIfZero { + target: 131, + value: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 130: MemoryWriteUInt { + value: StatePartIndex(20), // (0x23) SlotDebugData { name: "", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 1>, + // data: [ + // // len = 0x1 + // [0x0]: 0x23, + // ], + // }) (), + addr: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + stride: 8, + start: 0, + width: 8, + }, + 131: XorSmallImmediate { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 132: XorSmallImmediate { + dest: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:84:31 + 133: XorSmallImmediate { + dest: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:64:1 + 134: Return, + ], + .. + }, + pc: 134, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array, 1>, + data: [ + // len = 0x1 + [0x0]: 0x23, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 1, + 1, + 1, + 0, + 0, + 1, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 71, + 0, + 71, + 35, + 71, + 0, + 71, + 35, + 1, + 0, + 1, + 0, + 35, + 0, + 0, + 0, + 35, + 1, + 35, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 1, + 1, + 1, + 35, + 0, + 0, + 1, + 1, + 35, + 1, + 70, + 71, + 71, + 71, + 0, + 0, + 1, + 1, + 0, + 1, + 1, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.clk, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.rst, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.ready, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.ready, + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "queue", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "inp", + child: TraceBundle { + name: "inp", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(2), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(3), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(4), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceBundle { + name: "out", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(5), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(6), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(7), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + TraceModuleIO { + name: "count", + child: TraceUInt { + location: TraceScalarId(8), + name: "count", + ty: UInt<1>, + flow: Sink, + }, + ty: UInt<1>, + flow: Sink, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 1, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<0>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + #[hdl(flip)] /* offset = 2 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + #[hdl(flip)] /* offset = 2 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<0>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + /* offset = 2 */ + data: UInt<8>, + /* offset = 10 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + /* offset = 2 */ + data: UInt<8>, + /* offset = 10 */ + mask: Bool, + }, + }, + ], + array_type: Array, 1>, + }, + TraceReg { + name: "inp_index_reg", + child: TraceUInt { + location: TraceScalarId(18), + name: "inp_index_reg", + ty: UInt<0>, + flow: Duplex, + }, + ty: UInt<0>, + }, + TraceReg { + name: "out_index_reg", + child: TraceUInt { + location: TraceScalarId(19), + name: "out_index_reg", + ty: UInt<0>, + flow: Duplex, + }, + ty: UInt<0>, + }, + TraceReg { + name: "maybe_full_reg", + child: TraceBool { + location: TraceScalarId(20), + name: "maybe_full_reg", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "inp_firing", + child: TraceBool { + location: TraceScalarId(21), + name: "inp_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(22), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "out_firing", + child: TraceBool { + location: TraceScalarId(23), + name: "out_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(24), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "indexes_equal", + child: TraceBool { + location: TraceScalarId(25), + name: "indexes_equal", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "empty", + child: TraceBool { + location: TraceScalarId(26), + name: "empty", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "full", + child: TraceBool { + location: TraceScalarId(27), + name: "full", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "unwrap_or_else_out", + child: TraceUInt { + location: TraceScalarId(28), + name: "unwrap_or_else_out", + ty: UInt<8>, + flow: Duplex, + }, + ty: UInt<8>, + }, + TraceWire { + name: "count_lower", + child: TraceUInt { + location: TraceScalarId(29), + name: "count_lower", + ty: UInt<0>, + flow: Duplex, + }, + ty: UInt<0>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSyncReset { + index: StatePartIndex(1), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<8>, + }, + state: 0x23, + last_state: 0x23, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigBool { + index: StatePartIndex(3), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(5), + kind: EnumDiscriminant { + index: StatePartIndex(1), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(9), + ty: UInt<8>, + }, + state: 0x23, + last_state: 0x23, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigBool { + index: StatePartIndex(7), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigUInt { + index: StatePartIndex(10), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigUInt { + index: StatePartIndex(11), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigBool { + index: StatePartIndex(12), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigClock { + index: StatePartIndex(13), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(12), + kind: BigUInt { + index: StatePartIndex(14), + ty: UInt<8>, + }, + state: 0x23, + last_state: 0x23, + }, + SimTrace { + id: TraceScalarId(13), + kind: BigUInt { + index: StatePartIndex(15), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigBool { + index: StatePartIndex(16), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(15), + kind: BigClock { + index: StatePartIndex(17), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(16), + kind: BigUInt { + index: StatePartIndex(18), + ty: UInt<8>, + }, + state: 0x23, + last_state: 0x23, + }, + SimTrace { + id: TraceScalarId(17), + kind: BigBool { + index: StatePartIndex(19), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigUInt { + index: StatePartIndex(22), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigUInt { + index: StatePartIndex(25), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(20), + kind: BigBool { + index: StatePartIndex(27), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(21), + kind: BigBool { + index: StatePartIndex(30), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(22), + kind: BigBool { + index: StatePartIndex(31), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(23), + kind: BigBool { + index: StatePartIndex(32), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(24), + kind: BigBool { + index: StatePartIndex(33), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(25), + kind: BigBool { + index: StatePartIndex(34), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(26), + kind: BigBool { + index: StatePartIndex(36), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(27), + kind: BigBool { + index: StatePartIndex(39), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(28), + kind: BigUInt { + index: StatePartIndex(42), + ty: UInt<8>, + }, + state: 0x23, + last_state: 0x23, + }, + SimTrace { + id: TraceScalarId(29), + kind: BigUInt { + index: StatePartIndex(64), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 1, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<0>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + #[hdl(flip)] /* offset = 2 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + #[hdl(flip)] /* offset = 2 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<0>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + /* offset = 2 */ + data: UInt<8>, + /* offset = 10 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + /* offset = 2 */ + data: UInt<8>, + /* offset = 10 */ + mask: Bool, + }, + }, + ], + array_type: Array, 1>, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [ + StatePartIndex(3), + StatePartIndex(8), + StatePartIndex(15), + ], + event_queue: EventQueue(EventQueueData { + instant: 100 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_1_true_true.vcd b/crates/fayalite/tests/sim/expected/queue_1_true_true.vcd new file mode 100644 index 0000000..9fc4356 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/queue_1_true_true.vcd @@ -0,0 +1,1804 @@ +$timescale 1 ps $end +$scope module queue $end +$scope struct cd $end +$var wire 1 11z(a clk $end +$var wire 1 q1t|f rst $end +$upscope $end +$scope struct inp $end +$scope struct data $end +$var string 1 j|a-9 \$tag $end +$var wire 8 pjN&T HdlSome $end +$upscope $end +$var wire 1 *x8M* ready $end +$upscope $end +$scope struct out $end +$scope struct data $end +$var string 1 'Aa8} \$tag $end +$var wire 8 1b%.O HdlSome $end +$upscope $end +$var wire 1 vZD*c ready $end +$upscope $end +$var wire 1 rf7Xh count $end +$scope struct mem $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 8 (.Juw mem $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var string 0 K]Dkr addr $end +$var wire 1 P|=HX en $end +$var wire 1 z+ft% clk $end +$var wire 8 m+9ec data $end +$upscope $end +$scope struct w1 $end +$var string 0 8Oa@o addr $end +$var wire 1 VaM[2 en $end +$var wire 1 aH[{] clk $end +$var wire 8 8|1uZ data $end +$var wire 1 DYq.y mask $end +$upscope $end +$upscope $end +$var string 0 Xk?#v inp_index_reg $end +$var string 0 p19yW out_index_reg $end +$var reg 1 kEQiI maybe_full_reg $end +$var wire 1 *gdL1 inp_firing $end +$var wire 1 ;HWUJ firing $end +$var wire 1 Ph#@^ out_firing $end +$var wire 1 ;HWUJ" firing_2 $end +$var wire 1 i[~ { + len: 18, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 72, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::indexes_equal", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::empty", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::full", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count_lower", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 1, + debug_data: [ + (), + ], + layout_data: [ + MemoryData { + array_type: Array, 2>, + data: [ + // len = 0x2 + [0x0]: 0x00, + [0x1]: 0x00, + ], + }, + ], + .. + }, + }, + insns: [ + // at: ready_valid.rs:64:1 + 0: SubU { + dest: StatePartIndex(69), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + dest_width: 2, + }, + 1: CastToUInt { + dest: StatePartIndex(70), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(69), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + // at: ready_valid.rs:178:13 + 2: Copy { + dest: StatePartIndex(68), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<1> }, + src: StatePartIndex(70), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:64:1 + 3: CastToUInt { + dest: StatePartIndex(71), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(68), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<1> }, + dest_width: 2, + }, + 4: Const { + dest: StatePartIndex(65), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x2, + }, + 5: CastToUInt { + dest: StatePartIndex(66), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(65), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + dest_width: 2, + }, + 6: Const { + dest: StatePartIndex(58), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + value: 0x0, + }, + 7: CastToUInt { + dest: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(58), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 1, + }, + 8: CastToUInt { + dest: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(58), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 2, + }, + 9: Const { + dest: StatePartIndex(56), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x1, + }, + 10: CmpEq { + dest: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(56), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + }, + 11: CmpEq { + dest: StatePartIndex(62), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(56), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + }, + 12: Const { + dest: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + value: 0x0, + }, + 13: Copy { + dest: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + }, + 14: Const { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 15: Add { + dest: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 16: CastToUInt { + dest: StatePartIndex(61), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + 17: Add { + dest: StatePartIndex(63), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 18: CastToUInt { + dest: StatePartIndex(64), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(63), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + 19: Const { + dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:118:30 + 20: Copy { + dest: StatePartIndex(42), // (0x23) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:117:5 + 21: Copy { + dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:115:5 + 22: Copy { + dest: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<1> }, + src: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:114:5 + 23: Copy { + dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:64:1 + 24: Const { + dest: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + value: 0x1, + }, + // at: ready_valid.rs:113:5 + 25: Copy { + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:119:5 + 26: Copy { + dest: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:112:5 + 27: Copy { + dest: StatePartIndex(11), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<1> }, + src: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:64:1 + 28: NotU { + dest: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + width: 1, + }, + 29: CmpEq { + dest: StatePartIndex(35), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:104:5 + 30: Copy { + dest: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + src: StatePartIndex(35), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 31: And { + dest: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:107:5 + 32: Copy { + dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + src: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 33: NotU { + dest: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + width: 1, + }, + 34: And { + dest: StatePartIndex(40), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:110:5 + 35: Copy { + dest: StatePartIndex(39), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + src: StatePartIndex(40), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 36: NotU { + dest: StatePartIndex(44), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(39), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + width: 1, + }, + // at: ready_valid.rs:121:5 + 37: Copy { + dest: StatePartIndex(3), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(44), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:166:5 + 38: BranchIfZero { + target: 43, + value: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 39: BranchIfZero { + target: 41, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:169:13 + 40: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(66), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:168:9 + 41: BranchIfNonZero { + target: 43, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:171:13 + 42: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:166:5 + 43: BranchIfNonZero { + target: 45, + value: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:182:13 + 44: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(71), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:88:26 + 45: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 46: Const { + dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, + }, + // at: ready_valid.rs:86:25 + 47: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:84:31 + 48: IsNonZeroDestIsSmall { + dest: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.rst", ty: SyncReset }, + }, + 49: IsNonZeroDestIsSmall { + dest: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + 50: AndSmall { + dest: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 51: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:64:1 + 52: Const { + dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x0, + }, + // at: ready_valid.rs:91:19 + 53: CastBigToArrayIndex { + dest: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<1> }, + }, + 54: IsNonZeroDestIsSmall { + dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + }, + 55: AndSmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 56: CastBigToArrayIndex { + dest: StatePartIndex(6), // (0x1 1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(11), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<1> }, + }, + 57: IsNonZeroDestIsSmall { + dest: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + }, + 58: BranchIfSmallZero { + target: 61, + value: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 59: MemoryReadUInt { + dest: StatePartIndex(14), // (0x23) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 2>, + // data: [ + // // len = 0x2 + // [0x0]: 0x22, + // [0x1]: 0x23, + // ], + // }) (), + addr: StatePartIndex(6), // (0x1 1) SlotDebugData { name: "", ty: UInt<1> }, + stride: 8, + start: 0, + width: 8, + }, + 60: Branch { + target: 62, + }, + 61: Const { + dest: StatePartIndex(14), // (0x23) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:64:1 + 62: Copy { + dest: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 63: Copy { + dest: StatePartIndex(47), // (0x23) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(14), // (0x23) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + }, + 64: Shl { + dest: StatePartIndex(49), // (0x46) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(47), // (0x23) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 1, + }, + 65: Or { + dest: StatePartIndex(50), // (0x47) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(49), // (0x46) SlotDebugData { name: "", ty: UInt<9> }, + }, + 66: CastToUInt { + dest: StatePartIndex(51), // (0x47) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(50), // (0x47) SlotDebugData { name: "", ty: UInt<9> }, + dest_width: 9, + }, + 67: Copy { + dest: StatePartIndex(52), // (0x47) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(51), // (0x47) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: ready_valid.rs:130:5 + 68: BranchIfZero { + target: 70, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:131:9 + 69: Copy { + dest: StatePartIndex(6), // (0x47) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(52), // (0x47) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:130:5 + 70: BranchIfNonZero { + target: 72, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:136:13 + 71: Copy { + dest: StatePartIndex(6), // (0x47) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:91:19 + 72: IsNonZeroDestIsSmall { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + }, + 73: AndSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 74: Copy { + dest: StatePartIndex(8), // (0x47) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(6), // (0x47) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 75: SliceInt { + dest: StatePartIndex(9), // (0x23) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(8), // (0x47) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:79:32 + 76: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(6), // (0x47) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 77: BranchIfSmallNeImmediate { + target: 79, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 78: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 79: BranchIfSmallNeImmediate { + target: 81, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 80: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:101:5 + 81: Copy { + dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + src: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:156:5 + 82: BranchIfZero { + target: 87, + value: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:158:9 + 83: BranchIfZero { + target: 85, + value: StatePartIndex(62), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:159:13 + 84: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:158:9 + 85: BranchIfNonZero { + target: 87, + value: StatePartIndex(62), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:161:13 + 86: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(64), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:64:1 + 87: Copy { + dest: StatePartIndex(4), // (0x47) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(2), // (0x47) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 88: SliceInt { + dest: StatePartIndex(5), // (0x23) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(4), // (0x47) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:77:32 + 89: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2), // (0x47) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 90: BranchIfSmallNeImmediate { + target: 92, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 91: Copy { + dest: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 92: BranchIfSmallNeImmediate { + target: 94, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 93: Copy { + dest: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(3), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + }, + // at: ready_valid.rs:98:5 + 94: Copy { + dest: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + src: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:116:5 + 95: Copy { + dest: StatePartIndex(16), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + src: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 96: IsNonZeroDestIsSmall { + dest: StatePartIndex(10), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(16), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 97: CmpNe { + dest: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + rhs: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:141:5 + 98: BranchIfZero { + target: 100, + value: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:142:9 + 99: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:146:5 + 100: BranchIfZero { + target: 105, + value: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:148:9 + 101: BranchIfZero { + target: 103, + value: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:149:13 + 102: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:148:9 + 103: BranchIfNonZero { + target: 105, + value: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:151:13 + 104: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(61), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:118:30 + 105: BranchIfSmallNeImmediate { + target: 107, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + 106: Copy { + dest: StatePartIndex(42), // (0x23) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(5), // (0x23) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:118:5 + 107: Copy { + dest: StatePartIndex(18), // (0x23) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + src: StatePartIndex(42), // (0x23) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + }, + // at: ready_valid.rs:84:31 + 108: BranchIfSmallZero { + target: 113, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 109: BranchIfSmallNonZero { + target: 112, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 110: Copy { + dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + src: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<1> }, + }, + 111: Branch { + target: 113, + }, + 112: Copy { + dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:86:25 + 113: BranchIfSmallZero { + target: 118, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 114: BranchIfSmallNonZero { + target: 117, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 115: Copy { + dest: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + src: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<1> }, + }, + 116: Branch { + target: 118, + }, + 117: Copy { + dest: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:88:26 + 118: BranchIfSmallZero { + target: 123, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 119: BranchIfSmallNonZero { + target: 122, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 120: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + }, + 121: Branch { + target: 123, + }, + 122: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 123: BranchIfSmallZero { + target: 124, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 124: BranchIfSmallZero { + target: 132, + value: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 125: CopySmall { + dest: StatePartIndex(12), // (0x1 1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 126: CopySmall { + dest: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(10), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 127: Copy { + dest: StatePartIndex(20), // (0x23) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(18), // (0x23) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + }, + 128: Copy { + dest: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + }, + 129: BranchIfSmallZero { + target: 132, + value: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 130: BranchIfZero { + target: 132, + value: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 131: MemoryWriteUInt { + value: StatePartIndex(20), // (0x23) SlotDebugData { name: "", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 2>, + // data: [ + // // len = 0x2 + // [0x0]: 0x22, + // [0x1]: 0x23, + // ], + // }) (), + addr: StatePartIndex(12), // (0x1 1) SlotDebugData { name: "", ty: UInt<1> }, + stride: 8, + start: 0, + width: 8, + }, + 132: XorSmallImmediate { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 133: XorSmallImmediate { + dest: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:84:31 + 134: XorSmallImmediate { + dest: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:64:1 + 135: Return, + ], + .. + }, + pc: 135, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array, 2>, + data: [ + // len = 0x2 + [0x0]: 0x22, + [0x1]: 0x23, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 1, + 1, + 1, + 0, + 0, + 1, + 1, + 1, + 0, + 0, + 1, + 0, + 1, + 1, + 1, + 0, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 71, + 1, + 71, + 35, + 71, + 0, + 71, + 35, + 1, + 1, + 1, + 0, + 35, + 0, + 1, + 0, + 35, + 1, + 35, + 1, + 0, + 1, + 0, + 1, + 1, + 1, + 1, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 35, + 0, + 1, + 1, + 1, + 35, + 1, + 70, + 71, + 71, + 71, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 1, + 1, + 1, + 2, + 0, + 2, + 2, + 0, + 1, + 3, + 1, + 1, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.clk, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.rst, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.ready, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.ready, + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "queue", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "inp", + child: TraceBundle { + name: "inp", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(2), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(3), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(4), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceBundle { + name: "out", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(5), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(6), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(7), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + TraceModuleIO { + name: "count", + child: TraceUInt { + location: TraceScalarId(8), + name: "count", + ty: UInt<2>, + flow: Sink, + }, + ty: UInt<2>, + flow: Sink, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 2, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + /* offset = 3 */ + data: UInt<8>, + /* offset = 11 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + /* offset = 3 */ + data: UInt<8>, + /* offset = 11 */ + mask: Bool, + }, + }, + ], + array_type: Array, 2>, + }, + TraceReg { + name: "inp_index_reg", + child: TraceUInt { + location: TraceScalarId(18), + name: "inp_index_reg", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceReg { + name: "out_index_reg", + child: TraceUInt { + location: TraceScalarId(19), + name: "out_index_reg", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceReg { + name: "maybe_full_reg", + child: TraceBool { + location: TraceScalarId(20), + name: "maybe_full_reg", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "inp_firing", + child: TraceBool { + location: TraceScalarId(21), + name: "inp_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(22), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "out_firing", + child: TraceBool { + location: TraceScalarId(23), + name: "out_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(24), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "indexes_equal", + child: TraceBool { + location: TraceScalarId(25), + name: "indexes_equal", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "empty", + child: TraceBool { + location: TraceScalarId(26), + name: "empty", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "full", + child: TraceBool { + location: TraceScalarId(27), + name: "full", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "unwrap_or_else_out", + child: TraceUInt { + location: TraceScalarId(28), + name: "unwrap_or_else_out", + ty: UInt<8>, + flow: Duplex, + }, + ty: UInt<8>, + }, + TraceWire { + name: "count_lower", + child: TraceUInt { + location: TraceScalarId(29), + name: "count_lower", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSyncReset { + index: StatePartIndex(1), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<8>, + }, + state: 0x23, + last_state: 0x23, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigBool { + index: StatePartIndex(3), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(5), + kind: EnumDiscriminant { + index: StatePartIndex(1), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(9), + ty: UInt<8>, + }, + state: 0x23, + last_state: 0x23, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigBool { + index: StatePartIndex(7), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigUInt { + index: StatePartIndex(10), + ty: UInt<2>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigUInt { + index: StatePartIndex(11), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigBool { + index: StatePartIndex(12), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigClock { + index: StatePartIndex(13), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(12), + kind: BigUInt { + index: StatePartIndex(14), + ty: UInt<8>, + }, + state: 0x23, + last_state: 0x23, + }, + SimTrace { + id: TraceScalarId(13), + kind: BigUInt { + index: StatePartIndex(15), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigBool { + index: StatePartIndex(16), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(15), + kind: BigClock { + index: StatePartIndex(17), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(16), + kind: BigUInt { + index: StatePartIndex(18), + ty: UInt<8>, + }, + state: 0x23, + last_state: 0x23, + }, + SimTrace { + id: TraceScalarId(17), + kind: BigBool { + index: StatePartIndex(19), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigUInt { + index: StatePartIndex(22), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigUInt { + index: StatePartIndex(25), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(20), + kind: BigBool { + index: StatePartIndex(27), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(21), + kind: BigBool { + index: StatePartIndex(30), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(22), + kind: BigBool { + index: StatePartIndex(31), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(23), + kind: BigBool { + index: StatePartIndex(32), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(24), + kind: BigBool { + index: StatePartIndex(33), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(25), + kind: BigBool { + index: StatePartIndex(34), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(26), + kind: BigBool { + index: StatePartIndex(36), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(27), + kind: BigBool { + index: StatePartIndex(39), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(28), + kind: BigUInt { + index: StatePartIndex(42), + ty: UInt<8>, + }, + state: 0x23, + last_state: 0x23, + }, + SimTrace { + id: TraceScalarId(29), + kind: BigUInt { + index: StatePartIndex(68), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 2, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + /* offset = 3 */ + data: UInt<8>, + /* offset = 11 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + /* offset = 3 */ + data: UInt<8>, + /* offset = 11 */ + mask: Bool, + }, + }, + ], + array_type: Array, 2>, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [ + StatePartIndex(3), + StatePartIndex(8), + StatePartIndex(15), + ], + event_queue: EventQueue(EventQueueData { + instant: 100 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_2_false_false.vcd b/crates/fayalite/tests/sim/expected/queue_2_false_false.vcd new file mode 100644 index 0000000..92a7278 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/queue_2_false_false.vcd @@ -0,0 +1,2117 @@ +$timescale 1 ps $end +$scope module queue $end +$scope struct cd $end +$var wire 1 11z(a clk $end +$var wire 1 q1t|f rst $end +$upscope $end +$scope struct inp $end +$scope struct data $end +$var string 1 j|a-9 \$tag $end +$var wire 8 pjN&T HdlSome $end +$upscope $end +$var wire 1 *x8M* ready $end +$upscope $end +$scope struct out $end +$scope struct data $end +$var string 1 'Aa8} \$tag $end +$var wire 8 1b%.O HdlSome $end +$upscope $end +$var wire 1 vZD*c ready $end +$upscope $end +$var wire 2 rf7Xh count $end +$scope struct mem $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 8 (.Juw mem $end +$upscope $end +$scope struct \[1] $end +$var reg 8 5F$iE mem $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var wire 1 K]Dkr addr $end +$var wire 1 P|=HX en $end +$var wire 1 z+ft% clk $end +$var wire 8 m+9ec data $end +$upscope $end +$scope struct w1 $end +$var wire 1 8Oa@o addr $end +$var wire 1 VaM[2 en $end +$var wire 1 aH[{] clk $end +$var wire 8 8|1uZ data $end +$var wire 1 DYq.y mask $end +$upscope $end +$upscope $end +$var reg 1 Xk?#v inp_index_reg $end +$var reg 1 p19yW out_index_reg $end +$var reg 1 kEQiI maybe_full_reg $end +$var wire 1 *gdL1 inp_firing $end +$var wire 1 ;HWUJ firing $end +$var wire 1 Ph#@^ out_firing $end +$var wire 1 ;HWUJ" firing_2 $end +$var wire 1 i[~ { + len: 18, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 70, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::indexes_equal", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::empty", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::full", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count_lower", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 1, + debug_data: [ + (), + ], + layout_data: [ + MemoryData { + array_type: Array, 2>, + data: [ + // len = 0x2 + [0x0]: 0x00, + [0x1]: 0x00, + ], + }, + ], + .. + }, + }, + insns: [ + // at: ready_valid.rs:64:1 + 0: SubU { + dest: StatePartIndex(67), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + dest_width: 2, + }, + 1: CastToUInt { + dest: StatePartIndex(68), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(67), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + // at: ready_valid.rs:178:13 + 2: Copy { + dest: StatePartIndex(66), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<1> }, + src: StatePartIndex(68), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:64:1 + 3: CastToUInt { + dest: StatePartIndex(69), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(66), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<1> }, + dest_width: 2, + }, + 4: Const { + dest: StatePartIndex(63), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x2, + }, + 5: CastToUInt { + dest: StatePartIndex(64), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(63), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + dest_width: 2, + }, + 6: Const { + dest: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + value: 0x0, + }, + 7: CastToUInt { + dest: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 1, + }, + 8: CastToUInt { + dest: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 2, + }, + 9: Const { + dest: StatePartIndex(54), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x1, + }, + 10: CmpEq { + dest: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(54), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + }, + 11: CmpEq { + dest: StatePartIndex(60), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(54), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + }, + 12: Const { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 13: Add { + dest: StatePartIndex(58), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 14: CastToUInt { + dest: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(58), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + 15: Add { + dest: StatePartIndex(61), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 16: CastToUInt { + dest: StatePartIndex(62), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(61), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + 17: Const { + dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:118:30 + 18: Copy { + dest: StatePartIndex(42), // (0x26) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:117:5 + 19: Copy { + dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:115:5 + 20: Copy { + dest: StatePartIndex(15), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<1> }, + src: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:114:5 + 21: Copy { + dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:64:1 + 22: Const { + dest: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + value: 0x1, + }, + // at: ready_valid.rs:113:5 + 23: Copy { + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:119:5 + 24: Copy { + dest: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:112:5 + 25: Copy { + dest: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<1> }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:64:1 + 26: NotU { + dest: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + width: 1, + }, + 27: CmpEq { + dest: StatePartIndex(35), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:104:5 + 28: Copy { + dest: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + src: StatePartIndex(35), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 29: And { + dest: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:107:5 + 30: Copy { + dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + src: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 31: NotU { + dest: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + width: 1, + }, + 32: And { + dest: StatePartIndex(40), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:110:5 + 33: Copy { + dest: StatePartIndex(39), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + src: StatePartIndex(40), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 34: NotU { + dest: StatePartIndex(44), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(39), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + width: 1, + }, + // at: ready_valid.rs:121:5 + 35: Copy { + dest: StatePartIndex(3), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(44), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:166:5 + 36: BranchIfZero { + target: 41, + value: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 37: BranchIfZero { + target: 39, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:169:13 + 38: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(64), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:168:9 + 39: BranchIfNonZero { + target: 41, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:171:13 + 40: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:166:5 + 41: BranchIfNonZero { + target: 43, + value: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:182:13 + 42: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(69), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:88:26 + 43: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 44: Const { + dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, + }, + // at: ready_valid.rs:86:25 + 45: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:84:31 + 46: IsNonZeroDestIsSmall { + dest: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.rst", ty: SyncReset }, + }, + 47: IsNonZeroDestIsSmall { + dest: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + 48: AndSmall { + dest: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 49: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:64:1 + 50: Const { + dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x0, + }, + // at: ready_valid.rs:91:19 + 51: CastBigToArrayIndex { + dest: StatePartIndex(11), // (0x1 1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(15), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<1> }, + }, + 52: IsNonZeroDestIsSmall { + dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + }, + 53: AndSmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 54: CastBigToArrayIndex { + dest: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<1> }, + }, + 55: IsNonZeroDestIsSmall { + dest: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + }, + 56: BranchIfSmallZero { + target: 59, + value: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 57: MemoryReadUInt { + dest: StatePartIndex(14), // (0x26) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 2>, + // data: [ + // // len = 0x2 + // [0x0]: 0x26, + // [0x1]: 0x25, + // ], + // }) (), + addr: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + stride: 8, + start: 0, + width: 8, + }, + 58: Branch { + target: 60, + }, + 59: Const { + dest: StatePartIndex(14), // (0x26) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:64:1 + 60: Copy { + dest: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 61: Copy { + dest: StatePartIndex(47), // (0x26) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(14), // (0x26) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + }, + 62: Shl { + dest: StatePartIndex(49), // (0x4c) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(47), // (0x26) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 1, + }, + 63: Or { + dest: StatePartIndex(50), // (0x4d) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(49), // (0x4c) SlotDebugData { name: "", ty: UInt<9> }, + }, + 64: CastToUInt { + dest: StatePartIndex(51), // (0x4d) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(50), // (0x4d) SlotDebugData { name: "", ty: UInt<9> }, + dest_width: 9, + }, + 65: Copy { + dest: StatePartIndex(52), // (0x4d) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(51), // (0x4d) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: ready_valid.rs:130:5 + 66: BranchIfZero { + target: 68, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:131:9 + 67: Copy { + dest: StatePartIndex(6), // (0x4d) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(52), // (0x4d) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:130:5 + 68: BranchIfNonZero { + target: 70, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:134:13 + 69: Copy { + dest: StatePartIndex(6), // (0x4d) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(2), // (0x4d) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:91:19 + 70: IsNonZeroDestIsSmall { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + }, + 71: AndSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 72: Copy { + dest: StatePartIndex(8), // (0x4d) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(6), // (0x4d) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 73: SliceInt { + dest: StatePartIndex(9), // (0x26) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(8), // (0x4d) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:79:32 + 74: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(6), // (0x4d) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 75: BranchIfSmallNeImmediate { + target: 77, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 76: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 77: BranchIfSmallNeImmediate { + target: 79, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 78: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:101:5 + 79: Copy { + dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + src: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:156:5 + 80: BranchIfZero { + target: 85, + value: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:158:9 + 81: BranchIfZero { + target: 83, + value: StatePartIndex(60), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:159:13 + 82: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:158:9 + 83: BranchIfNonZero { + target: 85, + value: StatePartIndex(60), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:161:13 + 84: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(62), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:64:1 + 85: Copy { + dest: StatePartIndex(4), // (0x4d) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(2), // (0x4d) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 86: SliceInt { + dest: StatePartIndex(5), // (0x26) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(4), // (0x4d) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:77:32 + 87: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2), // (0x4d) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 88: BranchIfSmallNeImmediate { + target: 90, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 89: Copy { + dest: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 90: BranchIfSmallNeImmediate { + target: 92, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 91: Copy { + dest: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(3), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + }, + // at: ready_valid.rs:98:5 + 92: Copy { + dest: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + src: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:116:5 + 93: Copy { + dest: StatePartIndex(16), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + src: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 94: IsNonZeroDestIsSmall { + dest: StatePartIndex(10), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(16), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 95: CmpNe { + dest: StatePartIndex(53), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + rhs: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:141:5 + 96: BranchIfZero { + target: 98, + value: StatePartIndex(53), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:142:9 + 97: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:146:5 + 98: BranchIfZero { + target: 103, + value: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:148:9 + 99: BranchIfZero { + target: 101, + value: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:149:13 + 100: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:148:9 + 101: BranchIfNonZero { + target: 103, + value: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:151:13 + 102: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:118:30 + 103: BranchIfSmallNeImmediate { + target: 105, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + 104: Copy { + dest: StatePartIndex(42), // (0x26) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(5), // (0x26) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:118:5 + 105: Copy { + dest: StatePartIndex(18), // (0x26) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + src: StatePartIndex(42), // (0x26) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + }, + // at: ready_valid.rs:84:31 + 106: BranchIfSmallZero { + target: 111, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 107: BranchIfSmallNonZero { + target: 110, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 108: Copy { + dest: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + src: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<1> }, + }, + 109: Branch { + target: 111, + }, + 110: Copy { + dest: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:86:25 + 111: BranchIfSmallZero { + target: 116, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 112: BranchIfSmallNonZero { + target: 115, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 113: Copy { + dest: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + src: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<1> }, + }, + 114: Branch { + target: 116, + }, + 115: Copy { + dest: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:88:26 + 116: BranchIfSmallZero { + target: 121, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 117: BranchIfSmallNonZero { + target: 120, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 118: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + }, + 119: Branch { + target: 121, + }, + 120: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 121: BranchIfSmallZero { + target: 122, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 122: BranchIfSmallZero { + target: 130, + value: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 123: CopySmall { + dest: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(11), // (0x1 1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 124: CopySmall { + dest: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(10), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 125: Copy { + dest: StatePartIndex(20), // (0x26) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(18), // (0x26) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + }, + 126: Copy { + dest: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + }, + 127: BranchIfSmallZero { + target: 130, + value: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 128: BranchIfZero { + target: 130, + value: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 129: MemoryWriteUInt { + value: StatePartIndex(20), // (0x26) SlotDebugData { name: "", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 2>, + // data: [ + // // len = 0x2 + // [0x0]: 0x26, + // [0x1]: 0x25, + // ], + // }) (), + addr: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + stride: 8, + start: 0, + width: 8, + }, + 130: XorSmallImmediate { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 131: XorSmallImmediate { + dest: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:84:31 + 132: XorSmallImmediate { + dest: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:64:1 + 133: Return, + ], + .. + }, + pc: 133, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array, 2>, + data: [ + // len = 0x2 + [0x0]: 0x26, + [0x1]: 0x25, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 1, + 1, + 1, + 0, + 0, + 1, + 0, + 1, + 0, + 0, + 1, + 1, + 0, + 1, + 1, + 0, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 77, + 1, + 77, + 38, + 77, + 0, + 77, + 38, + 1, + 0, + 1, + 0, + 38, + 1, + 1, + 0, + 38, + 1, + 38, + 1, + 1, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 38, + 0, + 1, + 1, + 1, + 38, + 1, + 76, + 77, + 77, + 77, + 1, + 1, + 1, + 0, + 0, + 2, + 0, + 0, + 1, + 1, + 2, + 2, + 0, + 1, + 1, + 1, + 1, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.clk, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.rst, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.ready, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.ready, + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "queue", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "inp", + child: TraceBundle { + name: "inp", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(2), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(3), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(4), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceBundle { + name: "out", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(5), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(6), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(7), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + TraceModuleIO { + name: "count", + child: TraceUInt { + location: TraceScalarId(8), + name: "count", + ty: UInt<2>, + flow: Sink, + }, + ty: UInt<2>, + flow: Sink, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 2, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + /* offset = 3 */ + data: UInt<8>, + /* offset = 11 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + /* offset = 3 */ + data: UInt<8>, + /* offset = 11 */ + mask: Bool, + }, + }, + ], + array_type: Array, 2>, + }, + TraceReg { + name: "inp_index_reg", + child: TraceUInt { + location: TraceScalarId(18), + name: "inp_index_reg", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceReg { + name: "out_index_reg", + child: TraceUInt { + location: TraceScalarId(19), + name: "out_index_reg", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceReg { + name: "maybe_full_reg", + child: TraceBool { + location: TraceScalarId(20), + name: "maybe_full_reg", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "inp_firing", + child: TraceBool { + location: TraceScalarId(21), + name: "inp_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(22), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "out_firing", + child: TraceBool { + location: TraceScalarId(23), + name: "out_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(24), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "indexes_equal", + child: TraceBool { + location: TraceScalarId(25), + name: "indexes_equal", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "empty", + child: TraceBool { + location: TraceScalarId(26), + name: "empty", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "full", + child: TraceBool { + location: TraceScalarId(27), + name: "full", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "unwrap_or_else_out", + child: TraceUInt { + location: TraceScalarId(28), + name: "unwrap_or_else_out", + ty: UInt<8>, + flow: Duplex, + }, + ty: UInt<8>, + }, + TraceWire { + name: "count_lower", + child: TraceUInt { + location: TraceScalarId(29), + name: "count_lower", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSyncReset { + index: StatePartIndex(1), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<8>, + }, + state: 0x26, + last_state: 0x26, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigBool { + index: StatePartIndex(3), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(5), + kind: EnumDiscriminant { + index: StatePartIndex(1), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(9), + ty: UInt<8>, + }, + state: 0x26, + last_state: 0x26, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigBool { + index: StatePartIndex(7), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigUInt { + index: StatePartIndex(10), + ty: UInt<2>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigUInt { + index: StatePartIndex(11), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigBool { + index: StatePartIndex(12), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigClock { + index: StatePartIndex(13), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(12), + kind: BigUInt { + index: StatePartIndex(14), + ty: UInt<8>, + }, + state: 0x26, + last_state: 0x26, + }, + SimTrace { + id: TraceScalarId(13), + kind: BigUInt { + index: StatePartIndex(15), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigBool { + index: StatePartIndex(16), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(15), + kind: BigClock { + index: StatePartIndex(17), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(16), + kind: BigUInt { + index: StatePartIndex(18), + ty: UInt<8>, + }, + state: 0x26, + last_state: 0x26, + }, + SimTrace { + id: TraceScalarId(17), + kind: BigBool { + index: StatePartIndex(19), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigUInt { + index: StatePartIndex(22), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigUInt { + index: StatePartIndex(25), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(20), + kind: BigBool { + index: StatePartIndex(27), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(21), + kind: BigBool { + index: StatePartIndex(30), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(22), + kind: BigBool { + index: StatePartIndex(31), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(23), + kind: BigBool { + index: StatePartIndex(32), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(24), + kind: BigBool { + index: StatePartIndex(33), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(25), + kind: BigBool { + index: StatePartIndex(34), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(26), + kind: BigBool { + index: StatePartIndex(36), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(27), + kind: BigBool { + index: StatePartIndex(39), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(28), + kind: BigUInt { + index: StatePartIndex(42), + ty: UInt<8>, + }, + state: 0x26, + last_state: 0x26, + }, + SimTrace { + id: TraceScalarId(29), + kind: BigUInt { + index: StatePartIndex(66), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 2, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + /* offset = 3 */ + data: UInt<8>, + /* offset = 11 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + /* offset = 3 */ + data: UInt<8>, + /* offset = 11 */ + mask: Bool, + }, + }, + ], + array_type: Array, 2>, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [ + StatePartIndex(3), + StatePartIndex(8), + StatePartIndex(15), + ], + event_queue: EventQueue(EventQueueData { + instant: 100 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_2_false_true.vcd b/crates/fayalite/tests/sim/expected/queue_2_false_true.vcd new file mode 100644 index 0000000..55da6e1 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/queue_2_false_true.vcd @@ -0,0 +1,2075 @@ +$timescale 1 ps $end +$scope module queue $end +$scope struct cd $end +$var wire 1 11z(a clk $end +$var wire 1 q1t|f rst $end +$upscope $end +$scope struct inp $end +$scope struct data $end +$var string 1 j|a-9 \$tag $end +$var wire 8 pjN&T HdlSome $end +$upscope $end +$var wire 1 *x8M* ready $end +$upscope $end +$scope struct out $end +$scope struct data $end +$var string 1 'Aa8} \$tag $end +$var wire 8 1b%.O HdlSome $end +$upscope $end +$var wire 1 vZD*c ready $end +$upscope $end +$var wire 2 rf7Xh count $end +$scope struct mem $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 8 (.Juw mem $end +$upscope $end +$scope struct \[1] $end +$var reg 8 5F$iE mem $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var wire 1 K]Dkr addr $end +$var wire 1 P|=HX en $end +$var wire 1 z+ft% clk $end +$var wire 8 m+9ec data $end +$upscope $end +$scope struct w1 $end +$var wire 1 8Oa@o addr $end +$var wire 1 VaM[2 en $end +$var wire 1 aH[{] clk $end +$var wire 8 8|1uZ data $end +$var wire 1 DYq.y mask $end +$upscope $end +$upscope $end +$var reg 1 Xk?#v inp_index_reg $end +$var reg 1 p19yW out_index_reg $end +$var reg 1 kEQiI maybe_full_reg $end +$var wire 1 *gdL1 inp_firing $end +$var wire 1 ;HWUJ firing $end +$var wire 1 Ph#@^ out_firing $end +$var wire 1 ;HWUJ" firing_2 $end +$var wire 1 i[~ { + len: 18, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 72, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::indexes_equal", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::empty", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::full", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count_lower", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 1, + debug_data: [ + (), + ], + layout_data: [ + MemoryData { + array_type: Array, 2>, + data: [ + // len = 0x2 + [0x0]: 0x00, + [0x1]: 0x00, + ], + }, + ], + .. + }, + }, + insns: [ + // at: ready_valid.rs:64:1 + 0: SubU { + dest: StatePartIndex(69), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + dest_width: 2, + }, + 1: CastToUInt { + dest: StatePartIndex(70), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(69), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + // at: ready_valid.rs:178:13 + 2: Copy { + dest: StatePartIndex(68), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<1> }, + src: StatePartIndex(70), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:64:1 + 3: CastToUInt { + dest: StatePartIndex(71), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(68), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<1> }, + dest_width: 2, + }, + 4: Const { + dest: StatePartIndex(65), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x2, + }, + 5: CastToUInt { + dest: StatePartIndex(66), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(65), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + dest_width: 2, + }, + 6: Const { + dest: StatePartIndex(58), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + value: 0x0, + }, + 7: CastToUInt { + dest: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(58), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 1, + }, + 8: CastToUInt { + dest: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(58), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 2, + }, + 9: Const { + dest: StatePartIndex(56), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x1, + }, + 10: CmpEq { + dest: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(56), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + }, + 11: CmpEq { + dest: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(56), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + }, + 12: Const { + dest: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + value: 0x0, + }, + 13: Copy { + dest: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + }, + 14: Const { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 15: Add { + dest: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 16: CastToUInt { + dest: StatePartIndex(61), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + 17: Add { + dest: StatePartIndex(63), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 18: CastToUInt { + dest: StatePartIndex(64), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(63), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + 19: Const { + dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:118:30 + 20: Copy { + dest: StatePartIndex(42), // (0x27) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:117:5 + 21: Copy { + dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:115:5 + 22: Copy { + dest: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<1> }, + src: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:114:5 + 23: Copy { + dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:64:1 + 24: Const { + dest: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + value: 0x1, + }, + // at: ready_valid.rs:113:5 + 25: Copy { + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:119:5 + 26: Copy { + dest: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:112:5 + 27: Copy { + dest: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<1> }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:64:1 + 28: NotU { + dest: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + width: 1, + }, + 29: CmpEq { + dest: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:104:5 + 30: Copy { + dest: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + src: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 31: And { + dest: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:107:5 + 32: Copy { + dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + src: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 33: NotU { + dest: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + width: 1, + }, + 34: And { + dest: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:110:5 + 35: Copy { + dest: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + src: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 36: NotU { + dest: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + width: 1, + }, + // at: ready_valid.rs:121:5 + 37: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:124:9 + 38: BranchIfZero { + target: 40, + value: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:125:13 + 39: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:166:5 + 40: BranchIfZero { + target: 45, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 41: BranchIfZero { + target: 43, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:169:13 + 42: Copy { + dest: StatePartIndex(10), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(66), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:168:9 + 43: BranchIfNonZero { + target: 45, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:171:13 + 44: Copy { + dest: StatePartIndex(10), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:166:5 + 45: BranchIfNonZero { + target: 47, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:182:13 + 46: Copy { + dest: StatePartIndex(10), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(71), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:88:26 + 47: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 48: Const { + dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, + }, + // at: ready_valid.rs:86:25 + 49: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:84:31 + 50: IsNonZeroDestIsSmall { + dest: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.rst", ty: SyncReset }, + }, + 51: IsNonZeroDestIsSmall { + dest: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + 52: AndSmall { + dest: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 53: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:64:1 + 54: Const { + dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x0, + }, + // at: ready_valid.rs:91:19 + 55: CastBigToArrayIndex { + dest: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<1> }, + }, + 56: IsNonZeroDestIsSmall { + dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + }, + 57: AndSmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 58: CastBigToArrayIndex { + dest: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<1> }, + }, + 59: IsNonZeroDestIsSmall { + dest: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + }, + 60: BranchIfSmallZero { + target: 63, + value: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 61: MemoryReadUInt { + dest: StatePartIndex(14), // (0x26) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 2>, + // data: [ + // // len = 0x2 + // [0x0]: 0x26, + // [0x1]: 0x27, + // ], + // }) (), + addr: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + stride: 8, + start: 0, + width: 8, + }, + 62: Branch { + target: 64, + }, + 63: Const { + dest: StatePartIndex(14), // (0x26) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:64:1 + 64: Copy { + dest: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 65: Copy { + dest: StatePartIndex(47), // (0x26) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(14), // (0x26) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + }, + 66: Shl { + dest: StatePartIndex(49), // (0x4c) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(47), // (0x26) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 1, + }, + 67: Or { + dest: StatePartIndex(50), // (0x4d) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(49), // (0x4c) SlotDebugData { name: "", ty: UInt<9> }, + }, + 68: CastToUInt { + dest: StatePartIndex(51), // (0x4d) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(50), // (0x4d) SlotDebugData { name: "", ty: UInt<9> }, + dest_width: 9, + }, + 69: Copy { + dest: StatePartIndex(52), // (0x4d) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(51), // (0x4d) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: ready_valid.rs:130:5 + 70: BranchIfZero { + target: 72, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:131:9 + 71: Copy { + dest: StatePartIndex(6), // (0x4d) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(52), // (0x4d) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:130:5 + 72: BranchIfNonZero { + target: 74, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:136:13 + 73: Copy { + dest: StatePartIndex(6), // (0x4d) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:91:19 + 74: IsNonZeroDestIsSmall { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + }, + 75: AndSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 76: Copy { + dest: StatePartIndex(8), // (0x4d) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(6), // (0x4d) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 77: SliceInt { + dest: StatePartIndex(9), // (0x26) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(8), // (0x4d) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:79:32 + 78: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(6), // (0x4d) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 79: BranchIfSmallNeImmediate { + target: 81, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 80: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 81: BranchIfSmallNeImmediate { + target: 83, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 82: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:101:5 + 83: Copy { + dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + src: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:156:5 + 84: BranchIfZero { + target: 89, + value: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:158:9 + 85: BranchIfZero { + target: 87, + value: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:159:13 + 86: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:158:9 + 87: BranchIfNonZero { + target: 89, + value: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:161:13 + 88: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(64), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:64:1 + 89: Copy { + dest: StatePartIndex(4), // (0x4f) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(2), // (0x4f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 90: SliceInt { + dest: StatePartIndex(5), // (0x27) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(4), // (0x4f) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:77:32 + 91: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2), // (0x4f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 92: BranchIfSmallNeImmediate { + target: 94, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 93: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 94: BranchIfSmallNeImmediate { + target: 96, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 95: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + }, + // at: ready_valid.rs:98:5 + 96: Copy { + dest: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + src: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:116:5 + 97: Copy { + dest: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 98: IsNonZeroDestIsSmall { + dest: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 99: CmpNe { + dest: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + rhs: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:141:5 + 100: BranchIfZero { + target: 102, + value: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:142:9 + 101: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:146:5 + 102: BranchIfZero { + target: 107, + value: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:148:9 + 103: BranchIfZero { + target: 105, + value: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:149:13 + 104: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:148:9 + 105: BranchIfNonZero { + target: 107, + value: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:151:13 + 106: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(61), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:118:30 + 107: BranchIfSmallNeImmediate { + target: 109, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + 108: Copy { + dest: StatePartIndex(42), // (0x27) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(5), // (0x27) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:118:5 + 109: Copy { + dest: StatePartIndex(18), // (0x27) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + src: StatePartIndex(42), // (0x27) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + }, + // at: ready_valid.rs:84:31 + 110: BranchIfSmallZero { + target: 115, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 111: BranchIfSmallNonZero { + target: 114, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 112: Copy { + dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + src: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<1> }, + }, + 113: Branch { + target: 115, + }, + 114: Copy { + dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:86:25 + 115: BranchIfSmallZero { + target: 120, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 116: BranchIfSmallNonZero { + target: 119, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 117: Copy { + dest: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + src: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<1> }, + }, + 118: Branch { + target: 120, + }, + 119: Copy { + dest: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:88:26 + 120: BranchIfSmallZero { + target: 125, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 121: BranchIfSmallNonZero { + target: 124, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 122: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + }, + 123: Branch { + target: 125, + }, + 124: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 125: BranchIfSmallZero { + target: 126, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 126: BranchIfSmallZero { + target: 134, + value: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 127: CopySmall { + dest: StatePartIndex(12), // (0x1 1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 128: CopySmall { + dest: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 129: Copy { + dest: StatePartIndex(20), // (0x27) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(18), // (0x27) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + }, + 130: Copy { + dest: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + }, + 131: BranchIfSmallZero { + target: 134, + value: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 132: BranchIfZero { + target: 134, + value: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 133: MemoryWriteUInt { + value: StatePartIndex(20), // (0x27) SlotDebugData { name: "", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 2>, + // data: [ + // // len = 0x2 + // [0x0]: 0x26, + // [0x1]: 0x27, + // ], + // }) (), + addr: StatePartIndex(12), // (0x1 1) SlotDebugData { name: "", ty: UInt<1> }, + stride: 8, + start: 0, + width: 8, + }, + 134: XorSmallImmediate { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 135: XorSmallImmediate { + dest: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:84:31 + 136: XorSmallImmediate { + dest: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:64:1 + 137: Return, + ], + .. + }, + pc: 137, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array, 2>, + data: [ + // len = 0x2 + [0x0]: 0x26, + [0x1]: 0x27, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 1, + 1, + 1, + 0, + 0, + 1, + 0, + 1, + 0, + 0, + 0, + 0, + 1, + 1, + 1, + 0, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 79, + 0, + 79, + 39, + 77, + 0, + 77, + 38, + 2, + 0, + 1, + 0, + 38, + 0, + 0, + 0, + 39, + 1, + 39, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 1, + 1, + 1, + 39, + 0, + 0, + 1, + 1, + 38, + 1, + 76, + 77, + 77, + 77, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 1, + 1, + 0, + 1, + 1, + 2, + 2, + 0, + 0, + 0, + 0, + 0, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.clk, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.rst, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.ready, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.ready, + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "queue", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "inp", + child: TraceBundle { + name: "inp", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(2), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(3), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(4), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceBundle { + name: "out", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(5), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(6), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(7), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + TraceModuleIO { + name: "count", + child: TraceUInt { + location: TraceScalarId(8), + name: "count", + ty: UInt<2>, + flow: Sink, + }, + ty: UInt<2>, + flow: Sink, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 2, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + /* offset = 3 */ + data: UInt<8>, + /* offset = 11 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + /* offset = 3 */ + data: UInt<8>, + /* offset = 11 */ + mask: Bool, + }, + }, + ], + array_type: Array, 2>, + }, + TraceReg { + name: "inp_index_reg", + child: TraceUInt { + location: TraceScalarId(18), + name: "inp_index_reg", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceReg { + name: "out_index_reg", + child: TraceUInt { + location: TraceScalarId(19), + name: "out_index_reg", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceReg { + name: "maybe_full_reg", + child: TraceBool { + location: TraceScalarId(20), + name: "maybe_full_reg", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "inp_firing", + child: TraceBool { + location: TraceScalarId(21), + name: "inp_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(22), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "out_firing", + child: TraceBool { + location: TraceScalarId(23), + name: "out_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(24), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "indexes_equal", + child: TraceBool { + location: TraceScalarId(25), + name: "indexes_equal", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "empty", + child: TraceBool { + location: TraceScalarId(26), + name: "empty", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "full", + child: TraceBool { + location: TraceScalarId(27), + name: "full", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "unwrap_or_else_out", + child: TraceUInt { + location: TraceScalarId(28), + name: "unwrap_or_else_out", + ty: UInt<8>, + flow: Duplex, + }, + ty: UInt<8>, + }, + TraceWire { + name: "count_lower", + child: TraceUInt { + location: TraceScalarId(29), + name: "count_lower", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSyncReset { + index: StatePartIndex(1), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<8>, + }, + state: 0x27, + last_state: 0x27, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigBool { + index: StatePartIndex(3), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(5), + kind: EnumDiscriminant { + index: StatePartIndex(1), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(9), + ty: UInt<8>, + }, + state: 0x26, + last_state: 0x26, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigBool { + index: StatePartIndex(7), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigUInt { + index: StatePartIndex(10), + ty: UInt<2>, + }, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigUInt { + index: StatePartIndex(11), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigBool { + index: StatePartIndex(12), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigClock { + index: StatePartIndex(13), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(12), + kind: BigUInt { + index: StatePartIndex(14), + ty: UInt<8>, + }, + state: 0x26, + last_state: 0x26, + }, + SimTrace { + id: TraceScalarId(13), + kind: BigUInt { + index: StatePartIndex(15), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigBool { + index: StatePartIndex(16), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(15), + kind: BigClock { + index: StatePartIndex(17), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(16), + kind: BigUInt { + index: StatePartIndex(18), + ty: UInt<8>, + }, + state: 0x27, + last_state: 0x27, + }, + SimTrace { + id: TraceScalarId(17), + kind: BigBool { + index: StatePartIndex(19), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigUInt { + index: StatePartIndex(22), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigUInt { + index: StatePartIndex(25), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(20), + kind: BigBool { + index: StatePartIndex(27), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(21), + kind: BigBool { + index: StatePartIndex(30), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(22), + kind: BigBool { + index: StatePartIndex(31), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(23), + kind: BigBool { + index: StatePartIndex(32), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(24), + kind: BigBool { + index: StatePartIndex(33), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(25), + kind: BigBool { + index: StatePartIndex(34), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(26), + kind: BigBool { + index: StatePartIndex(36), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(27), + kind: BigBool { + index: StatePartIndex(39), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(28), + kind: BigUInt { + index: StatePartIndex(42), + ty: UInt<8>, + }, + state: 0x27, + last_state: 0x27, + }, + SimTrace { + id: TraceScalarId(29), + kind: BigUInt { + index: StatePartIndex(68), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 2, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + /* offset = 3 */ + data: UInt<8>, + /* offset = 11 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + /* offset = 3 */ + data: UInt<8>, + /* offset = 11 */ + mask: Bool, + }, + }, + ], + array_type: Array, 2>, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [ + StatePartIndex(3), + StatePartIndex(8), + StatePartIndex(15), + ], + event_queue: EventQueue(EventQueueData { + instant: 100 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_2_true_false.vcd b/crates/fayalite/tests/sim/expected/queue_2_true_false.vcd new file mode 100644 index 0000000..e54b985 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/queue_2_true_false.vcd @@ -0,0 +1,2035 @@ +$timescale 1 ps $end +$scope module queue $end +$scope struct cd $end +$var wire 1 11z(a clk $end +$var wire 1 q1t|f rst $end +$upscope $end +$scope struct inp $end +$scope struct data $end +$var string 1 j|a-9 \$tag $end +$var wire 8 pjN&T HdlSome $end +$upscope $end +$var wire 1 *x8M* ready $end +$upscope $end +$scope struct out $end +$scope struct data $end +$var string 1 'Aa8} \$tag $end +$var wire 8 1b%.O HdlSome $end +$upscope $end +$var wire 1 vZD*c ready $end +$upscope $end +$var wire 2 rf7Xh count $end +$scope struct mem $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 8 (.Juw mem $end +$upscope $end +$scope struct \[1] $end +$var reg 8 5F$iE mem $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var wire 1 K]Dkr addr $end +$var wire 1 P|=HX en $end +$var wire 1 z+ft% clk $end +$var wire 8 m+9ec data $end +$upscope $end +$scope struct w1 $end +$var wire 1 8Oa@o addr $end +$var wire 1 VaM[2 en $end +$var wire 1 aH[{] clk $end +$var wire 8 8|1uZ data $end +$var wire 1 DYq.y mask $end +$upscope $end +$upscope $end +$var reg 1 Xk?#v inp_index_reg $end +$var reg 1 p19yW out_index_reg $end +$var reg 1 kEQiI maybe_full_reg $end +$var wire 1 *gdL1 inp_firing $end +$var wire 1 ;HWUJ firing $end +$var wire 1 Ph#@^ out_firing $end +$var wire 1 ;HWUJ" firing_2 $end +$var wire 1 i[~ { + len: 18, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 70, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::indexes_equal", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::empty", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::full", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count_lower", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 1, + debug_data: [ + (), + ], + layout_data: [ + MemoryData { + array_type: Array, 2>, + data: [ + // len = 0x2 + [0x0]: 0x00, + [0x1]: 0x00, + ], + }, + ], + .. + }, + }, + insns: [ + // at: ready_valid.rs:64:1 + 0: SubU { + dest: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + dest_width: 2, + }, + 1: CastToUInt { + dest: StatePartIndex(68), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + // at: ready_valid.rs:178:13 + 2: Copy { + dest: StatePartIndex(66), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<1> }, + src: StatePartIndex(68), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:64:1 + 3: CastToUInt { + dest: StatePartIndex(69), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(66), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<1> }, + dest_width: 2, + }, + 4: Const { + dest: StatePartIndex(63), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x2, + }, + 5: CastToUInt { + dest: StatePartIndex(64), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(63), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + dest_width: 2, + }, + 6: Const { + dest: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + value: 0x0, + }, + 7: CastToUInt { + dest: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 1, + }, + 8: CastToUInt { + dest: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 2, + }, + 9: Const { + dest: StatePartIndex(54), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x1, + }, + 10: CmpEq { + dest: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(54), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + }, + 11: CmpEq { + dest: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(54), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + }, + 12: Const { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 13: Add { + dest: StatePartIndex(58), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 14: CastToUInt { + dest: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(58), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + 15: Add { + dest: StatePartIndex(61), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 16: CastToUInt { + dest: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(61), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + 17: Const { + dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:118:30 + 18: Copy { + dest: StatePartIndex(42), // (0x2a) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:117:5 + 19: Copy { + dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:115:5 + 20: Copy { + dest: StatePartIndex(15), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<1> }, + src: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:114:5 + 21: Copy { + dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:64:1 + 22: Const { + dest: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + value: 0x1, + }, + // at: ready_valid.rs:113:5 + 23: Copy { + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:119:5 + 24: Copy { + dest: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:112:5 + 25: Copy { + dest: StatePartIndex(11), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<1> }, + src: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:64:1 + 26: NotU { + dest: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + width: 1, + }, + 27: CmpEq { + dest: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:104:5 + 28: Copy { + dest: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + src: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 29: And { + dest: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:107:5 + 30: Copy { + dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + src: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 31: NotU { + dest: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + width: 1, + }, + 32: And { + dest: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:110:5 + 33: Copy { + dest: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + src: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 34: NotU { + dest: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + width: 1, + }, + // at: ready_valid.rs:121:5 + 35: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:124:9 + 36: BranchIfZero { + target: 38, + value: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:125:13 + 37: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:166:5 + 38: BranchIfZero { + target: 43, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 39: BranchIfZero { + target: 41, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:169:13 + 40: Copy { + dest: StatePartIndex(10), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(64), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:168:9 + 41: BranchIfNonZero { + target: 43, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:171:13 + 42: Copy { + dest: StatePartIndex(10), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:166:5 + 43: BranchIfNonZero { + target: 45, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:182:13 + 44: Copy { + dest: StatePartIndex(10), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(69), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:88:26 + 45: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 46: Const { + dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, + }, + // at: ready_valid.rs:86:25 + 47: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:84:31 + 48: IsNonZeroDestIsSmall { + dest: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.rst", ty: SyncReset }, + }, + 49: IsNonZeroDestIsSmall { + dest: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + 50: AndSmall { + dest: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 51: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:64:1 + 52: Const { + dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x0, + }, + // at: ready_valid.rs:91:19 + 53: CastBigToArrayIndex { + dest: StatePartIndex(11), // (0x1 1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(15), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<1> }, + }, + 54: IsNonZeroDestIsSmall { + dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + }, + 55: AndSmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 56: CastBigToArrayIndex { + dest: StatePartIndex(6), // (0x1 1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(11), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<1> }, + }, + 57: IsNonZeroDestIsSmall { + dest: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + }, + 58: BranchIfSmallZero { + target: 61, + value: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 59: MemoryReadUInt { + dest: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 2>, + // data: [ + // // len = 0x2 + // [0x0]: 0x2a, + // [0x1]: 0x29, + // ], + // }) (), + addr: StatePartIndex(6), // (0x1 1) SlotDebugData { name: "", ty: UInt<1> }, + stride: 8, + start: 0, + width: 8, + }, + 60: Branch { + target: 62, + }, + 61: Const { + dest: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:64:1 + 62: Copy { + dest: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 63: Copy { + dest: StatePartIndex(47), // (0x29) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + }, + 64: Shl { + dest: StatePartIndex(49), // (0x52) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(47), // (0x29) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 1, + }, + 65: Or { + dest: StatePartIndex(50), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(49), // (0x52) SlotDebugData { name: "", ty: UInt<9> }, + }, + 66: CastToUInt { + dest: StatePartIndex(51), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(50), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + dest_width: 9, + }, + 67: Copy { + dest: StatePartIndex(52), // (0x53) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(51), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: ready_valid.rs:130:5 + 68: BranchIfZero { + target: 70, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:131:9 + 69: Copy { + dest: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(52), // (0x53) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:130:5 + 70: BranchIfNonZero { + target: 72, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:134:13 + 71: Copy { + dest: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(2), // (0x55) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:91:19 + 72: IsNonZeroDestIsSmall { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + }, + 73: AndSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 74: Copy { + dest: StatePartIndex(8), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 75: SliceInt { + dest: StatePartIndex(9), // (0x29) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(8), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:79:32 + 76: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 77: BranchIfSmallNeImmediate { + target: 79, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 78: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 79: BranchIfSmallNeImmediate { + target: 81, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 80: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:101:5 + 81: Copy { + dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + src: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:156:5 + 82: BranchIfZero { + target: 87, + value: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:158:9 + 83: BranchIfZero { + target: 85, + value: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:159:13 + 84: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:158:9 + 85: BranchIfNonZero { + target: 87, + value: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:161:13 + 86: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:64:1 + 87: Copy { + dest: StatePartIndex(4), // (0x55) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(2), // (0x55) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 88: SliceInt { + dest: StatePartIndex(5), // (0x2a) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(4), // (0x55) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:77:32 + 89: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2), // (0x55) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 90: BranchIfSmallNeImmediate { + target: 92, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 91: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 92: BranchIfSmallNeImmediate { + target: 94, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 93: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + }, + // at: ready_valid.rs:98:5 + 94: Copy { + dest: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + src: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:116:5 + 95: Copy { + dest: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 96: IsNonZeroDestIsSmall { + dest: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 97: CmpNe { + dest: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + rhs: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:141:5 + 98: BranchIfZero { + target: 100, + value: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:142:9 + 99: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:146:5 + 100: BranchIfZero { + target: 105, + value: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:148:9 + 101: BranchIfZero { + target: 103, + value: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:149:13 + 102: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:148:9 + 103: BranchIfNonZero { + target: 105, + value: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:151:13 + 104: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:118:30 + 105: BranchIfSmallNeImmediate { + target: 107, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + 106: Copy { + dest: StatePartIndex(42), // (0x2a) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(5), // (0x2a) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:118:5 + 107: Copy { + dest: StatePartIndex(18), // (0x2a) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + src: StatePartIndex(42), // (0x2a) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + }, + // at: ready_valid.rs:84:31 + 108: BranchIfSmallZero { + target: 113, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 109: BranchIfSmallNonZero { + target: 112, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 110: Copy { + dest: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + src: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<1> }, + }, + 111: Branch { + target: 113, + }, + 112: Copy { + dest: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:86:25 + 113: BranchIfSmallZero { + target: 118, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 114: BranchIfSmallNonZero { + target: 117, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 115: Copy { + dest: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + src: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<1> }, + }, + 116: Branch { + target: 118, + }, + 117: Copy { + dest: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:88:26 + 118: BranchIfSmallZero { + target: 123, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 119: BranchIfSmallNonZero { + target: 122, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 120: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + }, + 121: Branch { + target: 123, + }, + 122: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 123: BranchIfSmallZero { + target: 124, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 124: BranchIfSmallZero { + target: 132, + value: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 125: CopySmall { + dest: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(11), // (0x1 1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 126: CopySmall { + dest: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 127: Copy { + dest: StatePartIndex(20), // (0x2a) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(18), // (0x2a) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + }, + 128: Copy { + dest: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + }, + 129: BranchIfSmallZero { + target: 132, + value: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 130: BranchIfZero { + target: 132, + value: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 131: MemoryWriteUInt { + value: StatePartIndex(20), // (0x2a) SlotDebugData { name: "", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 2>, + // data: [ + // // len = 0x2 + // [0x0]: 0x2a, + // [0x1]: 0x29, + // ], + // }) (), + addr: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + stride: 8, + start: 0, + width: 8, + }, + 132: XorSmallImmediate { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 133: XorSmallImmediate { + dest: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:84:31 + 134: XorSmallImmediate { + dest: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:64:1 + 135: Return, + ], + .. + }, + pc: 135, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array, 2>, + data: [ + // len = 0x2 + [0x0]: 0x2a, + [0x1]: 0x29, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 1, + 1, + 1, + 0, + 0, + 1, + 1, + 1, + 0, + 0, + 0, + 1, + 0, + 1, + 1, + 0, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 85, + 0, + 85, + 42, + 83, + 0, + 83, + 41, + 2, + 1, + 1, + 0, + 41, + 1, + 0, + 0, + 42, + 1, + 42, + 1, + 1, + 1, + 0, + 1, + 1, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 1, + 1, + 1, + 42, + 0, + 0, + 1, + 1, + 41, + 1, + 82, + 83, + 83, + 83, + 0, + 1, + 1, + 0, + 0, + 2, + 0, + 1, + 2, + 0, + 2, + 2, + 0, + 0, + 0, + 0, + 0, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.clk, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.rst, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.ready, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.ready, + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "queue", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "inp", + child: TraceBundle { + name: "inp", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(2), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(3), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(4), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceBundle { + name: "out", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(5), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(6), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(7), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + TraceModuleIO { + name: "count", + child: TraceUInt { + location: TraceScalarId(8), + name: "count", + ty: UInt<2>, + flow: Sink, + }, + ty: UInt<2>, + flow: Sink, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 2, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + /* offset = 3 */ + data: UInt<8>, + /* offset = 11 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + /* offset = 3 */ + data: UInt<8>, + /* offset = 11 */ + mask: Bool, + }, + }, + ], + array_type: Array, 2>, + }, + TraceReg { + name: "inp_index_reg", + child: TraceUInt { + location: TraceScalarId(18), + name: "inp_index_reg", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceReg { + name: "out_index_reg", + child: TraceUInt { + location: TraceScalarId(19), + name: "out_index_reg", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceReg { + name: "maybe_full_reg", + child: TraceBool { + location: TraceScalarId(20), + name: "maybe_full_reg", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "inp_firing", + child: TraceBool { + location: TraceScalarId(21), + name: "inp_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(22), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "out_firing", + child: TraceBool { + location: TraceScalarId(23), + name: "out_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(24), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "indexes_equal", + child: TraceBool { + location: TraceScalarId(25), + name: "indexes_equal", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "empty", + child: TraceBool { + location: TraceScalarId(26), + name: "empty", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "full", + child: TraceBool { + location: TraceScalarId(27), + name: "full", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "unwrap_or_else_out", + child: TraceUInt { + location: TraceScalarId(28), + name: "unwrap_or_else_out", + ty: UInt<8>, + flow: Duplex, + }, + ty: UInt<8>, + }, + TraceWire { + name: "count_lower", + child: TraceUInt { + location: TraceScalarId(29), + name: "count_lower", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSyncReset { + index: StatePartIndex(1), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<8>, + }, + state: 0x2a, + last_state: 0x2a, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigBool { + index: StatePartIndex(3), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(5), + kind: EnumDiscriminant { + index: StatePartIndex(1), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(9), + ty: UInt<8>, + }, + state: 0x29, + last_state: 0x29, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigBool { + index: StatePartIndex(7), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigUInt { + index: StatePartIndex(10), + ty: UInt<2>, + }, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigUInt { + index: StatePartIndex(11), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigBool { + index: StatePartIndex(12), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigClock { + index: StatePartIndex(13), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(12), + kind: BigUInt { + index: StatePartIndex(14), + ty: UInt<8>, + }, + state: 0x29, + last_state: 0x29, + }, + SimTrace { + id: TraceScalarId(13), + kind: BigUInt { + index: StatePartIndex(15), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigBool { + index: StatePartIndex(16), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(15), + kind: BigClock { + index: StatePartIndex(17), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(16), + kind: BigUInt { + index: StatePartIndex(18), + ty: UInt<8>, + }, + state: 0x2a, + last_state: 0x2a, + }, + SimTrace { + id: TraceScalarId(17), + kind: BigBool { + index: StatePartIndex(19), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigUInt { + index: StatePartIndex(22), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigUInt { + index: StatePartIndex(25), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(20), + kind: BigBool { + index: StatePartIndex(27), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(21), + kind: BigBool { + index: StatePartIndex(30), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(22), + kind: BigBool { + index: StatePartIndex(31), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(23), + kind: BigBool { + index: StatePartIndex(32), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(24), + kind: BigBool { + index: StatePartIndex(33), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(25), + kind: BigBool { + index: StatePartIndex(34), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(26), + kind: BigBool { + index: StatePartIndex(36), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(27), + kind: BigBool { + index: StatePartIndex(39), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(28), + kind: BigUInt { + index: StatePartIndex(42), + ty: UInt<8>, + }, + state: 0x2a, + last_state: 0x2a, + }, + SimTrace { + id: TraceScalarId(29), + kind: BigUInt { + index: StatePartIndex(66), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 2, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + /* offset = 3 */ + data: UInt<8>, + /* offset = 11 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + /* offset = 3 */ + data: UInt<8>, + /* offset = 11 */ + mask: Bool, + }, + }, + ], + array_type: Array, 2>, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [ + StatePartIndex(3), + StatePartIndex(8), + StatePartIndex(15), + ], + event_queue: EventQueue(EventQueueData { + instant: 100 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_2_true_true.vcd b/crates/fayalite/tests/sim/expected/queue_2_true_true.vcd new file mode 100644 index 0000000..f58f9ab --- /dev/null +++ b/crates/fayalite/tests/sim/expected/queue_2_true_true.vcd @@ -0,0 +1,2043 @@ +$timescale 1 ps $end +$scope module queue $end +$scope struct cd $end +$var wire 1 11z(a clk $end +$var wire 1 q1t|f rst $end +$upscope $end +$scope struct inp $end +$scope struct data $end +$var string 1 j|a-9 \$tag $end +$var wire 8 pjN&T HdlSome $end +$upscope $end +$var wire 1 *x8M* ready $end +$upscope $end +$scope struct out $end +$scope struct data $end +$var string 1 'Aa8} \$tag $end +$var wire 8 1b%.O HdlSome $end +$upscope $end +$var wire 1 vZD*c ready $end +$upscope $end +$var wire 2 rf7Xh count $end +$scope struct mem $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 8 (.Juw mem $end +$upscope $end +$scope struct \[1] $end +$var reg 8 5F$iE mem $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var wire 1 K]Dkr addr $end +$var wire 1 P|=HX en $end +$var wire 1 z+ft% clk $end +$var wire 8 m+9ec data $end +$upscope $end +$scope struct w1 $end +$var wire 1 8Oa@o addr $end +$var wire 1 VaM[2 en $end +$var wire 1 aH[{] clk $end +$var wire 8 8|1uZ data $end +$var wire 1 DYq.y mask $end +$upscope $end +$upscope $end +$var reg 1 Xk?#v inp_index_reg $end +$var reg 1 p19yW out_index_reg $end +$var reg 1 kEQiI maybe_full_reg $end +$var wire 1 *gdL1 inp_firing $end +$var wire 1 ;HWUJ firing $end +$var wire 1 Ph#@^ out_firing $end +$var wire 1 ;HWUJ" firing_2 $end +$var wire 1 i[~ { + len: 18, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 73, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::indexes_equal", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::empty", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::full", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<66>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 1, + debug_data: [ + (), + ], + layout_data: [ + MemoryData { + array_type: Array, 3>, + data: [ + // len = 0x3 + [0x0]: 0x00, + [0x1]: 0x00, + [0x2]: 0x00, + ], + }, + ], + .. + }, + }, + insns: [ + // at: ready_valid.rs:64:1 + 0: SubU { + dest: StatePartIndex(71), // (0x2) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + dest_width: 3, + }, + 1: CastToUInt { + dest: StatePartIndex(72), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(71), // (0x2) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 2: CmpLt { + dest: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + 3: Const { + dest: StatePartIndex(65), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x3, + }, + 4: CastToUInt { + dest: StatePartIndex(66), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(65), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + dest_width: 2, + }, + 5: Add { + dest: StatePartIndex(68), // (0x5) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(65), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + }, + 6: SubU { + dest: StatePartIndex(69), // (0x5) SlotDebugData { name: "", ty: UInt<66> }, + lhs: StatePartIndex(68), // (0x5) SlotDebugData { name: "", ty: UInt<65> }, + rhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + dest_width: 66, + }, + 7: CastToUInt { + dest: StatePartIndex(70), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(69), // (0x5) SlotDebugData { name: "", ty: UInt<66> }, + dest_width: 2, + }, + 8: Const { + dest: StatePartIndex(58), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + value: 0x0, + }, + 9: CastToUInt { + dest: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(58), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 2, + }, + 10: Const { + dest: StatePartIndex(56), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x2, + }, + 11: CmpEq { + dest: StatePartIndex(57), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(56), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + }, + 12: CmpEq { + dest: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(56), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + }, + 13: Const { + dest: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + value: 0x0, + }, + 14: Copy { + dest: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + }, + 15: Const { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 16: Add { + dest: StatePartIndex(60), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 17: CastToUInt { + dest: StatePartIndex(61), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(60), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 18: Add { + dest: StatePartIndex(63), // (0x1) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 19: CastToUInt { + dest: StatePartIndex(64), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(63), // (0x1) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 20: Const { + dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:118:30 + 21: Copy { + dest: StatePartIndex(42), // (0x28) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:117:5 + 22: Copy { + dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:115:5 + 23: Copy { + dest: StatePartIndex(15), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<2> }, + src: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:114:5 + 24: Copy { + dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:64:1 + 25: Const { + dest: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + value: 0x1, + }, + // at: ready_valid.rs:113:5 + 26: Copy { + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:119:5 + 27: Copy { + dest: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:112:5 + 28: Copy { + dest: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<2> }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 29: NotU { + dest: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + width: 1, + }, + 30: CmpEq { + dest: StatePartIndex(35), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:104:5 + 31: Copy { + dest: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + src: StatePartIndex(35), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 32: And { + dest: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:107:5 + 33: Copy { + dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + src: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 34: NotU { + dest: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + width: 1, + }, + 35: And { + dest: StatePartIndex(40), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:110:5 + 36: Copy { + dest: StatePartIndex(39), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + src: StatePartIndex(40), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 37: NotU { + dest: StatePartIndex(44), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(39), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + width: 1, + }, + // at: ready_valid.rs:121:5 + 38: Copy { + dest: StatePartIndex(3), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(44), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:166:5 + 39: BranchIfZero { + target: 44, + value: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 40: BranchIfZero { + target: 42, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:169:13 + 41: Copy { + dest: StatePartIndex(10), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(66), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:168:9 + 42: BranchIfNonZero { + target: 44, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:171:13 + 43: Copy { + dest: StatePartIndex(10), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:166:5 + 44: BranchIfNonZero { + target: 49, + value: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:186:13 + 45: BranchIfZero { + target: 47, + value: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:187:17 + 46: Copy { + dest: StatePartIndex(10), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(70), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:186:13 + 47: BranchIfNonZero { + target: 49, + value: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:189:17 + 48: Copy { + dest: StatePartIndex(10), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(72), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:88:26 + 49: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 50: Const { + dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, + }, + // at: ready_valid.rs:86:25 + 51: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:84:31 + 52: IsNonZeroDestIsSmall { + dest: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.rst", ty: SyncReset }, + }, + 53: IsNonZeroDestIsSmall { + dest: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + 54: AndSmall { + dest: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 55: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 56: Const { + dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + value: 0x0, + }, + // at: ready_valid.rs:91:19 + 57: CastBigToArrayIndex { + dest: StatePartIndex(11), // (0x2 2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(15), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<2> }, + }, + 58: IsNonZeroDestIsSmall { + dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + }, + 59: AndSmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 60: CastBigToArrayIndex { + dest: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<2> }, + }, + 61: IsNonZeroDestIsSmall { + dest: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + }, + 62: BranchIfSmallZero { + target: 65, + value: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 63: MemoryReadUInt { + dest: StatePartIndex(14), // (0x27) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 3>, + // data: [ + // // len = 0x3 + // [0x0]: 0x27, + // [0x1]: 0x28, + // [0x2]: 0x26, + // ], + // }) (), + addr: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<2> }, + stride: 8, + start: 0, + width: 8, + }, + 64: Branch { + target: 66, + }, + 65: Const { + dest: StatePartIndex(14), // (0x27) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:64:1 + 66: Copy { + dest: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 67: Copy { + dest: StatePartIndex(47), // (0x27) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(14), // (0x27) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + }, + 68: Shl { + dest: StatePartIndex(49), // (0x4e) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(47), // (0x27) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 1, + }, + 69: Or { + dest: StatePartIndex(50), // (0x4f) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(49), // (0x4e) SlotDebugData { name: "", ty: UInt<9> }, + }, + 70: CastToUInt { + dest: StatePartIndex(51), // (0x4f) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(50), // (0x4f) SlotDebugData { name: "", ty: UInt<9> }, + dest_width: 9, + }, + 71: Copy { + dest: StatePartIndex(52), // (0x4f) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(51), // (0x4f) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: ready_valid.rs:130:5 + 72: BranchIfZero { + target: 74, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:131:9 + 73: Copy { + dest: StatePartIndex(6), // (0x4f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(52), // (0x4f) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:130:5 + 74: BranchIfNonZero { + target: 76, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:136:13 + 75: Copy { + dest: StatePartIndex(6), // (0x4f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:91:19 + 76: IsNonZeroDestIsSmall { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + }, + 77: AndSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 78: Copy { + dest: StatePartIndex(8), // (0x4f) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(6), // (0x4f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 79: SliceInt { + dest: StatePartIndex(9), // (0x27) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(8), // (0x4f) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:79:32 + 80: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(6), // (0x4f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 81: BranchIfSmallNeImmediate { + target: 83, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 82: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 83: BranchIfSmallNeImmediate { + target: 85, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 84: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:101:5 + 85: Copy { + dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + src: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:156:5 + 86: BranchIfZero { + target: 91, + value: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:158:9 + 87: BranchIfZero { + target: 89, + value: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:159:13 + 88: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:158:9 + 89: BranchIfNonZero { + target: 91, + value: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:161:13 + 90: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(64), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 91: Copy { + dest: StatePartIndex(4), // (0x51) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(2), // (0x51) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 92: SliceInt { + dest: StatePartIndex(5), // (0x28) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(4), // (0x51) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:77:32 + 93: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2), // (0x51) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 94: BranchIfSmallNeImmediate { + target: 96, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 95: Copy { + dest: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 96: BranchIfSmallNeImmediate { + target: 98, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 97: Copy { + dest: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(3), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + }, + // at: ready_valid.rs:98:5 + 98: Copy { + dest: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + src: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:116:5 + 99: Copy { + dest: StatePartIndex(16), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + src: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 100: IsNonZeroDestIsSmall { + dest: StatePartIndex(10), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(16), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 101: CmpNe { + dest: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + rhs: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:141:5 + 102: BranchIfZero { + target: 104, + value: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:142:9 + 103: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:146:5 + 104: BranchIfZero { + target: 109, + value: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:148:9 + 105: BranchIfZero { + target: 107, + value: StatePartIndex(57), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:149:13 + 106: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:148:9 + 107: BranchIfNonZero { + target: 109, + value: StatePartIndex(57), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:151:13 + 108: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(61), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:118:30 + 109: BranchIfSmallNeImmediate { + target: 111, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + 110: Copy { + dest: StatePartIndex(42), // (0x28) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(5), // (0x28) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:118:5 + 111: Copy { + dest: StatePartIndex(18), // (0x28) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + src: StatePartIndex(42), // (0x28) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + }, + // at: ready_valid.rs:84:31 + 112: BranchIfSmallZero { + target: 117, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 113: BranchIfSmallNonZero { + target: 116, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 114: Copy { + dest: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + src: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + }, + 115: Branch { + target: 117, + }, + 116: Copy { + dest: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:86:25 + 117: BranchIfSmallZero { + target: 122, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 118: BranchIfSmallNonZero { + target: 121, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 119: Copy { + dest: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + src: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + }, + 120: Branch { + target: 122, + }, + 121: Copy { + dest: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:88:26 + 122: BranchIfSmallZero { + target: 127, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 123: BranchIfSmallNonZero { + target: 126, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 124: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + }, + 125: Branch { + target: 127, + }, + 126: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 127: BranchIfSmallZero { + target: 128, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 128: BranchIfSmallZero { + target: 136, + value: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 129: CopySmall { + dest: StatePartIndex(12), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(11), // (0x2 2) SlotDebugData { name: "", ty: UInt<2> }, + }, + 130: CopySmall { + dest: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(10), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 131: Copy { + dest: StatePartIndex(20), // (0x28) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(18), // (0x28) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + }, + 132: Copy { + dest: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + }, + 133: BranchIfSmallZero { + target: 136, + value: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 134: BranchIfZero { + target: 136, + value: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 135: MemoryWriteUInt { + value: StatePartIndex(20), // (0x28) SlotDebugData { name: "", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 3>, + // data: [ + // // len = 0x3 + // [0x0]: 0x27, + // [0x1]: 0x28, + // [0x2]: 0x26, + // ], + // }) (), + addr: StatePartIndex(12), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + stride: 8, + start: 0, + width: 8, + }, + 136: XorSmallImmediate { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 137: XorSmallImmediate { + dest: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:84:31 + 138: XorSmallImmediate { + dest: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:64:1 + 139: Return, + ], + .. + }, + pc: 139, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array, 3>, + data: [ + // len = 0x3 + [0x0]: 0x27, + [0x1]: 0x28, + [0x2]: 0x26, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 1, + 1, + 1, + 0, + 0, + 1, + 0, + 1, + 0, + 0, + 1, + 2, + 1, + 1, + 1, + 0, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 81, + 1, + 81, + 40, + 79, + 0, + 79, + 39, + 2, + 0, + 1, + 0, + 39, + 2, + 1, + 0, + 40, + 1, + 40, + 1, + 2, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 40, + 0, + 1, + 1, + 1, + 39, + 1, + 78, + 79, + 79, + 79, + 0, + 0, + 1, + 2, + 1, + 0, + 0, + 3, + 3, + 0, + 1, + 1, + 3, + 3, + 0, + 5, + 5, + 1, + 2, + 2, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.clk, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.rst, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.ready, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.ready, + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "queue", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "inp", + child: TraceBundle { + name: "inp", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(2), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(3), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(4), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceBundle { + name: "out", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(5), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(6), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(7), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + TraceModuleIO { + name: "count", + child: TraceUInt { + location: TraceScalarId(8), + name: "count", + ty: UInt<2>, + flow: Sink, + }, + ty: UInt<2>, + flow: Sink, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 3, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + }, + ], + array_type: Array, 3>, + }, + TraceReg { + name: "inp_index_reg", + child: TraceUInt { + location: TraceScalarId(18), + name: "inp_index_reg", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + TraceReg { + name: "out_index_reg", + child: TraceUInt { + location: TraceScalarId(19), + name: "out_index_reg", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + TraceReg { + name: "maybe_full_reg", + child: TraceBool { + location: TraceScalarId(20), + name: "maybe_full_reg", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "inp_firing", + child: TraceBool { + location: TraceScalarId(21), + name: "inp_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(22), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "out_firing", + child: TraceBool { + location: TraceScalarId(23), + name: "out_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(24), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "indexes_equal", + child: TraceBool { + location: TraceScalarId(25), + name: "indexes_equal", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "empty", + child: TraceBool { + location: TraceScalarId(26), + name: "empty", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "full", + child: TraceBool { + location: TraceScalarId(27), + name: "full", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "unwrap_or_else_out", + child: TraceUInt { + location: TraceScalarId(28), + name: "unwrap_or_else_out", + ty: UInt<8>, + flow: Duplex, + }, + ty: UInt<8>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSyncReset { + index: StatePartIndex(1), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<8>, + }, + state: 0x28, + last_state: 0x28, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigBool { + index: StatePartIndex(3), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(5), + kind: EnumDiscriminant { + index: StatePartIndex(1), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(9), + ty: UInt<8>, + }, + state: 0x27, + last_state: 0x27, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigBool { + index: StatePartIndex(7), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigUInt { + index: StatePartIndex(10), + ty: UInt<2>, + }, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigUInt { + index: StatePartIndex(11), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigBool { + index: StatePartIndex(12), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigClock { + index: StatePartIndex(13), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(12), + kind: BigUInt { + index: StatePartIndex(14), + ty: UInt<8>, + }, + state: 0x27, + last_state: 0x27, + }, + SimTrace { + id: TraceScalarId(13), + kind: BigUInt { + index: StatePartIndex(15), + ty: UInt<2>, + }, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigBool { + index: StatePartIndex(16), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(15), + kind: BigClock { + index: StatePartIndex(17), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(16), + kind: BigUInt { + index: StatePartIndex(18), + ty: UInt<8>, + }, + state: 0x28, + last_state: 0x28, + }, + SimTrace { + id: TraceScalarId(17), + kind: BigBool { + index: StatePartIndex(19), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigUInt { + index: StatePartIndex(22), + ty: UInt<2>, + }, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigUInt { + index: StatePartIndex(25), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(20), + kind: BigBool { + index: StatePartIndex(27), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(21), + kind: BigBool { + index: StatePartIndex(30), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(22), + kind: BigBool { + index: StatePartIndex(31), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(23), + kind: BigBool { + index: StatePartIndex(32), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(24), + kind: BigBool { + index: StatePartIndex(33), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(25), + kind: BigBool { + index: StatePartIndex(34), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(26), + kind: BigBool { + index: StatePartIndex(36), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(27), + kind: BigBool { + index: StatePartIndex(39), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(28), + kind: BigUInt { + index: StatePartIndex(42), + ty: UInt<8>, + }, + state: 0x28, + last_state: 0x28, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 3, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + }, + ], + array_type: Array, 3>, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [ + StatePartIndex(3), + StatePartIndex(8), + StatePartIndex(15), + ], + event_queue: EventQueue(EventQueueData { + instant: 100 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_3_false_false.vcd b/crates/fayalite/tests/sim/expected/queue_3_false_false.vcd new file mode 100644 index 0000000..4481901 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/queue_3_false_false.vcd @@ -0,0 +1,1990 @@ +$timescale 1 ps $end +$scope module queue $end +$scope struct cd $end +$var wire 1 11z(a clk $end +$var wire 1 q1t|f rst $end +$upscope $end +$scope struct inp $end +$scope struct data $end +$var string 1 j|a-9 \$tag $end +$var wire 8 pjN&T HdlSome $end +$upscope $end +$var wire 1 *x8M* ready $end +$upscope $end +$scope struct out $end +$scope struct data $end +$var string 1 'Aa8} \$tag $end +$var wire 8 1b%.O HdlSome $end +$upscope $end +$var wire 1 vZD*c ready $end +$upscope $end +$var wire 2 rf7Xh count $end +$scope struct mem $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 8 (.Juw mem $end +$upscope $end +$scope struct \[1] $end +$var reg 8 5F$iE mem $end +$upscope $end +$scope struct \[2] $end +$var reg 8 !BEt5 mem $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var wire 2 K]Dkr addr $end +$var wire 1 P|=HX en $end +$var wire 1 z+ft% clk $end +$var wire 8 m+9ec data $end +$upscope $end +$scope struct w1 $end +$var wire 2 8Oa@o addr $end +$var wire 1 VaM[2 en $end +$var wire 1 aH[{] clk $end +$var wire 8 8|1uZ data $end +$var wire 1 DYq.y mask $end +$upscope $end +$upscope $end +$var reg 2 Xk?#v inp_index_reg $end +$var reg 2 p19yW out_index_reg $end +$var reg 1 kEQiI maybe_full_reg $end +$var wire 1 *gdL1 inp_firing $end +$var wire 1 ;HWUJ firing $end +$var wire 1 Ph#@^ out_firing $end +$var wire 1 ;HWUJ" firing_2 $end +$var wire 1 i[~ { + len: 18, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 71, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::indexes_equal", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::empty", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::full", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<66>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 1, + debug_data: [ + (), + ], + layout_data: [ + MemoryData { + array_type: Array, 3>, + data: [ + // len = 0x3 + [0x0]: 0x00, + [0x1]: 0x00, + [0x2]: 0x00, + ], + }, + ], + .. + }, + }, + insns: [ + // at: ready_valid.rs:64:1 + 0: SubU { + dest: StatePartIndex(69), // (0x7) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + dest_width: 3, + }, + 1: CastToUInt { + dest: StatePartIndex(70), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(69), // (0x7) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 2: CmpLt { + dest: StatePartIndex(65), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + 3: Const { + dest: StatePartIndex(63), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x3, + }, + 4: CastToUInt { + dest: StatePartIndex(64), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(63), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + dest_width: 2, + }, + 5: Add { + dest: StatePartIndex(66), // (0x4) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(63), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + }, + 6: SubU { + dest: StatePartIndex(67), // (0x2) SlotDebugData { name: "", ty: UInt<66> }, + lhs: StatePartIndex(66), // (0x4) SlotDebugData { name: "", ty: UInt<65> }, + rhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + dest_width: 66, + }, + 7: CastToUInt { + dest: StatePartIndex(68), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(67), // (0x2) SlotDebugData { name: "", ty: UInt<66> }, + dest_width: 2, + }, + 8: Const { + dest: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + value: 0x0, + }, + 9: CastToUInt { + dest: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 2, + }, + 10: Const { + dest: StatePartIndex(54), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x2, + }, + 11: CmpEq { + dest: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(54), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + }, + 12: CmpEq { + dest: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(54), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + }, + 13: Const { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 14: Add { + dest: StatePartIndex(58), // (0x2) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 15: CastToUInt { + dest: StatePartIndex(59), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(58), // (0x2) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 16: Add { + dest: StatePartIndex(61), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 17: CastToUInt { + dest: StatePartIndex(62), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(61), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 18: Const { + dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:118:30 + 19: Copy { + dest: StatePartIndex(42), // (0x2a) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:117:5 + 20: Copy { + dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:115:5 + 21: Copy { + dest: StatePartIndex(15), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<2> }, + src: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:114:5 + 22: Copy { + dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:64:1 + 23: Const { + dest: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + value: 0x1, + }, + // at: ready_valid.rs:113:5 + 24: Copy { + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:119:5 + 25: Copy { + dest: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:112:5 + 26: Copy { + dest: StatePartIndex(11), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<2> }, + src: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 27: NotU { + dest: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + width: 1, + }, + 28: CmpEq { + dest: StatePartIndex(35), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:104:5 + 29: Copy { + dest: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + src: StatePartIndex(35), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 30: And { + dest: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:107:5 + 31: Copy { + dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + src: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 32: NotU { + dest: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + width: 1, + }, + 33: And { + dest: StatePartIndex(40), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:110:5 + 34: Copy { + dest: StatePartIndex(39), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + src: StatePartIndex(40), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 35: NotU { + dest: StatePartIndex(44), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(39), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + width: 1, + }, + // at: ready_valid.rs:121:5 + 36: Copy { + dest: StatePartIndex(3), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(44), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:166:5 + 37: BranchIfZero { + target: 42, + value: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 38: BranchIfZero { + target: 40, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:169:13 + 39: Copy { + dest: StatePartIndex(10), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(64), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:168:9 + 40: BranchIfNonZero { + target: 42, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:171:13 + 41: Copy { + dest: StatePartIndex(10), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:166:5 + 42: BranchIfNonZero { + target: 47, + value: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:186:13 + 43: BranchIfZero { + target: 45, + value: StatePartIndex(65), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:187:17 + 44: Copy { + dest: StatePartIndex(10), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(68), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:186:13 + 45: BranchIfNonZero { + target: 47, + value: StatePartIndex(65), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:189:17 + 46: Copy { + dest: StatePartIndex(10), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(70), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:88:26 + 47: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 48: Const { + dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, + }, + // at: ready_valid.rs:86:25 + 49: Copy { + dest: StatePartIndex(26), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:84:31 + 50: IsNonZeroDestIsSmall { + dest: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.rst", ty: SyncReset }, + }, + 51: IsNonZeroDestIsSmall { + dest: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + 52: AndSmall { + dest: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 53: Copy { + dest: StatePartIndex(23), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 54: Const { + dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + value: 0x0, + }, + // at: ready_valid.rs:91:19 + 55: CastBigToArrayIndex { + dest: StatePartIndex(11), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(15), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<2> }, + }, + 56: IsNonZeroDestIsSmall { + dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + }, + 57: AndSmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 58: CastBigToArrayIndex { + dest: StatePartIndex(6), // (0x2 2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(11), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<2> }, + }, + 59: IsNonZeroDestIsSmall { + dest: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + }, + 60: BranchIfSmallZero { + target: 63, + value: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 61: MemoryReadUInt { + dest: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 3>, + // data: [ + // // len = 0x3 + // [0x0]: 0x2a, + // [0x1]: 0x28, + // [0x2]: 0x29, + // ], + // }) (), + addr: StatePartIndex(6), // (0x2 2) SlotDebugData { name: "", ty: UInt<2> }, + stride: 8, + start: 0, + width: 8, + }, + 62: Branch { + target: 64, + }, + 63: Const { + dest: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:64:1 + 64: Copy { + dest: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 65: Copy { + dest: StatePartIndex(47), // (0x29) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + }, + 66: Shl { + dest: StatePartIndex(49), // (0x52) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(47), // (0x29) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 1, + }, + 67: Or { + dest: StatePartIndex(50), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(49), // (0x52) SlotDebugData { name: "", ty: UInt<9> }, + }, + 68: CastToUInt { + dest: StatePartIndex(51), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(50), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + dest_width: 9, + }, + 69: Copy { + dest: StatePartIndex(52), // (0x53) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(51), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: ready_valid.rs:130:5 + 70: BranchIfZero { + target: 72, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:131:9 + 71: Copy { + dest: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(52), // (0x53) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:130:5 + 72: BranchIfNonZero { + target: 74, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:134:13 + 73: Copy { + dest: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(2), // (0x55) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:91:19 + 74: IsNonZeroDestIsSmall { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + }, + 75: AndSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 76: Copy { + dest: StatePartIndex(8), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 77: SliceInt { + dest: StatePartIndex(9), // (0x29) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(8), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:79:32 + 78: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 79: BranchIfSmallNeImmediate { + target: 81, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 80: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 81: BranchIfSmallNeImmediate { + target: 83, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 82: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:101:5 + 83: Copy { + dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + src: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:156:5 + 84: BranchIfZero { + target: 89, + value: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:158:9 + 85: BranchIfZero { + target: 87, + value: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:159:13 + 86: Copy { + dest: StatePartIndex(26), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:158:9 + 87: BranchIfNonZero { + target: 89, + value: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:161:13 + 88: Copy { + dest: StatePartIndex(26), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(62), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 89: Copy { + dest: StatePartIndex(4), // (0x55) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(2), // (0x55) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 90: SliceInt { + dest: StatePartIndex(5), // (0x2a) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(4), // (0x55) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:77:32 + 91: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2), // (0x55) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 92: BranchIfSmallNeImmediate { + target: 94, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 93: Copy { + dest: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 94: BranchIfSmallNeImmediate { + target: 96, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 95: Copy { + dest: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(3), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + }, + // at: ready_valid.rs:98:5 + 96: Copy { + dest: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + src: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:116:5 + 97: Copy { + dest: StatePartIndex(16), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + src: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 98: IsNonZeroDestIsSmall { + dest: StatePartIndex(10), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(16), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 99: CmpNe { + dest: StatePartIndex(53), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + rhs: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:141:5 + 100: BranchIfZero { + target: 102, + value: StatePartIndex(53), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:142:9 + 101: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:146:5 + 102: BranchIfZero { + target: 107, + value: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:148:9 + 103: BranchIfZero { + target: 105, + value: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:149:13 + 104: Copy { + dest: StatePartIndex(23), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:148:9 + 105: BranchIfNonZero { + target: 107, + value: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:151:13 + 106: Copy { + dest: StatePartIndex(23), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(59), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:118:30 + 107: BranchIfSmallNeImmediate { + target: 109, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + 108: Copy { + dest: StatePartIndex(42), // (0x2a) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(5), // (0x2a) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:118:5 + 109: Copy { + dest: StatePartIndex(18), // (0x2a) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + src: StatePartIndex(42), // (0x2a) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + }, + // at: ready_valid.rs:84:31 + 110: BranchIfSmallZero { + target: 115, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 111: BranchIfSmallNonZero { + target: 114, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 112: Copy { + dest: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + src: StatePartIndex(23), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + }, + 113: Branch { + target: 115, + }, + 114: Copy { + dest: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:86:25 + 115: BranchIfSmallZero { + target: 120, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 116: BranchIfSmallNonZero { + target: 119, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 117: Copy { + dest: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + src: StatePartIndex(26), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + }, + 118: Branch { + target: 120, + }, + 119: Copy { + dest: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:88:26 + 120: BranchIfSmallZero { + target: 125, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 121: BranchIfSmallNonZero { + target: 124, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 122: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + }, + 123: Branch { + target: 125, + }, + 124: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 125: BranchIfSmallZero { + target: 126, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 126: BranchIfSmallZero { + target: 134, + value: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 127: CopySmall { + dest: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(11), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + }, + 128: CopySmall { + dest: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(10), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 129: Copy { + dest: StatePartIndex(20), // (0x2a) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(18), // (0x2a) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + }, + 130: Copy { + dest: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + }, + 131: BranchIfSmallZero { + target: 134, + value: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 132: BranchIfZero { + target: 134, + value: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 133: MemoryWriteUInt { + value: StatePartIndex(20), // (0x2a) SlotDebugData { name: "", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 3>, + // data: [ + // // len = 0x3 + // [0x0]: 0x2a, + // [0x1]: 0x28, + // [0x2]: 0x29, + // ], + // }) (), + addr: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<2> }, + stride: 8, + start: 0, + width: 8, + }, + 134: XorSmallImmediate { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 135: XorSmallImmediate { + dest: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:84:31 + 136: XorSmallImmediate { + dest: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:64:1 + 137: Return, + ], + .. + }, + pc: 137, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array, 3>, + data: [ + // len = 0x3 + [0x0]: 0x2a, + [0x1]: 0x28, + [0x2]: 0x29, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 1, + 1, + 1, + 0, + 0, + 1, + 2, + 1, + 0, + 0, + 1, + 1, + 0, + 1, + 1, + 0, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 85, + 1, + 85, + 42, + 83, + 0, + 83, + 41, + 2, + 2, + 1, + 0, + 41, + 1, + 1, + 0, + 42, + 1, + 42, + 1, + 1, + 2, + 0, + 2, + 2, + 1, + 1, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 42, + 0, + 1, + 1, + 1, + 41, + 1, + 82, + 83, + 83, + 83, + 1, + 2, + 0, + 0, + 0, + 2, + 2, + 1, + 3, + 3, + 3, + 3, + 1, + 4, + 2, + 2, + 7, + 3, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.clk, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.rst, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.ready, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.ready, + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "queue", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "inp", + child: TraceBundle { + name: "inp", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(2), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(3), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(4), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceBundle { + name: "out", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(5), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(6), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(7), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + TraceModuleIO { + name: "count", + child: TraceUInt { + location: TraceScalarId(8), + name: "count", + ty: UInt<2>, + flow: Sink, + }, + ty: UInt<2>, + flow: Sink, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 3, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + }, + ], + array_type: Array, 3>, + }, + TraceReg { + name: "inp_index_reg", + child: TraceUInt { + location: TraceScalarId(18), + name: "inp_index_reg", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + TraceReg { + name: "out_index_reg", + child: TraceUInt { + location: TraceScalarId(19), + name: "out_index_reg", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + TraceReg { + name: "maybe_full_reg", + child: TraceBool { + location: TraceScalarId(20), + name: "maybe_full_reg", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "inp_firing", + child: TraceBool { + location: TraceScalarId(21), + name: "inp_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(22), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "out_firing", + child: TraceBool { + location: TraceScalarId(23), + name: "out_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(24), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "indexes_equal", + child: TraceBool { + location: TraceScalarId(25), + name: "indexes_equal", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "empty", + child: TraceBool { + location: TraceScalarId(26), + name: "empty", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "full", + child: TraceBool { + location: TraceScalarId(27), + name: "full", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "unwrap_or_else_out", + child: TraceUInt { + location: TraceScalarId(28), + name: "unwrap_or_else_out", + ty: UInt<8>, + flow: Duplex, + }, + ty: UInt<8>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSyncReset { + index: StatePartIndex(1), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<8>, + }, + state: 0x2a, + last_state: 0x2a, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigBool { + index: StatePartIndex(3), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(5), + kind: EnumDiscriminant { + index: StatePartIndex(1), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(9), + ty: UInt<8>, + }, + state: 0x29, + last_state: 0x29, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigBool { + index: StatePartIndex(7), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigUInt { + index: StatePartIndex(10), + ty: UInt<2>, + }, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigUInt { + index: StatePartIndex(11), + ty: UInt<2>, + }, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigBool { + index: StatePartIndex(12), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigClock { + index: StatePartIndex(13), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(12), + kind: BigUInt { + index: StatePartIndex(14), + ty: UInt<8>, + }, + state: 0x29, + last_state: 0x29, + }, + SimTrace { + id: TraceScalarId(13), + kind: BigUInt { + index: StatePartIndex(15), + ty: UInt<2>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigBool { + index: StatePartIndex(16), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(15), + kind: BigClock { + index: StatePartIndex(17), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(16), + kind: BigUInt { + index: StatePartIndex(18), + ty: UInt<8>, + }, + state: 0x2a, + last_state: 0x2a, + }, + SimTrace { + id: TraceScalarId(17), + kind: BigBool { + index: StatePartIndex(19), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigUInt { + index: StatePartIndex(22), + ty: UInt<2>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigUInt { + index: StatePartIndex(25), + ty: UInt<2>, + }, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(20), + kind: BigBool { + index: StatePartIndex(27), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(21), + kind: BigBool { + index: StatePartIndex(30), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(22), + kind: BigBool { + index: StatePartIndex(31), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(23), + kind: BigBool { + index: StatePartIndex(32), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(24), + kind: BigBool { + index: StatePartIndex(33), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(25), + kind: BigBool { + index: StatePartIndex(34), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(26), + kind: BigBool { + index: StatePartIndex(36), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(27), + kind: BigBool { + index: StatePartIndex(39), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(28), + kind: BigUInt { + index: StatePartIndex(42), + ty: UInt<8>, + }, + state: 0x2a, + last_state: 0x2a, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 3, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + }, + ], + array_type: Array, 3>, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [ + StatePartIndex(3), + StatePartIndex(8), + StatePartIndex(15), + ], + event_queue: EventQueue(EventQueueData { + instant: 100 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_3_false_true.vcd b/crates/fayalite/tests/sim/expected/queue_3_false_true.vcd new file mode 100644 index 0000000..622613c --- /dev/null +++ b/crates/fayalite/tests/sim/expected/queue_3_false_true.vcd @@ -0,0 +1,2002 @@ +$timescale 1 ps $end +$scope module queue $end +$scope struct cd $end +$var wire 1 11z(a clk $end +$var wire 1 q1t|f rst $end +$upscope $end +$scope struct inp $end +$scope struct data $end +$var string 1 j|a-9 \$tag $end +$var wire 8 pjN&T HdlSome $end +$upscope $end +$var wire 1 *x8M* ready $end +$upscope $end +$scope struct out $end +$scope struct data $end +$var string 1 'Aa8} \$tag $end +$var wire 8 1b%.O HdlSome $end +$upscope $end +$var wire 1 vZD*c ready $end +$upscope $end +$var wire 2 rf7Xh count $end +$scope struct mem $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 8 (.Juw mem $end +$upscope $end +$scope struct \[1] $end +$var reg 8 5F$iE mem $end +$upscope $end +$scope struct \[2] $end +$var reg 8 !BEt5 mem $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var wire 2 K]Dkr addr $end +$var wire 1 P|=HX en $end +$var wire 1 z+ft% clk $end +$var wire 8 m+9ec data $end +$upscope $end +$scope struct w1 $end +$var wire 2 8Oa@o addr $end +$var wire 1 VaM[2 en $end +$var wire 1 aH[{] clk $end +$var wire 8 8|1uZ data $end +$var wire 1 DYq.y mask $end +$upscope $end +$upscope $end +$var reg 2 Xk?#v inp_index_reg $end +$var reg 2 p19yW out_index_reg $end +$var reg 1 kEQiI maybe_full_reg $end +$var wire 1 *gdL1 inp_firing $end +$var wire 1 ;HWUJ firing $end +$var wire 1 Ph#@^ out_firing $end +$var wire 1 ;HWUJ" firing_2 $end +$var wire 1 i[~ { + len: 18, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 73, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::indexes_equal", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::empty", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::full", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<66>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 1, + debug_data: [ + (), + ], + layout_data: [ + MemoryData { + array_type: Array, 3>, + data: [ + // len = 0x3 + [0x0]: 0x00, + [0x1]: 0x00, + [0x2]: 0x00, + ], + }, + ], + .. + }, + }, + insns: [ + // at: ready_valid.rs:64:1 + 0: SubU { + dest: StatePartIndex(71), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + dest_width: 3, + }, + 1: CastToUInt { + dest: StatePartIndex(72), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(71), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 2: CmpLt { + dest: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + 3: Const { + dest: StatePartIndex(65), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x3, + }, + 4: CastToUInt { + dest: StatePartIndex(66), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(65), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + dest_width: 2, + }, + 5: Add { + dest: StatePartIndex(68), // (0x5) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(65), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + }, + 6: SubU { + dest: StatePartIndex(69), // (0x3) SlotDebugData { name: "", ty: UInt<66> }, + lhs: StatePartIndex(68), // (0x5) SlotDebugData { name: "", ty: UInt<65> }, + rhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + dest_width: 66, + }, + 7: CastToUInt { + dest: StatePartIndex(70), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(69), // (0x3) SlotDebugData { name: "", ty: UInt<66> }, + dest_width: 2, + }, + 8: Const { + dest: StatePartIndex(58), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + value: 0x0, + }, + 9: CastToUInt { + dest: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(58), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 2, + }, + 10: Const { + dest: StatePartIndex(56), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x2, + }, + 11: CmpEq { + dest: StatePartIndex(57), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(56), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + }, + 12: CmpEq { + dest: StatePartIndex(62), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(56), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + }, + 13: Const { + dest: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + value: 0x0, + }, + 14: Copy { + dest: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + }, + 15: Const { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 16: Add { + dest: StatePartIndex(60), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 17: CastToUInt { + dest: StatePartIndex(61), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(60), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 18: Add { + dest: StatePartIndex(63), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 19: CastToUInt { + dest: StatePartIndex(64), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(63), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 20: Const { + dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:118:30 + 21: Copy { + dest: StatePartIndex(42), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:117:5 + 22: Copy { + dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:115:5 + 23: Copy { + dest: StatePartIndex(15), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<2> }, + src: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:114:5 + 24: Copy { + dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:64:1 + 25: Const { + dest: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + value: 0x1, + }, + // at: ready_valid.rs:113:5 + 26: Copy { + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:119:5 + 27: Copy { + dest: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:112:5 + 28: Copy { + dest: StatePartIndex(11), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<2> }, + src: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 29: NotU { + dest: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + width: 1, + }, + 30: CmpEq { + dest: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:104:5 + 31: Copy { + dest: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + src: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 32: And { + dest: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:107:5 + 33: Copy { + dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + src: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 34: NotU { + dest: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + width: 1, + }, + 35: And { + dest: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:110:5 + 36: Copy { + dest: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + src: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 37: NotU { + dest: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + width: 1, + }, + // at: ready_valid.rs:121:5 + 38: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:124:9 + 39: BranchIfZero { + target: 41, + value: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:125:13 + 40: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:166:5 + 41: BranchIfZero { + target: 46, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 42: BranchIfZero { + target: 44, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:169:13 + 43: Copy { + dest: StatePartIndex(10), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(66), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:168:9 + 44: BranchIfNonZero { + target: 46, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:171:13 + 45: Copy { + dest: StatePartIndex(10), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:166:5 + 46: BranchIfNonZero { + target: 51, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:186:13 + 47: BranchIfZero { + target: 49, + value: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:187:17 + 48: Copy { + dest: StatePartIndex(10), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(70), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:186:13 + 49: BranchIfNonZero { + target: 51, + value: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:189:17 + 50: Copy { + dest: StatePartIndex(10), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(72), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:88:26 + 51: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 52: Const { + dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, + }, + // at: ready_valid.rs:86:25 + 53: Copy { + dest: StatePartIndex(26), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:84:31 + 54: IsNonZeroDestIsSmall { + dest: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.rst", ty: SyncReset }, + }, + 55: IsNonZeroDestIsSmall { + dest: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + 56: AndSmall { + dest: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 57: Copy { + dest: StatePartIndex(23), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 58: Const { + dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + value: 0x0, + }, + // at: ready_valid.rs:91:19 + 59: CastBigToArrayIndex { + dest: StatePartIndex(11), // (0x2 2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(15), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<2> }, + }, + 60: IsNonZeroDestIsSmall { + dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + }, + 61: AndSmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 62: CastBigToArrayIndex { + dest: StatePartIndex(6), // (0x2 2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(11), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<2> }, + }, + 63: IsNonZeroDestIsSmall { + dest: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + }, + 64: BranchIfSmallZero { + target: 67, + value: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 65: MemoryReadUInt { + dest: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 3>, + // data: [ + // // len = 0x3 + // [0x0]: 0x2a, + // [0x1]: 0x2b, + // [0x2]: 0x29, + // ], + // }) (), + addr: StatePartIndex(6), // (0x2 2) SlotDebugData { name: "", ty: UInt<2> }, + stride: 8, + start: 0, + width: 8, + }, + 66: Branch { + target: 68, + }, + 67: Const { + dest: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:64:1 + 68: Copy { + dest: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 69: Copy { + dest: StatePartIndex(47), // (0x29) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + }, + 70: Shl { + dest: StatePartIndex(49), // (0x52) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(47), // (0x29) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 1, + }, + 71: Or { + dest: StatePartIndex(50), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(49), // (0x52) SlotDebugData { name: "", ty: UInt<9> }, + }, + 72: CastToUInt { + dest: StatePartIndex(51), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(50), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + dest_width: 9, + }, + 73: Copy { + dest: StatePartIndex(52), // (0x53) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(51), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: ready_valid.rs:130:5 + 74: BranchIfZero { + target: 76, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:131:9 + 75: Copy { + dest: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(52), // (0x53) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:130:5 + 76: BranchIfNonZero { + target: 78, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:136:13 + 77: Copy { + dest: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:91:19 + 78: IsNonZeroDestIsSmall { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + }, + 79: AndSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 80: Copy { + dest: StatePartIndex(8), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 81: SliceInt { + dest: StatePartIndex(9), // (0x29) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(8), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:79:32 + 82: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 83: BranchIfSmallNeImmediate { + target: 85, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 84: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 85: BranchIfSmallNeImmediate { + target: 87, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 86: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:101:5 + 87: Copy { + dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + src: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:156:5 + 88: BranchIfZero { + target: 93, + value: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:158:9 + 89: BranchIfZero { + target: 91, + value: StatePartIndex(62), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:159:13 + 90: Copy { + dest: StatePartIndex(26), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:158:9 + 91: BranchIfNonZero { + target: 93, + value: StatePartIndex(62), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:161:13 + 92: Copy { + dest: StatePartIndex(26), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(64), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 93: Copy { + dest: StatePartIndex(4), // (0x57) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(2), // (0x57) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 94: SliceInt { + dest: StatePartIndex(5), // (0x2b) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(4), // (0x57) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:77:32 + 95: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2), // (0x57) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 96: BranchIfSmallNeImmediate { + target: 98, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 97: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 98: BranchIfSmallNeImmediate { + target: 100, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 99: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + }, + // at: ready_valid.rs:98:5 + 100: Copy { + dest: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + src: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:116:5 + 101: Copy { + dest: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 102: IsNonZeroDestIsSmall { + dest: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 103: CmpNe { + dest: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + rhs: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:141:5 + 104: BranchIfZero { + target: 106, + value: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:142:9 + 105: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:146:5 + 106: BranchIfZero { + target: 111, + value: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:148:9 + 107: BranchIfZero { + target: 109, + value: StatePartIndex(57), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:149:13 + 108: Copy { + dest: StatePartIndex(23), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:148:9 + 109: BranchIfNonZero { + target: 111, + value: StatePartIndex(57), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:151:13 + 110: Copy { + dest: StatePartIndex(23), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(61), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:118:30 + 111: BranchIfSmallNeImmediate { + target: 113, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + 112: Copy { + dest: StatePartIndex(42), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(5), // (0x2b) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:118:5 + 113: Copy { + dest: StatePartIndex(18), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + src: StatePartIndex(42), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + }, + // at: ready_valid.rs:84:31 + 114: BranchIfSmallZero { + target: 119, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 115: BranchIfSmallNonZero { + target: 118, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 116: Copy { + dest: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + src: StatePartIndex(23), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + }, + 117: Branch { + target: 119, + }, + 118: Copy { + dest: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:86:25 + 119: BranchIfSmallZero { + target: 124, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 120: BranchIfSmallNonZero { + target: 123, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 121: Copy { + dest: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + src: StatePartIndex(26), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + }, + 122: Branch { + target: 124, + }, + 123: Copy { + dest: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:88:26 + 124: BranchIfSmallZero { + target: 129, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 125: BranchIfSmallNonZero { + target: 128, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 126: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + }, + 127: Branch { + target: 129, + }, + 128: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 129: BranchIfSmallZero { + target: 130, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 130: BranchIfSmallZero { + target: 138, + value: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 131: CopySmall { + dest: StatePartIndex(12), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(11), // (0x2 2) SlotDebugData { name: "", ty: UInt<2> }, + }, + 132: CopySmall { + dest: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 133: Copy { + dest: StatePartIndex(20), // (0x2b) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(18), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + }, + 134: Copy { + dest: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + }, + 135: BranchIfSmallZero { + target: 138, + value: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 136: BranchIfZero { + target: 138, + value: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 137: MemoryWriteUInt { + value: StatePartIndex(20), // (0x2b) SlotDebugData { name: "", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 3>, + // data: [ + // // len = 0x3 + // [0x0]: 0x2a, + // [0x1]: 0x2b, + // [0x2]: 0x29, + // ], + // }) (), + addr: StatePartIndex(12), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + stride: 8, + start: 0, + width: 8, + }, + 138: XorSmallImmediate { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 139: XorSmallImmediate { + dest: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:84:31 + 140: XorSmallImmediate { + dest: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:64:1 + 141: Return, + ], + .. + }, + pc: 141, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array, 3>, + data: [ + // len = 0x3 + [0x0]: 0x2a, + [0x1]: 0x2b, + [0x2]: 0x29, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 1, + 1, + 1, + 0, + 0, + 1, + 2, + 1, + 0, + 0, + 0, + 2, + 1, + 1, + 1, + 0, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 87, + 0, + 87, + 43, + 83, + 0, + 83, + 41, + 3, + 2, + 1, + 0, + 41, + 2, + 0, + 0, + 43, + 1, + 43, + 1, + 2, + 2, + 0, + 2, + 2, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 1, + 1, + 1, + 43, + 0, + 0, + 1, + 1, + 41, + 1, + 82, + 83, + 83, + 83, + 0, + 0, + 0, + 2, + 1, + 0, + 0, + 3, + 3, + 1, + 3, + 3, + 3, + 3, + 0, + 5, + 3, + 3, + 0, + 0, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.clk, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.rst, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.ready, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.ready, + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "queue", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "inp", + child: TraceBundle { + name: "inp", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(2), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(3), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(4), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceBundle { + name: "out", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(5), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(6), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(7), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + TraceModuleIO { + name: "count", + child: TraceUInt { + location: TraceScalarId(8), + name: "count", + ty: UInt<2>, + flow: Sink, + }, + ty: UInt<2>, + flow: Sink, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 3, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + }, + ], + array_type: Array, 3>, + }, + TraceReg { + name: "inp_index_reg", + child: TraceUInt { + location: TraceScalarId(18), + name: "inp_index_reg", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + TraceReg { + name: "out_index_reg", + child: TraceUInt { + location: TraceScalarId(19), + name: "out_index_reg", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + TraceReg { + name: "maybe_full_reg", + child: TraceBool { + location: TraceScalarId(20), + name: "maybe_full_reg", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "inp_firing", + child: TraceBool { + location: TraceScalarId(21), + name: "inp_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(22), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "out_firing", + child: TraceBool { + location: TraceScalarId(23), + name: "out_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(24), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "indexes_equal", + child: TraceBool { + location: TraceScalarId(25), + name: "indexes_equal", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "empty", + child: TraceBool { + location: TraceScalarId(26), + name: "empty", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "full", + child: TraceBool { + location: TraceScalarId(27), + name: "full", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "unwrap_or_else_out", + child: TraceUInt { + location: TraceScalarId(28), + name: "unwrap_or_else_out", + ty: UInt<8>, + flow: Duplex, + }, + ty: UInt<8>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSyncReset { + index: StatePartIndex(1), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<8>, + }, + state: 0x2b, + last_state: 0x2b, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigBool { + index: StatePartIndex(3), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(5), + kind: EnumDiscriminant { + index: StatePartIndex(1), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(9), + ty: UInt<8>, + }, + state: 0x29, + last_state: 0x29, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigBool { + index: StatePartIndex(7), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigUInt { + index: StatePartIndex(10), + ty: UInt<2>, + }, + state: 0x3, + last_state: 0x3, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigUInt { + index: StatePartIndex(11), + ty: UInt<2>, + }, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigBool { + index: StatePartIndex(12), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigClock { + index: StatePartIndex(13), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(12), + kind: BigUInt { + index: StatePartIndex(14), + ty: UInt<8>, + }, + state: 0x29, + last_state: 0x29, + }, + SimTrace { + id: TraceScalarId(13), + kind: BigUInt { + index: StatePartIndex(15), + ty: UInt<2>, + }, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigBool { + index: StatePartIndex(16), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(15), + kind: BigClock { + index: StatePartIndex(17), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(16), + kind: BigUInt { + index: StatePartIndex(18), + ty: UInt<8>, + }, + state: 0x2b, + last_state: 0x2b, + }, + SimTrace { + id: TraceScalarId(17), + kind: BigBool { + index: StatePartIndex(19), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigUInt { + index: StatePartIndex(22), + ty: UInt<2>, + }, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigUInt { + index: StatePartIndex(25), + ty: UInt<2>, + }, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(20), + kind: BigBool { + index: StatePartIndex(27), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(21), + kind: BigBool { + index: StatePartIndex(30), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(22), + kind: BigBool { + index: StatePartIndex(31), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(23), + kind: BigBool { + index: StatePartIndex(32), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(24), + kind: BigBool { + index: StatePartIndex(33), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(25), + kind: BigBool { + index: StatePartIndex(34), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(26), + kind: BigBool { + index: StatePartIndex(36), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(27), + kind: BigBool { + index: StatePartIndex(39), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(28), + kind: BigUInt { + index: StatePartIndex(42), + ty: UInt<8>, + }, + state: 0x2b, + last_state: 0x2b, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 3, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + }, + ], + array_type: Array, 3>, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [ + StatePartIndex(3), + StatePartIndex(8), + StatePartIndex(15), + ], + event_queue: EventQueue(EventQueueData { + instant: 100 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_3_true_false.vcd b/crates/fayalite/tests/sim/expected/queue_3_true_false.vcd new file mode 100644 index 0000000..53d6937 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/queue_3_true_false.vcd @@ -0,0 +1,1949 @@ +$timescale 1 ps $end +$scope module queue $end +$scope struct cd $end +$var wire 1 11z(a clk $end +$var wire 1 q1t|f rst $end +$upscope $end +$scope struct inp $end +$scope struct data $end +$var string 1 j|a-9 \$tag $end +$var wire 8 pjN&T HdlSome $end +$upscope $end +$var wire 1 *x8M* ready $end +$upscope $end +$scope struct out $end +$scope struct data $end +$var string 1 'Aa8} \$tag $end +$var wire 8 1b%.O HdlSome $end +$upscope $end +$var wire 1 vZD*c ready $end +$upscope $end +$var wire 2 rf7Xh count $end +$scope struct mem $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 8 (.Juw mem $end +$upscope $end +$scope struct \[1] $end +$var reg 8 5F$iE mem $end +$upscope $end +$scope struct \[2] $end +$var reg 8 !BEt5 mem $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var wire 2 K]Dkr addr $end +$var wire 1 P|=HX en $end +$var wire 1 z+ft% clk $end +$var wire 8 m+9ec data $end +$upscope $end +$scope struct w1 $end +$var wire 2 8Oa@o addr $end +$var wire 1 VaM[2 en $end +$var wire 1 aH[{] clk $end +$var wire 8 8|1uZ data $end +$var wire 1 DYq.y mask $end +$upscope $end +$upscope $end +$var reg 2 Xk?#v inp_index_reg $end +$var reg 2 p19yW out_index_reg $end +$var reg 1 kEQiI maybe_full_reg $end +$var wire 1 *gdL1 inp_firing $end +$var wire 1 ;HWUJ firing $end +$var wire 1 Ph#@^ out_firing $end +$var wire 1 ;HWUJ" firing_2 $end +$var wire 1 i[~ { + len: 18, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 71, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::indexes_equal", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::empty", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::full", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<66>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 1, + debug_data: [ + (), + ], + layout_data: [ + MemoryData { + array_type: Array, 3>, + data: [ + // len = 0x3 + [0x0]: 0x00, + [0x1]: 0x00, + [0x2]: 0x00, + ], + }, + ], + .. + }, + }, + insns: [ + // at: ready_valid.rs:64:1 + 0: SubU { + dest: StatePartIndex(69), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + dest_width: 3, + }, + 1: CastToUInt { + dest: StatePartIndex(70), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(69), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 2: CmpLt { + dest: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + 3: Const { + dest: StatePartIndex(63), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x3, + }, + 4: CastToUInt { + dest: StatePartIndex(64), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(63), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + dest_width: 2, + }, + 5: Add { + dest: StatePartIndex(66), // (0x5) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(63), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + }, + 6: SubU { + dest: StatePartIndex(67), // (0x3) SlotDebugData { name: "", ty: UInt<66> }, + lhs: StatePartIndex(66), // (0x5) SlotDebugData { name: "", ty: UInt<65> }, + rhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + dest_width: 66, + }, + 7: CastToUInt { + dest: StatePartIndex(68), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(67), // (0x3) SlotDebugData { name: "", ty: UInt<66> }, + dest_width: 2, + }, + 8: Const { + dest: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + value: 0x0, + }, + 9: CastToUInt { + dest: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 2, + }, + 10: Const { + dest: StatePartIndex(54), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x2, + }, + 11: CmpEq { + dest: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(54), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + }, + 12: CmpEq { + dest: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(54), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + }, + 13: Const { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 14: Add { + dest: StatePartIndex(58), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 15: CastToUInt { + dest: StatePartIndex(59), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(58), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 16: Add { + dest: StatePartIndex(61), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 17: CastToUInt { + dest: StatePartIndex(62), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(61), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 18: Const { + dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:118:30 + 19: Copy { + dest: StatePartIndex(42), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:117:5 + 20: Copy { + dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:115:5 + 21: Copy { + dest: StatePartIndex(15), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<2> }, + src: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:114:5 + 22: Copy { + dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:64:1 + 23: Const { + dest: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + value: 0x1, + }, + // at: ready_valid.rs:113:5 + 24: Copy { + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:119:5 + 25: Copy { + dest: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:112:5 + 26: Copy { + dest: StatePartIndex(11), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<2> }, + src: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 27: NotU { + dest: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + width: 1, + }, + 28: CmpEq { + dest: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:104:5 + 29: Copy { + dest: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + src: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 30: And { + dest: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:107:5 + 31: Copy { + dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + src: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 32: NotU { + dest: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + width: 1, + }, + 33: And { + dest: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:110:5 + 34: Copy { + dest: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + src: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 35: NotU { + dest: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + width: 1, + }, + // at: ready_valid.rs:121:5 + 36: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:124:9 + 37: BranchIfZero { + target: 39, + value: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:125:13 + 38: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:166:5 + 39: BranchIfZero { + target: 44, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 40: BranchIfZero { + target: 42, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:169:13 + 41: Copy { + dest: StatePartIndex(10), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(64), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:168:9 + 42: BranchIfNonZero { + target: 44, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:171:13 + 43: Copy { + dest: StatePartIndex(10), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:166:5 + 44: BranchIfNonZero { + target: 49, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:186:13 + 45: BranchIfZero { + target: 47, + value: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:187:17 + 46: Copy { + dest: StatePartIndex(10), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(68), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:186:13 + 47: BranchIfNonZero { + target: 49, + value: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:189:17 + 48: Copy { + dest: StatePartIndex(10), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(70), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:88:26 + 49: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 50: Const { + dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, + }, + // at: ready_valid.rs:86:25 + 51: Copy { + dest: StatePartIndex(26), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:84:31 + 52: IsNonZeroDestIsSmall { + dest: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.rst", ty: SyncReset }, + }, + 53: IsNonZeroDestIsSmall { + dest: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + 54: AndSmall { + dest: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 55: Copy { + dest: StatePartIndex(23), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 56: Const { + dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + value: 0x0, + }, + // at: ready_valid.rs:91:19 + 57: CastBigToArrayIndex { + dest: StatePartIndex(11), // (0x2 2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(15), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<2> }, + }, + 58: IsNonZeroDestIsSmall { + dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + }, + 59: AndSmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 60: CastBigToArrayIndex { + dest: StatePartIndex(6), // (0x2 2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(11), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<2> }, + }, + 61: IsNonZeroDestIsSmall { + dest: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + }, + 62: BranchIfSmallZero { + target: 65, + value: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 63: MemoryReadUInt { + dest: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 3>, + // data: [ + // // len = 0x3 + // [0x0]: 0x2a, + // [0x1]: 0x2b, + // [0x2]: 0x29, + // ], + // }) (), + addr: StatePartIndex(6), // (0x2 2) SlotDebugData { name: "", ty: UInt<2> }, + stride: 8, + start: 0, + width: 8, + }, + 64: Branch { + target: 66, + }, + 65: Const { + dest: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:64:1 + 66: Copy { + dest: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 67: Copy { + dest: StatePartIndex(47), // (0x29) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + }, + 68: Shl { + dest: StatePartIndex(49), // (0x52) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(47), // (0x29) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 1, + }, + 69: Or { + dest: StatePartIndex(50), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(49), // (0x52) SlotDebugData { name: "", ty: UInt<9> }, + }, + 70: CastToUInt { + dest: StatePartIndex(51), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(50), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + dest_width: 9, + }, + 71: Copy { + dest: StatePartIndex(52), // (0x53) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(51), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: ready_valid.rs:130:5 + 72: BranchIfZero { + target: 74, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:131:9 + 73: Copy { + dest: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(52), // (0x53) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:130:5 + 74: BranchIfNonZero { + target: 76, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:134:13 + 75: Copy { + dest: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(2), // (0x57) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:91:19 + 76: IsNonZeroDestIsSmall { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + }, + 77: AndSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 78: Copy { + dest: StatePartIndex(8), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 79: SliceInt { + dest: StatePartIndex(9), // (0x29) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(8), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:79:32 + 80: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 81: BranchIfSmallNeImmediate { + target: 83, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 82: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 83: BranchIfSmallNeImmediate { + target: 85, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 84: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:101:5 + 85: Copy { + dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + src: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:156:5 + 86: BranchIfZero { + target: 91, + value: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:158:9 + 87: BranchIfZero { + target: 89, + value: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:159:13 + 88: Copy { + dest: StatePartIndex(26), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:158:9 + 89: BranchIfNonZero { + target: 91, + value: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:161:13 + 90: Copy { + dest: StatePartIndex(26), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(62), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 91: Copy { + dest: StatePartIndex(4), // (0x57) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(2), // (0x57) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 92: SliceInt { + dest: StatePartIndex(5), // (0x2b) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(4), // (0x57) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:77:32 + 93: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2), // (0x57) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 94: BranchIfSmallNeImmediate { + target: 96, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 95: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 96: BranchIfSmallNeImmediate { + target: 98, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 97: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + }, + // at: ready_valid.rs:98:5 + 98: Copy { + dest: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + src: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:116:5 + 99: Copy { + dest: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 100: IsNonZeroDestIsSmall { + dest: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 101: CmpNe { + dest: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + rhs: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:141:5 + 102: BranchIfZero { + target: 104, + value: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:142:9 + 103: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:146:5 + 104: BranchIfZero { + target: 109, + value: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:148:9 + 105: BranchIfZero { + target: 107, + value: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:149:13 + 106: Copy { + dest: StatePartIndex(23), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:148:9 + 107: BranchIfNonZero { + target: 109, + value: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:151:13 + 108: Copy { + dest: StatePartIndex(23), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(59), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:118:30 + 109: BranchIfSmallNeImmediate { + target: 111, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + 110: Copy { + dest: StatePartIndex(42), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(5), // (0x2b) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:118:5 + 111: Copy { + dest: StatePartIndex(18), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + src: StatePartIndex(42), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + }, + // at: ready_valid.rs:84:31 + 112: BranchIfSmallZero { + target: 117, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 113: BranchIfSmallNonZero { + target: 116, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 114: Copy { + dest: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + src: StatePartIndex(23), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + }, + 115: Branch { + target: 117, + }, + 116: Copy { + dest: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:86:25 + 117: BranchIfSmallZero { + target: 122, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 118: BranchIfSmallNonZero { + target: 121, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 119: Copy { + dest: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + src: StatePartIndex(26), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + }, + 120: Branch { + target: 122, + }, + 121: Copy { + dest: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:88:26 + 122: BranchIfSmallZero { + target: 127, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 123: BranchIfSmallNonZero { + target: 126, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 124: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + }, + 125: Branch { + target: 127, + }, + 126: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 127: BranchIfSmallZero { + target: 128, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 128: BranchIfSmallZero { + target: 136, + value: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 129: CopySmall { + dest: StatePartIndex(12), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(11), // (0x2 2) SlotDebugData { name: "", ty: UInt<2> }, + }, + 130: CopySmall { + dest: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 131: Copy { + dest: StatePartIndex(20), // (0x2b) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(18), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + }, + 132: Copy { + dest: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + }, + 133: BranchIfSmallZero { + target: 136, + value: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 134: BranchIfZero { + target: 136, + value: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 135: MemoryWriteUInt { + value: StatePartIndex(20), // (0x2b) SlotDebugData { name: "", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 3>, + // data: [ + // // len = 0x3 + // [0x0]: 0x2a, + // [0x1]: 0x2b, + // [0x2]: 0x29, + // ], + // }) (), + addr: StatePartIndex(12), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + stride: 8, + start: 0, + width: 8, + }, + 136: XorSmallImmediate { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 137: XorSmallImmediate { + dest: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:84:31 + 138: XorSmallImmediate { + dest: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:64:1 + 139: Return, + ], + .. + }, + pc: 139, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array, 3>, + data: [ + // len = 0x3 + [0x0]: 0x2a, + [0x1]: 0x2b, + [0x2]: 0x29, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 1, + 1, + 1, + 0, + 0, + 1, + 2, + 1, + 0, + 0, + 0, + 2, + 1, + 1, + 1, + 0, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 87, + 0, + 87, + 43, + 83, + 0, + 83, + 41, + 3, + 2, + 1, + 0, + 41, + 2, + 0, + 0, + 43, + 1, + 43, + 1, + 2, + 2, + 0, + 2, + 2, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 1, + 1, + 1, + 43, + 0, + 0, + 1, + 1, + 41, + 1, + 82, + 83, + 83, + 83, + 0, + 2, + 1, + 0, + 0, + 3, + 3, + 1, + 3, + 3, + 3, + 3, + 0, + 5, + 3, + 3, + 0, + 0, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.clk, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.rst, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.ready, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.ready, + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "queue", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "inp", + child: TraceBundle { + name: "inp", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(2), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(3), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(4), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceBundle { + name: "out", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(5), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(6), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(7), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + TraceModuleIO { + name: "count", + child: TraceUInt { + location: TraceScalarId(8), + name: "count", + ty: UInt<2>, + flow: Sink, + }, + ty: UInt<2>, + flow: Sink, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 3, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + }, + ], + array_type: Array, 3>, + }, + TraceReg { + name: "inp_index_reg", + child: TraceUInt { + location: TraceScalarId(18), + name: "inp_index_reg", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + TraceReg { + name: "out_index_reg", + child: TraceUInt { + location: TraceScalarId(19), + name: "out_index_reg", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + TraceReg { + name: "maybe_full_reg", + child: TraceBool { + location: TraceScalarId(20), + name: "maybe_full_reg", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "inp_firing", + child: TraceBool { + location: TraceScalarId(21), + name: "inp_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(22), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "out_firing", + child: TraceBool { + location: TraceScalarId(23), + name: "out_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(24), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "indexes_equal", + child: TraceBool { + location: TraceScalarId(25), + name: "indexes_equal", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "empty", + child: TraceBool { + location: TraceScalarId(26), + name: "empty", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "full", + child: TraceBool { + location: TraceScalarId(27), + name: "full", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "unwrap_or_else_out", + child: TraceUInt { + location: TraceScalarId(28), + name: "unwrap_or_else_out", + ty: UInt<8>, + flow: Duplex, + }, + ty: UInt<8>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSyncReset { + index: StatePartIndex(1), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<8>, + }, + state: 0x2b, + last_state: 0x2b, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigBool { + index: StatePartIndex(3), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(5), + kind: EnumDiscriminant { + index: StatePartIndex(1), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(9), + ty: UInt<8>, + }, + state: 0x29, + last_state: 0x29, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigBool { + index: StatePartIndex(7), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigUInt { + index: StatePartIndex(10), + ty: UInt<2>, + }, + state: 0x3, + last_state: 0x3, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigUInt { + index: StatePartIndex(11), + ty: UInt<2>, + }, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigBool { + index: StatePartIndex(12), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigClock { + index: StatePartIndex(13), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(12), + kind: BigUInt { + index: StatePartIndex(14), + ty: UInt<8>, + }, + state: 0x29, + last_state: 0x29, + }, + SimTrace { + id: TraceScalarId(13), + kind: BigUInt { + index: StatePartIndex(15), + ty: UInt<2>, + }, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigBool { + index: StatePartIndex(16), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(15), + kind: BigClock { + index: StatePartIndex(17), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(16), + kind: BigUInt { + index: StatePartIndex(18), + ty: UInt<8>, + }, + state: 0x2b, + last_state: 0x2b, + }, + SimTrace { + id: TraceScalarId(17), + kind: BigBool { + index: StatePartIndex(19), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigUInt { + index: StatePartIndex(22), + ty: UInt<2>, + }, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigUInt { + index: StatePartIndex(25), + ty: UInt<2>, + }, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(20), + kind: BigBool { + index: StatePartIndex(27), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(21), + kind: BigBool { + index: StatePartIndex(30), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(22), + kind: BigBool { + index: StatePartIndex(31), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(23), + kind: BigBool { + index: StatePartIndex(32), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(24), + kind: BigBool { + index: StatePartIndex(33), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(25), + kind: BigBool { + index: StatePartIndex(34), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(26), + kind: BigBool { + index: StatePartIndex(36), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(27), + kind: BigBool { + index: StatePartIndex(39), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(28), + kind: BigUInt { + index: StatePartIndex(42), + ty: UInt<8>, + }, + state: 0x2b, + last_state: 0x2b, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 3, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + }, + ], + array_type: Array, 3>, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [ + StatePartIndex(3), + StatePartIndex(8), + StatePartIndex(15), + ], + event_queue: EventQueue(EventQueueData { + instant: 100 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_3_true_true.vcd b/crates/fayalite/tests/sim/expected/queue_3_true_true.vcd new file mode 100644 index 0000000..1c178a6 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/queue_3_true_true.vcd @@ -0,0 +1,1935 @@ +$timescale 1 ps $end +$scope module queue $end +$scope struct cd $end +$var wire 1 11z(a clk $end +$var wire 1 q1t|f rst $end +$upscope $end +$scope struct inp $end +$scope struct data $end +$var string 1 j|a-9 \$tag $end +$var wire 8 pjN&T HdlSome $end +$upscope $end +$var wire 1 *x8M* ready $end +$upscope $end +$scope struct out $end +$scope struct data $end +$var string 1 'Aa8} \$tag $end +$var wire 8 1b%.O HdlSome $end +$upscope $end +$var wire 1 vZD*c ready $end +$upscope $end +$var wire 2 rf7Xh count $end +$scope struct mem $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 8 (.Juw mem $end +$upscope $end +$scope struct \[1] $end +$var reg 8 5F$iE mem $end +$upscope $end +$scope struct \[2] $end +$var reg 8 !BEt5 mem $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var wire 2 K]Dkr addr $end +$var wire 1 P|=HX en $end +$var wire 1 z+ft% clk $end +$var wire 8 m+9ec data $end +$upscope $end +$scope struct w1 $end +$var wire 2 8Oa@o addr $end +$var wire 1 VaM[2 en $end +$var wire 1 aH[{] clk $end +$var wire 8 8|1uZ data $end +$var wire 1 DYq.y mask $end +$upscope $end +$upscope $end +$var reg 2 Xk?#v inp_index_reg $end +$var reg 2 p19yW out_index_reg $end +$var reg 1 kEQiI maybe_full_reg $end +$var wire 1 *gdL1 inp_firing $end +$var wire 1 ;HWUJ firing $end +$var wire 1 Ph#@^ out_firing $end +$var wire 1 ;HWUJ" firing_2 $end +$var wire 1 i[~ { + len: 18, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 72, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count", + ty: UInt<3>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::indexes_equal", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::empty", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::full", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count_lower", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 1, + debug_data: [ + (), + ], + layout_data: [ + MemoryData { + array_type: Array, 4>, + data: [ + // len = 0x4 + [0x0]: 0x00, + [0x1]: 0x00, + [0x2]: 0x00, + [0x3]: 0x00, + ], + }, + ], + .. + }, + }, + insns: [ + // at: ready_valid.rs:64:1 + 0: SubU { + dest: StatePartIndex(69), // (0x7) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + dest_width: 3, + }, + 1: CastToUInt { + dest: StatePartIndex(70), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(69), // (0x7) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + // at: ready_valid.rs:178:13 + 2: Copy { + dest: StatePartIndex(68), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<2> }, + src: StatePartIndex(70), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 3: CastToUInt { + dest: StatePartIndex(71), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(68), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<2> }, + dest_width: 3, + }, + 4: Const { + dest: StatePartIndex(65), // (0x4) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x4, + }, + 5: CastToUInt { + dest: StatePartIndex(66), // (0x4) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(65), // (0x4) SlotDebugData { name: "", ty: UInt<64> }, + dest_width: 3, + }, + 6: Const { + dest: StatePartIndex(58), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + value: 0x0, + }, + 7: CastToUInt { + dest: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(58), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 2, + }, + 8: CastToUInt { + dest: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(58), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 3, + }, + 9: Const { + dest: StatePartIndex(56), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x3, + }, + 10: CmpEq { + dest: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(56), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + }, + 11: CmpEq { + dest: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(56), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + }, + 12: Const { + dest: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + value: 0x0, + }, + 13: Copy { + dest: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + }, + 14: Const { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 15: Add { + dest: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 16: CastToUInt { + dest: StatePartIndex(61), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 17: Add { + dest: StatePartIndex(63), // (0x2) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 18: CastToUInt { + dest: StatePartIndex(64), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(63), // (0x2) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 19: Const { + dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:118:30 + 20: Copy { + dest: StatePartIndex(42), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:117:5 + 21: Copy { + dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:115:5 + 22: Copy { + dest: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<2> }, + src: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:114:5 + 23: Copy { + dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:64:1 + 24: Const { + dest: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + value: 0x1, + }, + // at: ready_valid.rs:113:5 + 25: Copy { + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:119:5 + 26: Copy { + dest: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:112:5 + 27: Copy { + dest: StatePartIndex(11), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<2> }, + src: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 28: NotU { + dest: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + width: 1, + }, + 29: CmpEq { + dest: StatePartIndex(35), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:104:5 + 30: Copy { + dest: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + src: StatePartIndex(35), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 31: And { + dest: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:107:5 + 32: Copy { + dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + src: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 33: NotU { + dest: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + width: 1, + }, + 34: And { + dest: StatePartIndex(40), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:110:5 + 35: Copy { + dest: StatePartIndex(39), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + src: StatePartIndex(40), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 36: NotU { + dest: StatePartIndex(44), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(39), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + width: 1, + }, + // at: ready_valid.rs:121:5 + 37: Copy { + dest: StatePartIndex(3), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(44), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:166:5 + 38: BranchIfZero { + target: 43, + value: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 39: BranchIfZero { + target: 41, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:169:13 + 40: Copy { + dest: StatePartIndex(10), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<3> }, + src: StatePartIndex(66), // (0x4) SlotDebugData { name: "", ty: UInt<3> }, + }, + // at: ready_valid.rs:168:9 + 41: BranchIfNonZero { + target: 43, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:171:13 + 42: Copy { + dest: StatePartIndex(10), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<3> }, + src: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + }, + // at: ready_valid.rs:166:5 + 43: BranchIfNonZero { + target: 45, + value: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:182:13 + 44: Copy { + dest: StatePartIndex(10), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<3> }, + src: StatePartIndex(71), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + }, + // at: ready_valid.rs:88:26 + 45: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 46: Const { + dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, + }, + // at: ready_valid.rs:86:25 + 47: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:84:31 + 48: IsNonZeroDestIsSmall { + dest: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.rst", ty: SyncReset }, + }, + 49: IsNonZeroDestIsSmall { + dest: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + 50: AndSmall { + dest: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 51: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 52: Const { + dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + value: 0x0, + }, + // at: ready_valid.rs:91:19 + 53: CastBigToArrayIndex { + dest: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<2> }, + }, + 54: IsNonZeroDestIsSmall { + dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + }, + 55: AndSmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 56: CastBigToArrayIndex { + dest: StatePartIndex(6), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(11), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<2> }, + }, + 57: IsNonZeroDestIsSmall { + dest: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + }, + 58: BranchIfSmallZero { + target: 61, + value: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 59: MemoryReadUInt { + dest: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 4>, + // data: [ + // // len = 0x4 + // [0x0]: 0x28, + // [0x1]: 0x29, + // [0x2]: 0x2a, + // [0x3]: 0x2b, + // ], + // }) (), + addr: StatePartIndex(6), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + stride: 8, + start: 0, + width: 8, + }, + 60: Branch { + target: 62, + }, + 61: Const { + dest: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:64:1 + 62: Copy { + dest: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 63: Copy { + dest: StatePartIndex(47), // (0x29) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + }, + 64: Shl { + dest: StatePartIndex(49), // (0x52) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(47), // (0x29) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 1, + }, + 65: Or { + dest: StatePartIndex(50), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(49), // (0x52) SlotDebugData { name: "", ty: UInt<9> }, + }, + 66: CastToUInt { + dest: StatePartIndex(51), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(50), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + dest_width: 9, + }, + 67: Copy { + dest: StatePartIndex(52), // (0x53) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(51), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: ready_valid.rs:130:5 + 68: BranchIfZero { + target: 70, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:131:9 + 69: Copy { + dest: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(52), // (0x53) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:130:5 + 70: BranchIfNonZero { + target: 72, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:136:13 + 71: Copy { + dest: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:91:19 + 72: IsNonZeroDestIsSmall { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + }, + 73: AndSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 74: Copy { + dest: StatePartIndex(8), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 75: SliceInt { + dest: StatePartIndex(9), // (0x29) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(8), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:79:32 + 76: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 77: BranchIfSmallNeImmediate { + target: 79, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 78: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 79: BranchIfSmallNeImmediate { + target: 81, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 80: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:101:5 + 81: Copy { + dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + src: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:156:5 + 82: BranchIfZero { + target: 87, + value: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:158:9 + 83: BranchIfZero { + target: 85, + value: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:159:13 + 84: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:158:9 + 85: BranchIfNonZero { + target: 87, + value: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:161:13 + 86: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(64), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 87: Copy { + dest: StatePartIndex(4), // (0x57) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(2), // (0x57) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 88: SliceInt { + dest: StatePartIndex(5), // (0x2b) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(4), // (0x57) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:77:32 + 89: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2), // (0x57) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 90: BranchIfSmallNeImmediate { + target: 92, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 91: Copy { + dest: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 92: BranchIfSmallNeImmediate { + target: 94, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 93: Copy { + dest: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(3), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + }, + // at: ready_valid.rs:98:5 + 94: Copy { + dest: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + src: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:116:5 + 95: Copy { + dest: StatePartIndex(16), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + src: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 96: IsNonZeroDestIsSmall { + dest: StatePartIndex(10), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(16), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 97: CmpNe { + dest: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + rhs: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:141:5 + 98: BranchIfZero { + target: 100, + value: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:142:9 + 99: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:146:5 + 100: BranchIfZero { + target: 105, + value: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:148:9 + 101: BranchIfZero { + target: 103, + value: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:149:13 + 102: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:148:9 + 103: BranchIfNonZero { + target: 105, + value: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:151:13 + 104: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(61), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:118:30 + 105: BranchIfSmallNeImmediate { + target: 107, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + 106: Copy { + dest: StatePartIndex(42), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(5), // (0x2b) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:118:5 + 107: Copy { + dest: StatePartIndex(18), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + src: StatePartIndex(42), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + }, + // at: ready_valid.rs:84:31 + 108: BranchIfSmallZero { + target: 113, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 109: BranchIfSmallNonZero { + target: 112, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 110: Copy { + dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + src: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + }, + 111: Branch { + target: 113, + }, + 112: Copy { + dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:86:25 + 113: BranchIfSmallZero { + target: 118, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 114: BranchIfSmallNonZero { + target: 117, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 115: Copy { + dest: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + src: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + }, + 116: Branch { + target: 118, + }, + 117: Copy { + dest: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:88:26 + 118: BranchIfSmallZero { + target: 123, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 119: BranchIfSmallNonZero { + target: 122, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 120: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + }, + 121: Branch { + target: 123, + }, + 122: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 123: BranchIfSmallZero { + target: 124, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 124: BranchIfSmallZero { + target: 132, + value: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 125: CopySmall { + dest: StatePartIndex(12), // (0x3 3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<2> }, + }, + 126: CopySmall { + dest: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(10), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 127: Copy { + dest: StatePartIndex(20), // (0x2b) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(18), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + }, + 128: Copy { + dest: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + }, + 129: BranchIfSmallZero { + target: 132, + value: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 130: BranchIfZero { + target: 132, + value: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 131: MemoryWriteUInt { + value: StatePartIndex(20), // (0x2b) SlotDebugData { name: "", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 4>, + // data: [ + // // len = 0x4 + // [0x0]: 0x28, + // [0x1]: 0x29, + // [0x2]: 0x2a, + // [0x3]: 0x2b, + // ], + // }) (), + addr: StatePartIndex(12), // (0x3 3) SlotDebugData { name: "", ty: UInt<2> }, + stride: 8, + start: 0, + width: 8, + }, + 132: XorSmallImmediate { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 133: XorSmallImmediate { + dest: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:84:31 + 134: XorSmallImmediate { + dest: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:64:1 + 135: Return, + ], + .. + }, + pc: 135, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array, 4>, + data: [ + // len = 0x4 + [0x0]: 0x28, + [0x1]: 0x29, + [0x2]: 0x2a, + [0x3]: 0x2b, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 1, + 1, + 1, + 0, + 0, + 1, + 1, + 1, + 0, + 0, + 1, + 0, + 3, + 1, + 1, + 0, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 87, + 1, + 87, + 43, + 83, + 0, + 83, + 41, + 3, + 1, + 1, + 0, + 41, + 0, + 1, + 0, + 43, + 1, + 43, + 1, + 0, + 1, + 0, + 1, + 1, + 1, + 1, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 43, + 0, + 1, + 1, + 1, + 41, + 1, + 82, + 83, + 83, + 83, + 0, + 0, + 1, + 3, + 0, + 0, + 0, + 1, + 1, + 0, + 2, + 2, + 4, + 4, + 0, + 3, + 7, + 3, + 3, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.clk, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.rst, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.ready, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.ready, + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "queue", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "inp", + child: TraceBundle { + name: "inp", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(2), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(3), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(4), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceBundle { + name: "out", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(5), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(6), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(7), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + TraceModuleIO { + name: "count", + child: TraceUInt { + location: TraceScalarId(8), + name: "count", + ty: UInt<3>, + flow: Sink, + }, + ty: UInt<3>, + flow: Sink, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 4, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + }, + ], + array_type: Array, 4>, + }, + TraceReg { + name: "inp_index_reg", + child: TraceUInt { + location: TraceScalarId(18), + name: "inp_index_reg", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + TraceReg { + name: "out_index_reg", + child: TraceUInt { + location: TraceScalarId(19), + name: "out_index_reg", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + TraceReg { + name: "maybe_full_reg", + child: TraceBool { + location: TraceScalarId(20), + name: "maybe_full_reg", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "inp_firing", + child: TraceBool { + location: TraceScalarId(21), + name: "inp_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(22), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "out_firing", + child: TraceBool { + location: TraceScalarId(23), + name: "out_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(24), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "indexes_equal", + child: TraceBool { + location: TraceScalarId(25), + name: "indexes_equal", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "empty", + child: TraceBool { + location: TraceScalarId(26), + name: "empty", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "full", + child: TraceBool { + location: TraceScalarId(27), + name: "full", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "unwrap_or_else_out", + child: TraceUInt { + location: TraceScalarId(28), + name: "unwrap_or_else_out", + ty: UInt<8>, + flow: Duplex, + }, + ty: UInt<8>, + }, + TraceWire { + name: "count_lower", + child: TraceUInt { + location: TraceScalarId(29), + name: "count_lower", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSyncReset { + index: StatePartIndex(1), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<8>, + }, + state: 0x2b, + last_state: 0x2b, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigBool { + index: StatePartIndex(3), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(5), + kind: EnumDiscriminant { + index: StatePartIndex(1), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(9), + ty: UInt<8>, + }, + state: 0x29, + last_state: 0x29, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigBool { + index: StatePartIndex(7), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigUInt { + index: StatePartIndex(10), + ty: UInt<3>, + }, + state: 0x3, + last_state: 0x3, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigUInt { + index: StatePartIndex(11), + ty: UInt<2>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigBool { + index: StatePartIndex(12), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigClock { + index: StatePartIndex(13), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(12), + kind: BigUInt { + index: StatePartIndex(14), + ty: UInt<8>, + }, + state: 0x29, + last_state: 0x29, + }, + SimTrace { + id: TraceScalarId(13), + kind: BigUInt { + index: StatePartIndex(15), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigBool { + index: StatePartIndex(16), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(15), + kind: BigClock { + index: StatePartIndex(17), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(16), + kind: BigUInt { + index: StatePartIndex(18), + ty: UInt<8>, + }, + state: 0x2b, + last_state: 0x2b, + }, + SimTrace { + id: TraceScalarId(17), + kind: BigBool { + index: StatePartIndex(19), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigUInt { + index: StatePartIndex(22), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigUInt { + index: StatePartIndex(25), + ty: UInt<2>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(20), + kind: BigBool { + index: StatePartIndex(27), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(21), + kind: BigBool { + index: StatePartIndex(30), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(22), + kind: BigBool { + index: StatePartIndex(31), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(23), + kind: BigBool { + index: StatePartIndex(32), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(24), + kind: BigBool { + index: StatePartIndex(33), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(25), + kind: BigBool { + index: StatePartIndex(34), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(26), + kind: BigBool { + index: StatePartIndex(36), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(27), + kind: BigBool { + index: StatePartIndex(39), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(28), + kind: BigUInt { + index: StatePartIndex(42), + ty: UInt<8>, + }, + state: 0x2b, + last_state: 0x2b, + }, + SimTrace { + id: TraceScalarId(29), + kind: BigUInt { + index: StatePartIndex(68), + ty: UInt<2>, + }, + state: 0x3, + last_state: 0x3, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 4, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + }, + ], + array_type: Array, 4>, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [ + StatePartIndex(3), + StatePartIndex(8), + StatePartIndex(15), + ], + event_queue: EventQueue(EventQueueData { + instant: 100 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_4_false_false.vcd b/crates/fayalite/tests/sim/expected/queue_4_false_false.vcd new file mode 100644 index 0000000..5373a84 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/queue_4_false_false.vcd @@ -0,0 +1,2025 @@ +$timescale 1 ps $end +$scope module queue $end +$scope struct cd $end +$var wire 1 11z(a clk $end +$var wire 1 q1t|f rst $end +$upscope $end +$scope struct inp $end +$scope struct data $end +$var string 1 j|a-9 \$tag $end +$var wire 8 pjN&T HdlSome $end +$upscope $end +$var wire 1 *x8M* ready $end +$upscope $end +$scope struct out $end +$scope struct data $end +$var string 1 'Aa8} \$tag $end +$var wire 8 1b%.O HdlSome $end +$upscope $end +$var wire 1 vZD*c ready $end +$upscope $end +$var wire 3 rf7Xh count $end +$scope struct mem $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 8 (.Juw mem $end +$upscope $end +$scope struct \[1] $end +$var reg 8 5F$iE mem $end +$upscope $end +$scope struct \[2] $end +$var reg 8 !BEt5 mem $end +$upscope $end +$scope struct \[3] $end +$var reg 8 C7]kZ mem $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var wire 2 K]Dkr addr $end +$var wire 1 P|=HX en $end +$var wire 1 z+ft% clk $end +$var wire 8 m+9ec data $end +$upscope $end +$scope struct w1 $end +$var wire 2 8Oa@o addr $end +$var wire 1 VaM[2 en $end +$var wire 1 aH[{] clk $end +$var wire 8 8|1uZ data $end +$var wire 1 DYq.y mask $end +$upscope $end +$upscope $end +$var reg 2 Xk?#v inp_index_reg $end +$var reg 2 p19yW out_index_reg $end +$var reg 1 kEQiI maybe_full_reg $end +$var wire 1 *gdL1 inp_firing $end +$var wire 1 ;HWUJ firing $end +$var wire 1 Ph#@^ out_firing $end +$var wire 1 ;HWUJ" firing_2 $end +$var wire 1 i[~ { + len: 18, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 70, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count", + ty: UInt<3>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::indexes_equal", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::empty", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::full", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count_lower", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 1, + debug_data: [ + (), + ], + layout_data: [ + MemoryData { + array_type: Array, 4>, + data: [ + // len = 0x4 + [0x0]: 0x00, + [0x1]: 0x00, + [0x2]: 0x00, + [0x3]: 0x00, + ], + }, + ], + .. + }, + }, + insns: [ + // at: ready_valid.rs:64:1 + 0: SubU { + dest: StatePartIndex(67), // (0x7) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + dest_width: 3, + }, + 1: CastToUInt { + dest: StatePartIndex(68), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(67), // (0x7) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + // at: ready_valid.rs:178:13 + 2: Copy { + dest: StatePartIndex(66), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<2> }, + src: StatePartIndex(68), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 3: CastToUInt { + dest: StatePartIndex(69), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(66), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<2> }, + dest_width: 3, + }, + 4: Const { + dest: StatePartIndex(63), // (0x4) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x4, + }, + 5: CastToUInt { + dest: StatePartIndex(64), // (0x4) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(63), // (0x4) SlotDebugData { name: "", ty: UInt<64> }, + dest_width: 3, + }, + 6: Const { + dest: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + value: 0x0, + }, + 7: CastToUInt { + dest: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 2, + }, + 8: CastToUInt { + dest: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 3, + }, + 9: Const { + dest: StatePartIndex(54), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x3, + }, + 10: CmpEq { + dest: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(54), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + }, + 11: CmpEq { + dest: StatePartIndex(60), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(54), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + }, + 12: Const { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 13: Add { + dest: StatePartIndex(58), // (0x1) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 14: CastToUInt { + dest: StatePartIndex(59), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(58), // (0x1) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 15: Add { + dest: StatePartIndex(61), // (0x2) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 16: CastToUInt { + dest: StatePartIndex(62), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(61), // (0x2) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 17: Const { + dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:118:30 + 18: Copy { + dest: StatePartIndex(42), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:117:5 + 19: Copy { + dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:115:5 + 20: Copy { + dest: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<2> }, + src: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:114:5 + 21: Copy { + dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:64:1 + 22: Const { + dest: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + value: 0x1, + }, + // at: ready_valid.rs:113:5 + 23: Copy { + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:119:5 + 24: Copy { + dest: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:112:5 + 25: Copy { + dest: StatePartIndex(11), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<2> }, + src: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 26: NotU { + dest: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + width: 1, + }, + 27: CmpEq { + dest: StatePartIndex(35), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:104:5 + 28: Copy { + dest: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + src: StatePartIndex(35), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 29: And { + dest: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:107:5 + 30: Copy { + dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + src: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 31: NotU { + dest: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + width: 1, + }, + 32: And { + dest: StatePartIndex(40), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:110:5 + 33: Copy { + dest: StatePartIndex(39), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + src: StatePartIndex(40), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 34: NotU { + dest: StatePartIndex(44), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(39), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + width: 1, + }, + // at: ready_valid.rs:121:5 + 35: Copy { + dest: StatePartIndex(3), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(44), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:166:5 + 36: BranchIfZero { + target: 41, + value: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 37: BranchIfZero { + target: 39, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:169:13 + 38: Copy { + dest: StatePartIndex(10), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<3> }, + src: StatePartIndex(64), // (0x4) SlotDebugData { name: "", ty: UInt<3> }, + }, + // at: ready_valid.rs:168:9 + 39: BranchIfNonZero { + target: 41, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:171:13 + 40: Copy { + dest: StatePartIndex(10), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<3> }, + src: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + }, + // at: ready_valid.rs:166:5 + 41: BranchIfNonZero { + target: 43, + value: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:182:13 + 42: Copy { + dest: StatePartIndex(10), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<3> }, + src: StatePartIndex(69), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + }, + // at: ready_valid.rs:88:26 + 43: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 44: Const { + dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, + }, + // at: ready_valid.rs:86:25 + 45: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:84:31 + 46: IsNonZeroDestIsSmall { + dest: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.rst", ty: SyncReset }, + }, + 47: IsNonZeroDestIsSmall { + dest: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + 48: AndSmall { + dest: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 49: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 50: Const { + dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + value: 0x0, + }, + // at: ready_valid.rs:91:19 + 51: CastBigToArrayIndex { + dest: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<2> }, + }, + 52: IsNonZeroDestIsSmall { + dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + }, + 53: AndSmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 54: CastBigToArrayIndex { + dest: StatePartIndex(6), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(11), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<2> }, + }, + 55: IsNonZeroDestIsSmall { + dest: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + }, + 56: BranchIfSmallZero { + target: 59, + value: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 57: MemoryReadUInt { + dest: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 4>, + // data: [ + // // len = 0x4 + // [0x0]: 0x28, + // [0x1]: 0x29, + // [0x2]: 0x2a, + // [0x3]: 0x2b, + // ], + // }) (), + addr: StatePartIndex(6), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + stride: 8, + start: 0, + width: 8, + }, + 58: Branch { + target: 60, + }, + 59: Const { + dest: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:64:1 + 60: Copy { + dest: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 61: Copy { + dest: StatePartIndex(47), // (0x29) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + }, + 62: Shl { + dest: StatePartIndex(49), // (0x52) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(47), // (0x29) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 1, + }, + 63: Or { + dest: StatePartIndex(50), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(49), // (0x52) SlotDebugData { name: "", ty: UInt<9> }, + }, + 64: CastToUInt { + dest: StatePartIndex(51), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(50), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + dest_width: 9, + }, + 65: Copy { + dest: StatePartIndex(52), // (0x53) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(51), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: ready_valid.rs:130:5 + 66: BranchIfZero { + target: 68, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:131:9 + 67: Copy { + dest: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(52), // (0x53) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:130:5 + 68: BranchIfNonZero { + target: 70, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:134:13 + 69: Copy { + dest: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(2), // (0x57) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:91:19 + 70: IsNonZeroDestIsSmall { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + }, + 71: AndSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 72: Copy { + dest: StatePartIndex(8), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 73: SliceInt { + dest: StatePartIndex(9), // (0x29) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(8), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:79:32 + 74: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 75: BranchIfSmallNeImmediate { + target: 77, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 76: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 77: BranchIfSmallNeImmediate { + target: 79, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 78: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:101:5 + 79: Copy { + dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + src: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:156:5 + 80: BranchIfZero { + target: 85, + value: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:158:9 + 81: BranchIfZero { + target: 83, + value: StatePartIndex(60), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:159:13 + 82: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:158:9 + 83: BranchIfNonZero { + target: 85, + value: StatePartIndex(60), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:161:13 + 84: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(62), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 85: Copy { + dest: StatePartIndex(4), // (0x57) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(2), // (0x57) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 86: SliceInt { + dest: StatePartIndex(5), // (0x2b) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(4), // (0x57) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:77:32 + 87: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2), // (0x57) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 88: BranchIfSmallNeImmediate { + target: 90, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 89: Copy { + dest: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 90: BranchIfSmallNeImmediate { + target: 92, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 91: Copy { + dest: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(3), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + }, + // at: ready_valid.rs:98:5 + 92: Copy { + dest: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + src: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:116:5 + 93: Copy { + dest: StatePartIndex(16), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + src: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 94: IsNonZeroDestIsSmall { + dest: StatePartIndex(10), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(16), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 95: CmpNe { + dest: StatePartIndex(53), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + rhs: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:141:5 + 96: BranchIfZero { + target: 98, + value: StatePartIndex(53), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:142:9 + 97: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:146:5 + 98: BranchIfZero { + target: 103, + value: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:148:9 + 99: BranchIfZero { + target: 101, + value: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:149:13 + 100: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:148:9 + 101: BranchIfNonZero { + target: 103, + value: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:151:13 + 102: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(59), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:118:30 + 103: BranchIfSmallNeImmediate { + target: 105, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + 104: Copy { + dest: StatePartIndex(42), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(5), // (0x2b) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:118:5 + 105: Copy { + dest: StatePartIndex(18), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + src: StatePartIndex(42), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + }, + // at: ready_valid.rs:84:31 + 106: BranchIfSmallZero { + target: 111, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 107: BranchIfSmallNonZero { + target: 110, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 108: Copy { + dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + src: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + }, + 109: Branch { + target: 111, + }, + 110: Copy { + dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:86:25 + 111: BranchIfSmallZero { + target: 116, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 112: BranchIfSmallNonZero { + target: 115, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 113: Copy { + dest: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + src: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + }, + 114: Branch { + target: 116, + }, + 115: Copy { + dest: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:88:26 + 116: BranchIfSmallZero { + target: 121, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 117: BranchIfSmallNonZero { + target: 120, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 118: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + }, + 119: Branch { + target: 121, + }, + 120: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 121: BranchIfSmallZero { + target: 122, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 122: BranchIfSmallZero { + target: 130, + value: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 123: CopySmall { + dest: StatePartIndex(12), // (0x3 3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<2> }, + }, + 124: CopySmall { + dest: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(10), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 125: Copy { + dest: StatePartIndex(20), // (0x2b) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(18), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + }, + 126: Copy { + dest: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + }, + 127: BranchIfSmallZero { + target: 130, + value: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 128: BranchIfZero { + target: 130, + value: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 129: MemoryWriteUInt { + value: StatePartIndex(20), // (0x2b) SlotDebugData { name: "", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 4>, + // data: [ + // // len = 0x4 + // [0x0]: 0x28, + // [0x1]: 0x29, + // [0x2]: 0x2a, + // [0x3]: 0x2b, + // ], + // }) (), + addr: StatePartIndex(12), // (0x3 3) SlotDebugData { name: "", ty: UInt<2> }, + stride: 8, + start: 0, + width: 8, + }, + 130: XorSmallImmediate { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 131: XorSmallImmediate { + dest: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:84:31 + 132: XorSmallImmediate { + dest: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:64:1 + 133: Return, + ], + .. + }, + pc: 133, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array, 4>, + data: [ + // len = 0x4 + [0x0]: 0x28, + [0x1]: 0x29, + [0x2]: 0x2a, + [0x3]: 0x2b, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 1, + 1, + 1, + 0, + 0, + 1, + 1, + 1, + 0, + 0, + 1, + 0, + 3, + 1, + 1, + 0, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 87, + 1, + 87, + 43, + 83, + 0, + 83, + 41, + 3, + 1, + 1, + 0, + 41, + 0, + 1, + 0, + 43, + 1, + 43, + 1, + 0, + 1, + 0, + 1, + 1, + 1, + 1, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 43, + 0, + 1, + 1, + 1, + 41, + 1, + 82, + 83, + 83, + 83, + 1, + 3, + 0, + 0, + 0, + 1, + 1, + 0, + 2, + 2, + 4, + 4, + 0, + 3, + 7, + 3, + 3, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.clk, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.rst, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.ready, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.ready, + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "queue", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "inp", + child: TraceBundle { + name: "inp", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(2), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(3), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(4), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceBundle { + name: "out", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(5), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(6), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(7), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + TraceModuleIO { + name: "count", + child: TraceUInt { + location: TraceScalarId(8), + name: "count", + ty: UInt<3>, + flow: Sink, + }, + ty: UInt<3>, + flow: Sink, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 4, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + }, + ], + array_type: Array, 4>, + }, + TraceReg { + name: "inp_index_reg", + child: TraceUInt { + location: TraceScalarId(18), + name: "inp_index_reg", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + TraceReg { + name: "out_index_reg", + child: TraceUInt { + location: TraceScalarId(19), + name: "out_index_reg", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + TraceReg { + name: "maybe_full_reg", + child: TraceBool { + location: TraceScalarId(20), + name: "maybe_full_reg", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "inp_firing", + child: TraceBool { + location: TraceScalarId(21), + name: "inp_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(22), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "out_firing", + child: TraceBool { + location: TraceScalarId(23), + name: "out_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(24), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "indexes_equal", + child: TraceBool { + location: TraceScalarId(25), + name: "indexes_equal", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "empty", + child: TraceBool { + location: TraceScalarId(26), + name: "empty", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "full", + child: TraceBool { + location: TraceScalarId(27), + name: "full", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "unwrap_or_else_out", + child: TraceUInt { + location: TraceScalarId(28), + name: "unwrap_or_else_out", + ty: UInt<8>, + flow: Duplex, + }, + ty: UInt<8>, + }, + TraceWire { + name: "count_lower", + child: TraceUInt { + location: TraceScalarId(29), + name: "count_lower", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSyncReset { + index: StatePartIndex(1), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<8>, + }, + state: 0x2b, + last_state: 0x2b, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigBool { + index: StatePartIndex(3), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(5), + kind: EnumDiscriminant { + index: StatePartIndex(1), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(9), + ty: UInt<8>, + }, + state: 0x29, + last_state: 0x29, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigBool { + index: StatePartIndex(7), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigUInt { + index: StatePartIndex(10), + ty: UInt<3>, + }, + state: 0x3, + last_state: 0x3, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigUInt { + index: StatePartIndex(11), + ty: UInt<2>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigBool { + index: StatePartIndex(12), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigClock { + index: StatePartIndex(13), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(12), + kind: BigUInt { + index: StatePartIndex(14), + ty: UInt<8>, + }, + state: 0x29, + last_state: 0x29, + }, + SimTrace { + id: TraceScalarId(13), + kind: BigUInt { + index: StatePartIndex(15), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigBool { + index: StatePartIndex(16), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(15), + kind: BigClock { + index: StatePartIndex(17), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(16), + kind: BigUInt { + index: StatePartIndex(18), + ty: UInt<8>, + }, + state: 0x2b, + last_state: 0x2b, + }, + SimTrace { + id: TraceScalarId(17), + kind: BigBool { + index: StatePartIndex(19), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigUInt { + index: StatePartIndex(22), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigUInt { + index: StatePartIndex(25), + ty: UInt<2>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(20), + kind: BigBool { + index: StatePartIndex(27), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(21), + kind: BigBool { + index: StatePartIndex(30), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(22), + kind: BigBool { + index: StatePartIndex(31), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(23), + kind: BigBool { + index: StatePartIndex(32), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(24), + kind: BigBool { + index: StatePartIndex(33), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(25), + kind: BigBool { + index: StatePartIndex(34), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(26), + kind: BigBool { + index: StatePartIndex(36), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(27), + kind: BigBool { + index: StatePartIndex(39), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(28), + kind: BigUInt { + index: StatePartIndex(42), + ty: UInt<8>, + }, + state: 0x2b, + last_state: 0x2b, + }, + SimTrace { + id: TraceScalarId(29), + kind: BigUInt { + index: StatePartIndex(66), + ty: UInt<2>, + }, + state: 0x3, + last_state: 0x3, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 4, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + }, + ], + array_type: Array, 4>, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [ + StatePartIndex(3), + StatePartIndex(8), + StatePartIndex(15), + ], + event_queue: EventQueue(EventQueueData { + instant: 100 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_4_false_true.vcd b/crates/fayalite/tests/sim/expected/queue_4_false_true.vcd new file mode 100644 index 0000000..bed1241 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/queue_4_false_true.vcd @@ -0,0 +1,2021 @@ +$timescale 1 ps $end +$scope module queue $end +$scope struct cd $end +$var wire 1 11z(a clk $end +$var wire 1 q1t|f rst $end +$upscope $end +$scope struct inp $end +$scope struct data $end +$var string 1 j|a-9 \$tag $end +$var wire 8 pjN&T HdlSome $end +$upscope $end +$var wire 1 *x8M* ready $end +$upscope $end +$scope struct out $end +$scope struct data $end +$var string 1 'Aa8} \$tag $end +$var wire 8 1b%.O HdlSome $end +$upscope $end +$var wire 1 vZD*c ready $end +$upscope $end +$var wire 3 rf7Xh count $end +$scope struct mem $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 8 (.Juw mem $end +$upscope $end +$scope struct \[1] $end +$var reg 8 5F$iE mem $end +$upscope $end +$scope struct \[2] $end +$var reg 8 !BEt5 mem $end +$upscope $end +$scope struct \[3] $end +$var reg 8 C7]kZ mem $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var wire 2 K]Dkr addr $end +$var wire 1 P|=HX en $end +$var wire 1 z+ft% clk $end +$var wire 8 m+9ec data $end +$upscope $end +$scope struct w1 $end +$var wire 2 8Oa@o addr $end +$var wire 1 VaM[2 en $end +$var wire 1 aH[{] clk $end +$var wire 8 8|1uZ data $end +$var wire 1 DYq.y mask $end +$upscope $end +$upscope $end +$var reg 2 Xk?#v inp_index_reg $end +$var reg 2 p19yW out_index_reg $end +$var reg 1 kEQiI maybe_full_reg $end +$var wire 1 *gdL1 inp_firing $end +$var wire 1 ;HWUJ firing $end +$var wire 1 Ph#@^ out_firing $end +$var wire 1 ;HWUJ" firing_2 $end +$var wire 1 i[~ { + len: 18, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 72, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count", + ty: UInt<3>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::indexes_equal", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::empty", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::full", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count_lower", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 1, + debug_data: [ + (), + ], + layout_data: [ + MemoryData { + array_type: Array, 4>, + data: [ + // len = 0x4 + [0x0]: 0x00, + [0x1]: 0x00, + [0x2]: 0x00, + [0x3]: 0x00, + ], + }, + ], + .. + }, + }, + insns: [ + // at: ready_valid.rs:64:1 + 0: SubU { + dest: StatePartIndex(69), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + dest_width: 3, + }, + 1: CastToUInt { + dest: StatePartIndex(70), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(69), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + // at: ready_valid.rs:178:13 + 2: Copy { + dest: StatePartIndex(68), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<2> }, + src: StatePartIndex(70), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 3: CastToUInt { + dest: StatePartIndex(71), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(68), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<2> }, + dest_width: 3, + }, + 4: Const { + dest: StatePartIndex(65), // (0x4) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x4, + }, + 5: CastToUInt { + dest: StatePartIndex(66), // (0x4) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(65), // (0x4) SlotDebugData { name: "", ty: UInt<64> }, + dest_width: 3, + }, + 6: Const { + dest: StatePartIndex(58), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + value: 0x0, + }, + 7: CastToUInt { + dest: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(58), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 2, + }, + 8: CastToUInt { + dest: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(58), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 3, + }, + 9: Const { + dest: StatePartIndex(56), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x3, + }, + 10: CmpEq { + dest: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(56), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + }, + 11: CmpEq { + dest: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(56), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + }, + 12: Const { + dest: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + value: 0x0, + }, + 13: Copy { + dest: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + }, + 14: Const { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 15: Add { + dest: StatePartIndex(60), // (0x2) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 16: CastToUInt { + dest: StatePartIndex(61), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(60), // (0x2) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 17: Add { + dest: StatePartIndex(63), // (0x2) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 18: CastToUInt { + dest: StatePartIndex(64), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(63), // (0x2) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 19: Const { + dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:118:30 + 20: Copy { + dest: StatePartIndex(42), // (0x2c) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:117:5 + 21: Copy { + dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:115:5 + 22: Copy { + dest: StatePartIndex(15), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<2> }, + src: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:114:5 + 23: Copy { + dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:64:1 + 24: Const { + dest: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + value: 0x1, + }, + // at: ready_valid.rs:113:5 + 25: Copy { + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:119:5 + 26: Copy { + dest: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:112:5 + 27: Copy { + dest: StatePartIndex(11), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<2> }, + src: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 28: NotU { + dest: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + width: 1, + }, + 29: CmpEq { + dest: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:104:5 + 30: Copy { + dest: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + src: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 31: And { + dest: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:107:5 + 32: Copy { + dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + src: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 33: NotU { + dest: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + width: 1, + }, + 34: And { + dest: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:110:5 + 35: Copy { + dest: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + src: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 36: NotU { + dest: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + width: 1, + }, + // at: ready_valid.rs:121:5 + 37: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:124:9 + 38: BranchIfZero { + target: 40, + value: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:125:13 + 39: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:166:5 + 40: BranchIfZero { + target: 45, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 41: BranchIfZero { + target: 43, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:169:13 + 42: Copy { + dest: StatePartIndex(10), // (0x4) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<3> }, + src: StatePartIndex(66), // (0x4) SlotDebugData { name: "", ty: UInt<3> }, + }, + // at: ready_valid.rs:168:9 + 43: BranchIfNonZero { + target: 45, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:171:13 + 44: Copy { + dest: StatePartIndex(10), // (0x4) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<3> }, + src: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + }, + // at: ready_valid.rs:166:5 + 45: BranchIfNonZero { + target: 47, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:182:13 + 46: Copy { + dest: StatePartIndex(10), // (0x4) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<3> }, + src: StatePartIndex(71), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + }, + // at: ready_valid.rs:88:26 + 47: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 48: Const { + dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, + }, + // at: ready_valid.rs:86:25 + 49: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:84:31 + 50: IsNonZeroDestIsSmall { + dest: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.rst", ty: SyncReset }, + }, + 51: IsNonZeroDestIsSmall { + dest: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + 52: AndSmall { + dest: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 53: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 54: Const { + dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + value: 0x0, + }, + // at: ready_valid.rs:91:19 + 55: CastBigToArrayIndex { + dest: StatePartIndex(11), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(15), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<2> }, + }, + 56: IsNonZeroDestIsSmall { + dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + }, + 57: AndSmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 58: CastBigToArrayIndex { + dest: StatePartIndex(6), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(11), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<2> }, + }, + 59: IsNonZeroDestIsSmall { + dest: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + }, + 60: BranchIfSmallZero { + target: 63, + value: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 61: MemoryReadUInt { + dest: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 4>, + // data: [ + // // len = 0x4 + // [0x0]: 0x2c, + // [0x1]: 0x29, + // [0x2]: 0x2a, + // [0x3]: 0x2b, + // ], + // }) (), + addr: StatePartIndex(6), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + stride: 8, + start: 0, + width: 8, + }, + 62: Branch { + target: 64, + }, + 63: Const { + dest: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:64:1 + 64: Copy { + dest: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 65: Copy { + dest: StatePartIndex(47), // (0x29) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + }, + 66: Shl { + dest: StatePartIndex(49), // (0x52) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(47), // (0x29) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 1, + }, + 67: Or { + dest: StatePartIndex(50), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(49), // (0x52) SlotDebugData { name: "", ty: UInt<9> }, + }, + 68: CastToUInt { + dest: StatePartIndex(51), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(50), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + dest_width: 9, + }, + 69: Copy { + dest: StatePartIndex(52), // (0x53) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(51), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: ready_valid.rs:130:5 + 70: BranchIfZero { + target: 72, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:131:9 + 71: Copy { + dest: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(52), // (0x53) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:130:5 + 72: BranchIfNonZero { + target: 74, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:136:13 + 73: Copy { + dest: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:91:19 + 74: IsNonZeroDestIsSmall { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + }, + 75: AndSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 76: Copy { + dest: StatePartIndex(8), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 77: SliceInt { + dest: StatePartIndex(9), // (0x29) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(8), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:79:32 + 78: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 79: BranchIfSmallNeImmediate { + target: 81, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 80: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 81: BranchIfSmallNeImmediate { + target: 83, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 82: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:101:5 + 83: Copy { + dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + src: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:156:5 + 84: BranchIfZero { + target: 89, + value: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:158:9 + 85: BranchIfZero { + target: 87, + value: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:159:13 + 86: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:158:9 + 87: BranchIfNonZero { + target: 89, + value: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:161:13 + 88: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(64), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 89: Copy { + dest: StatePartIndex(4), // (0x59) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(2), // (0x59) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 90: SliceInt { + dest: StatePartIndex(5), // (0x2c) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(4), // (0x59) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:77:32 + 91: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2), // (0x59) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 92: BranchIfSmallNeImmediate { + target: 94, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 93: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 94: BranchIfSmallNeImmediate { + target: 96, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 95: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + }, + // at: ready_valid.rs:98:5 + 96: Copy { + dest: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + src: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:116:5 + 97: Copy { + dest: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 98: IsNonZeroDestIsSmall { + dest: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 99: CmpNe { + dest: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + rhs: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:141:5 + 100: BranchIfZero { + target: 102, + value: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:142:9 + 101: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:146:5 + 102: BranchIfZero { + target: 107, + value: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:148:9 + 103: BranchIfZero { + target: 105, + value: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:149:13 + 104: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:148:9 + 105: BranchIfNonZero { + target: 107, + value: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:151:13 + 106: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(61), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:118:30 + 107: BranchIfSmallNeImmediate { + target: 109, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + 108: Copy { + dest: StatePartIndex(42), // (0x2c) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(5), // (0x2c) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:118:5 + 109: Copy { + dest: StatePartIndex(18), // (0x2c) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + src: StatePartIndex(42), // (0x2c) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + }, + // at: ready_valid.rs:84:31 + 110: BranchIfSmallZero { + target: 115, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 111: BranchIfSmallNonZero { + target: 114, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 112: Copy { + dest: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + src: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + }, + 113: Branch { + target: 115, + }, + 114: Copy { + dest: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:86:25 + 115: BranchIfSmallZero { + target: 120, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 116: BranchIfSmallNonZero { + target: 119, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 117: Copy { + dest: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + src: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + }, + 118: Branch { + target: 120, + }, + 119: Copy { + dest: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:88:26 + 120: BranchIfSmallZero { + target: 125, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 121: BranchIfSmallNonZero { + target: 124, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 122: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + }, + 123: Branch { + target: 125, + }, + 124: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 125: BranchIfSmallZero { + target: 126, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 126: BranchIfSmallZero { + target: 134, + value: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 127: CopySmall { + dest: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(11), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + }, + 128: CopySmall { + dest: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 129: Copy { + dest: StatePartIndex(20), // (0x2c) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(18), // (0x2c) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + }, + 130: Copy { + dest: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + }, + 131: BranchIfSmallZero { + target: 134, + value: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 132: BranchIfZero { + target: 134, + value: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 133: MemoryWriteUInt { + value: StatePartIndex(20), // (0x2c) SlotDebugData { name: "", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 4>, + // data: [ + // // len = 0x4 + // [0x0]: 0x2c, + // [0x1]: 0x29, + // [0x2]: 0x2a, + // [0x3]: 0x2b, + // ], + // }) (), + addr: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<2> }, + stride: 8, + start: 0, + width: 8, + }, + 134: XorSmallImmediate { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 135: XorSmallImmediate { + dest: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:84:31 + 136: XorSmallImmediate { + dest: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:64:1 + 137: Return, + ], + .. + }, + pc: 137, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array, 4>, + data: [ + // len = 0x4 + [0x0]: 0x2c, + [0x1]: 0x29, + [0x2]: 0x2a, + [0x3]: 0x2b, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 1, + 1, + 1, + 0, + 0, + 1, + 1, + 1, + 0, + 0, + 0, + 1, + 0, + 1, + 1, + 0, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 89, + 0, + 89, + 44, + 83, + 0, + 83, + 41, + 4, + 1, + 1, + 0, + 41, + 1, + 0, + 0, + 44, + 1, + 44, + 1, + 1, + 1, + 0, + 1, + 1, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 1, + 1, + 1, + 44, + 0, + 0, + 1, + 1, + 41, + 1, + 82, + 83, + 83, + 83, + 0, + 0, + 0, + 3, + 0, + 0, + 0, + 2, + 2, + 0, + 2, + 2, + 4, + 4, + 0, + 0, + 0, + 0, + 0, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.clk, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.rst, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.ready, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.ready, + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "queue", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "inp", + child: TraceBundle { + name: "inp", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(2), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(3), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(4), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceBundle { + name: "out", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(5), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(6), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(7), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + TraceModuleIO { + name: "count", + child: TraceUInt { + location: TraceScalarId(8), + name: "count", + ty: UInt<3>, + flow: Sink, + }, + ty: UInt<3>, + flow: Sink, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 4, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + }, + ], + array_type: Array, 4>, + }, + TraceReg { + name: "inp_index_reg", + child: TraceUInt { + location: TraceScalarId(18), + name: "inp_index_reg", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + TraceReg { + name: "out_index_reg", + child: TraceUInt { + location: TraceScalarId(19), + name: "out_index_reg", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + TraceReg { + name: "maybe_full_reg", + child: TraceBool { + location: TraceScalarId(20), + name: "maybe_full_reg", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "inp_firing", + child: TraceBool { + location: TraceScalarId(21), + name: "inp_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(22), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "out_firing", + child: TraceBool { + location: TraceScalarId(23), + name: "out_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(24), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "indexes_equal", + child: TraceBool { + location: TraceScalarId(25), + name: "indexes_equal", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "empty", + child: TraceBool { + location: TraceScalarId(26), + name: "empty", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "full", + child: TraceBool { + location: TraceScalarId(27), + name: "full", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "unwrap_or_else_out", + child: TraceUInt { + location: TraceScalarId(28), + name: "unwrap_or_else_out", + ty: UInt<8>, + flow: Duplex, + }, + ty: UInt<8>, + }, + TraceWire { + name: "count_lower", + child: TraceUInt { + location: TraceScalarId(29), + name: "count_lower", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSyncReset { + index: StatePartIndex(1), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<8>, + }, + state: 0x2c, + last_state: 0x2c, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigBool { + index: StatePartIndex(3), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(5), + kind: EnumDiscriminant { + index: StatePartIndex(1), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(9), + ty: UInt<8>, + }, + state: 0x29, + last_state: 0x29, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigBool { + index: StatePartIndex(7), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigUInt { + index: StatePartIndex(10), + ty: UInt<3>, + }, + state: 0x4, + last_state: 0x4, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigUInt { + index: StatePartIndex(11), + ty: UInt<2>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigBool { + index: StatePartIndex(12), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigClock { + index: StatePartIndex(13), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(12), + kind: BigUInt { + index: StatePartIndex(14), + ty: UInt<8>, + }, + state: 0x29, + last_state: 0x29, + }, + SimTrace { + id: TraceScalarId(13), + kind: BigUInt { + index: StatePartIndex(15), + ty: UInt<2>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigBool { + index: StatePartIndex(16), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(15), + kind: BigClock { + index: StatePartIndex(17), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(16), + kind: BigUInt { + index: StatePartIndex(18), + ty: UInt<8>, + }, + state: 0x2c, + last_state: 0x2c, + }, + SimTrace { + id: TraceScalarId(17), + kind: BigBool { + index: StatePartIndex(19), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigUInt { + index: StatePartIndex(22), + ty: UInt<2>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigUInt { + index: StatePartIndex(25), + ty: UInt<2>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(20), + kind: BigBool { + index: StatePartIndex(27), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(21), + kind: BigBool { + index: StatePartIndex(30), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(22), + kind: BigBool { + index: StatePartIndex(31), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(23), + kind: BigBool { + index: StatePartIndex(32), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(24), + kind: BigBool { + index: StatePartIndex(33), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(25), + kind: BigBool { + index: StatePartIndex(34), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(26), + kind: BigBool { + index: StatePartIndex(36), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(27), + kind: BigBool { + index: StatePartIndex(39), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(28), + kind: BigUInt { + index: StatePartIndex(42), + ty: UInt<8>, + }, + state: 0x2c, + last_state: 0x2c, + }, + SimTrace { + id: TraceScalarId(29), + kind: BigUInt { + index: StatePartIndex(68), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 4, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + }, + ], + array_type: Array, 4>, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [ + StatePartIndex(3), + StatePartIndex(8), + StatePartIndex(15), + ], + event_queue: EventQueue(EventQueueData { + instant: 100 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_4_true_false.vcd b/crates/fayalite/tests/sim/expected/queue_4_true_false.vcd new file mode 100644 index 0000000..842a353 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/queue_4_true_false.vcd @@ -0,0 +1,1993 @@ +$timescale 1 ps $end +$scope module queue $end +$scope struct cd $end +$var wire 1 11z(a clk $end +$var wire 1 q1t|f rst $end +$upscope $end +$scope struct inp $end +$scope struct data $end +$var string 1 j|a-9 \$tag $end +$var wire 8 pjN&T HdlSome $end +$upscope $end +$var wire 1 *x8M* ready $end +$upscope $end +$scope struct out $end +$scope struct data $end +$var string 1 'Aa8} \$tag $end +$var wire 8 1b%.O HdlSome $end +$upscope $end +$var wire 1 vZD*c ready $end +$upscope $end +$var wire 3 rf7Xh count $end +$scope struct mem $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 8 (.Juw mem $end +$upscope $end +$scope struct \[1] $end +$var reg 8 5F$iE mem $end +$upscope $end +$scope struct \[2] $end +$var reg 8 !BEt5 mem $end +$upscope $end +$scope struct \[3] $end +$var reg 8 C7]kZ mem $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var wire 2 K]Dkr addr $end +$var wire 1 P|=HX en $end +$var wire 1 z+ft% clk $end +$var wire 8 m+9ec data $end +$upscope $end +$scope struct w1 $end +$var wire 2 8Oa@o addr $end +$var wire 1 VaM[2 en $end +$var wire 1 aH[{] clk $end +$var wire 8 8|1uZ data $end +$var wire 1 DYq.y mask $end +$upscope $end +$upscope $end +$var reg 2 Xk?#v inp_index_reg $end +$var reg 2 p19yW out_index_reg $end +$var reg 1 kEQiI maybe_full_reg $end +$var wire 1 *gdL1 inp_firing $end +$var wire 1 ;HWUJ firing $end +$var wire 1 Ph#@^ out_firing $end +$var wire 1 ;HWUJ" firing_2 $end +$var wire 1 i[~ { + len: 18, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 70, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count", + ty: UInt<3>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::indexes_equal", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::empty", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::full", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count_lower", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 1, + debug_data: [ + (), + ], + layout_data: [ + MemoryData { + array_type: Array, 4>, + data: [ + // len = 0x4 + [0x0]: 0x00, + [0x1]: 0x00, + [0x2]: 0x00, + [0x3]: 0x00, + ], + }, + ], + .. + }, + }, + insns: [ + // at: ready_valid.rs:64:1 + 0: SubU { + dest: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + dest_width: 3, + }, + 1: CastToUInt { + dest: StatePartIndex(68), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + // at: ready_valid.rs:178:13 + 2: Copy { + dest: StatePartIndex(66), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<2> }, + src: StatePartIndex(68), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 3: CastToUInt { + dest: StatePartIndex(69), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(66), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<2> }, + dest_width: 3, + }, + 4: Const { + dest: StatePartIndex(63), // (0x4) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x4, + }, + 5: CastToUInt { + dest: StatePartIndex(64), // (0x4) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(63), // (0x4) SlotDebugData { name: "", ty: UInt<64> }, + dest_width: 3, + }, + 6: Const { + dest: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + value: 0x0, + }, + 7: CastToUInt { + dest: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 2, + }, + 8: CastToUInt { + dest: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 3, + }, + 9: Const { + dest: StatePartIndex(54), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x3, + }, + 10: CmpEq { + dest: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(54), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + }, + 11: CmpEq { + dest: StatePartIndex(60), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(54), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + }, + 12: Const { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 13: Add { + dest: StatePartIndex(58), // (0x2) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 14: CastToUInt { + dest: StatePartIndex(59), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(58), // (0x2) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 15: Add { + dest: StatePartIndex(61), // (0x2) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 16: CastToUInt { + dest: StatePartIndex(62), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(61), // (0x2) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 17: Const { + dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:118:30 + 18: Copy { + dest: StatePartIndex(42), // (0x2c) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:117:5 + 19: Copy { + dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:115:5 + 20: Copy { + dest: StatePartIndex(15), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<2> }, + src: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:114:5 + 21: Copy { + dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:64:1 + 22: Const { + dest: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + value: 0x1, + }, + // at: ready_valid.rs:113:5 + 23: Copy { + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:119:5 + 24: Copy { + dest: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:112:5 + 25: Copy { + dest: StatePartIndex(11), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<2> }, + src: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 26: NotU { + dest: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + width: 1, + }, + 27: CmpEq { + dest: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:104:5 + 28: Copy { + dest: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + src: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 29: And { + dest: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:107:5 + 30: Copy { + dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + src: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 31: NotU { + dest: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + width: 1, + }, + 32: And { + dest: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:110:5 + 33: Copy { + dest: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + src: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 34: NotU { + dest: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + width: 1, + }, + // at: ready_valid.rs:121:5 + 35: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:124:9 + 36: BranchIfZero { + target: 38, + value: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:125:13 + 37: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:166:5 + 38: BranchIfZero { + target: 43, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 39: BranchIfZero { + target: 41, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:169:13 + 40: Copy { + dest: StatePartIndex(10), // (0x4) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<3> }, + src: StatePartIndex(64), // (0x4) SlotDebugData { name: "", ty: UInt<3> }, + }, + // at: ready_valid.rs:168:9 + 41: BranchIfNonZero { + target: 43, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:171:13 + 42: Copy { + dest: StatePartIndex(10), // (0x4) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<3> }, + src: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + }, + // at: ready_valid.rs:166:5 + 43: BranchIfNonZero { + target: 45, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:182:13 + 44: Copy { + dest: StatePartIndex(10), // (0x4) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<3> }, + src: StatePartIndex(69), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + }, + // at: ready_valid.rs:88:26 + 45: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 46: Const { + dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, + }, + // at: ready_valid.rs:86:25 + 47: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:84:31 + 48: IsNonZeroDestIsSmall { + dest: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.rst", ty: SyncReset }, + }, + 49: IsNonZeroDestIsSmall { + dest: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + 50: AndSmall { + dest: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 51: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 52: Const { + dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + value: 0x0, + }, + // at: ready_valid.rs:91:19 + 53: CastBigToArrayIndex { + dest: StatePartIndex(11), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(15), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<2> }, + }, + 54: IsNonZeroDestIsSmall { + dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + }, + 55: AndSmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 56: CastBigToArrayIndex { + dest: StatePartIndex(6), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(11), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<2> }, + }, + 57: IsNonZeroDestIsSmall { + dest: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + }, + 58: BranchIfSmallZero { + target: 61, + value: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 59: MemoryReadUInt { + dest: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 4>, + // data: [ + // // len = 0x4 + // [0x0]: 0x2c, + // [0x1]: 0x29, + // [0x2]: 0x2a, + // [0x3]: 0x2b, + // ], + // }) (), + addr: StatePartIndex(6), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + stride: 8, + start: 0, + width: 8, + }, + 60: Branch { + target: 62, + }, + 61: Const { + dest: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:64:1 + 62: Copy { + dest: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 63: Copy { + dest: StatePartIndex(47), // (0x29) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + }, + 64: Shl { + dest: StatePartIndex(49), // (0x52) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(47), // (0x29) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 1, + }, + 65: Or { + dest: StatePartIndex(50), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(49), // (0x52) SlotDebugData { name: "", ty: UInt<9> }, + }, + 66: CastToUInt { + dest: StatePartIndex(51), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(50), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + dest_width: 9, + }, + 67: Copy { + dest: StatePartIndex(52), // (0x53) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(51), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: ready_valid.rs:130:5 + 68: BranchIfZero { + target: 70, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:131:9 + 69: Copy { + dest: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(52), // (0x53) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:130:5 + 70: BranchIfNonZero { + target: 72, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:134:13 + 71: Copy { + dest: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(2), // (0x59) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:91:19 + 72: IsNonZeroDestIsSmall { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + }, + 73: AndSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 74: Copy { + dest: StatePartIndex(8), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 75: SliceInt { + dest: StatePartIndex(9), // (0x29) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(8), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:79:32 + 76: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 77: BranchIfSmallNeImmediate { + target: 79, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 78: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 79: BranchIfSmallNeImmediate { + target: 81, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 80: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:101:5 + 81: Copy { + dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + src: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:156:5 + 82: BranchIfZero { + target: 87, + value: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:158:9 + 83: BranchIfZero { + target: 85, + value: StatePartIndex(60), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:159:13 + 84: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:158:9 + 85: BranchIfNonZero { + target: 87, + value: StatePartIndex(60), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:161:13 + 86: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(62), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 87: Copy { + dest: StatePartIndex(4), // (0x59) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(2), // (0x59) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 88: SliceInt { + dest: StatePartIndex(5), // (0x2c) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(4), // (0x59) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:77:32 + 89: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2), // (0x59) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 90: BranchIfSmallNeImmediate { + target: 92, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 91: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 92: BranchIfSmallNeImmediate { + target: 94, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 93: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + }, + // at: ready_valid.rs:98:5 + 94: Copy { + dest: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + src: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:116:5 + 95: Copy { + dest: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 96: IsNonZeroDestIsSmall { + dest: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 97: CmpNe { + dest: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + rhs: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:141:5 + 98: BranchIfZero { + target: 100, + value: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:142:9 + 99: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:146:5 + 100: BranchIfZero { + target: 105, + value: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:148:9 + 101: BranchIfZero { + target: 103, + value: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:149:13 + 102: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:148:9 + 103: BranchIfNonZero { + target: 105, + value: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:151:13 + 104: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(59), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:118:30 + 105: BranchIfSmallNeImmediate { + target: 107, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + 106: Copy { + dest: StatePartIndex(42), // (0x2c) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(5), // (0x2c) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:118:5 + 107: Copy { + dest: StatePartIndex(18), // (0x2c) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + src: StatePartIndex(42), // (0x2c) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + }, + // at: ready_valid.rs:84:31 + 108: BranchIfSmallZero { + target: 113, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 109: BranchIfSmallNonZero { + target: 112, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 110: Copy { + dest: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + src: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + }, + 111: Branch { + target: 113, + }, + 112: Copy { + dest: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:86:25 + 113: BranchIfSmallZero { + target: 118, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 114: BranchIfSmallNonZero { + target: 117, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 115: Copy { + dest: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + src: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + }, + 116: Branch { + target: 118, + }, + 117: Copy { + dest: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:88:26 + 118: BranchIfSmallZero { + target: 123, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 119: BranchIfSmallNonZero { + target: 122, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 120: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + }, + 121: Branch { + target: 123, + }, + 122: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 123: BranchIfSmallZero { + target: 124, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 124: BranchIfSmallZero { + target: 132, + value: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 125: CopySmall { + dest: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(11), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + }, + 126: CopySmall { + dest: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 127: Copy { + dest: StatePartIndex(20), // (0x2c) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(18), // (0x2c) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + }, + 128: Copy { + dest: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + }, + 129: BranchIfSmallZero { + target: 132, + value: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 130: BranchIfZero { + target: 132, + value: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 131: MemoryWriteUInt { + value: StatePartIndex(20), // (0x2c) SlotDebugData { name: "", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 4>, + // data: [ + // // len = 0x4 + // [0x0]: 0x2c, + // [0x1]: 0x29, + // [0x2]: 0x2a, + // [0x3]: 0x2b, + // ], + // }) (), + addr: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<2> }, + stride: 8, + start: 0, + width: 8, + }, + 132: XorSmallImmediate { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 133: XorSmallImmediate { + dest: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:84:31 + 134: XorSmallImmediate { + dest: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:64:1 + 135: Return, + ], + .. + }, + pc: 135, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array, 4>, + data: [ + // len = 0x4 + [0x0]: 0x2c, + [0x1]: 0x29, + [0x2]: 0x2a, + [0x3]: 0x2b, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 1, + 1, + 1, + 0, + 0, + 1, + 1, + 1, + 0, + 0, + 0, + 1, + 0, + 1, + 1, + 0, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 89, + 0, + 89, + 44, + 83, + 0, + 83, + 41, + 4, + 1, + 1, + 0, + 41, + 1, + 0, + 0, + 44, + 1, + 44, + 1, + 1, + 1, + 0, + 1, + 1, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 1, + 1, + 1, + 44, + 0, + 0, + 1, + 1, + 41, + 1, + 82, + 83, + 83, + 83, + 0, + 3, + 0, + 0, + 0, + 2, + 2, + 0, + 2, + 2, + 4, + 4, + 0, + 0, + 0, + 0, + 0, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.clk, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.rst, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.ready, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.ready, + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "queue", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "inp", + child: TraceBundle { + name: "inp", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(2), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(3), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(4), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceBundle { + name: "out", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(5), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(6), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(7), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + TraceModuleIO { + name: "count", + child: TraceUInt { + location: TraceScalarId(8), + name: "count", + ty: UInt<3>, + flow: Sink, + }, + ty: UInt<3>, + flow: Sink, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 4, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + }, + ], + array_type: Array, 4>, + }, + TraceReg { + name: "inp_index_reg", + child: TraceUInt { + location: TraceScalarId(18), + name: "inp_index_reg", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + TraceReg { + name: "out_index_reg", + child: TraceUInt { + location: TraceScalarId(19), + name: "out_index_reg", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + TraceReg { + name: "maybe_full_reg", + child: TraceBool { + location: TraceScalarId(20), + name: "maybe_full_reg", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "inp_firing", + child: TraceBool { + location: TraceScalarId(21), + name: "inp_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(22), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "out_firing", + child: TraceBool { + location: TraceScalarId(23), + name: "out_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(24), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "indexes_equal", + child: TraceBool { + location: TraceScalarId(25), + name: "indexes_equal", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "empty", + child: TraceBool { + location: TraceScalarId(26), + name: "empty", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "full", + child: TraceBool { + location: TraceScalarId(27), + name: "full", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "unwrap_or_else_out", + child: TraceUInt { + location: TraceScalarId(28), + name: "unwrap_or_else_out", + ty: UInt<8>, + flow: Duplex, + }, + ty: UInt<8>, + }, + TraceWire { + name: "count_lower", + child: TraceUInt { + location: TraceScalarId(29), + name: "count_lower", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSyncReset { + index: StatePartIndex(1), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<8>, + }, + state: 0x2c, + last_state: 0x2c, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigBool { + index: StatePartIndex(3), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(5), + kind: EnumDiscriminant { + index: StatePartIndex(1), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(9), + ty: UInt<8>, + }, + state: 0x29, + last_state: 0x29, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigBool { + index: StatePartIndex(7), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigUInt { + index: StatePartIndex(10), + ty: UInt<3>, + }, + state: 0x4, + last_state: 0x4, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigUInt { + index: StatePartIndex(11), + ty: UInt<2>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigBool { + index: StatePartIndex(12), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigClock { + index: StatePartIndex(13), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(12), + kind: BigUInt { + index: StatePartIndex(14), + ty: UInt<8>, + }, + state: 0x29, + last_state: 0x29, + }, + SimTrace { + id: TraceScalarId(13), + kind: BigUInt { + index: StatePartIndex(15), + ty: UInt<2>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigBool { + index: StatePartIndex(16), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(15), + kind: BigClock { + index: StatePartIndex(17), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(16), + kind: BigUInt { + index: StatePartIndex(18), + ty: UInt<8>, + }, + state: 0x2c, + last_state: 0x2c, + }, + SimTrace { + id: TraceScalarId(17), + kind: BigBool { + index: StatePartIndex(19), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigUInt { + index: StatePartIndex(22), + ty: UInt<2>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigUInt { + index: StatePartIndex(25), + ty: UInt<2>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(20), + kind: BigBool { + index: StatePartIndex(27), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(21), + kind: BigBool { + index: StatePartIndex(30), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(22), + kind: BigBool { + index: StatePartIndex(31), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(23), + kind: BigBool { + index: StatePartIndex(32), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(24), + kind: BigBool { + index: StatePartIndex(33), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(25), + kind: BigBool { + index: StatePartIndex(34), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(26), + kind: BigBool { + index: StatePartIndex(36), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(27), + kind: BigBool { + index: StatePartIndex(39), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(28), + kind: BigUInt { + index: StatePartIndex(42), + ty: UInt<8>, + }, + state: 0x2c, + last_state: 0x2c, + }, + SimTrace { + id: TraceScalarId(29), + kind: BigUInt { + index: StatePartIndex(66), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 4, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + }, + ], + array_type: Array, 4>, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [ + StatePartIndex(3), + StatePartIndex(8), + StatePartIndex(15), + ], + event_queue: EventQueue(EventQueueData { + instant: 100 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_4_true_true.vcd b/crates/fayalite/tests/sim/expected/queue_4_true_true.vcd new file mode 100644 index 0000000..f4a2232 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/queue_4_true_true.vcd @@ -0,0 +1,1989 @@ +$timescale 1 ps $end +$scope module queue $end +$scope struct cd $end +$var wire 1 11z(a clk $end +$var wire 1 q1t|f rst $end +$upscope $end +$scope struct inp $end +$scope struct data $end +$var string 1 j|a-9 \$tag $end +$var wire 8 pjN&T HdlSome $end +$upscope $end +$var wire 1 *x8M* ready $end +$upscope $end +$scope struct out $end +$scope struct data $end +$var string 1 'Aa8} \$tag $end +$var wire 8 1b%.O HdlSome $end +$upscope $end +$var wire 1 vZD*c ready $end +$upscope $end +$var wire 3 rf7Xh count $end +$scope struct mem $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 8 (.Juw mem $end +$upscope $end +$scope struct \[1] $end +$var reg 8 5F$iE mem $end +$upscope $end +$scope struct \[2] $end +$var reg 8 !BEt5 mem $end +$upscope $end +$scope struct \[3] $end +$var reg 8 C7]kZ mem $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var wire 2 K]Dkr addr $end +$var wire 1 P|=HX en $end +$var wire 1 z+ft% clk $end +$var wire 8 m+9ec data $end +$upscope $end +$scope struct w1 $end +$var wire 2 8Oa@o addr $end +$var wire 1 VaM[2 en $end +$var wire 1 aH[{] clk $end +$var wire 8 8|1uZ data $end +$var wire 1 DYq.y mask $end +$upscope $end +$upscope $end +$var reg 2 Xk?#v inp_index_reg $end +$var reg 2 p19yW out_index_reg $end +$var reg 1 kEQiI maybe_full_reg $end +$var wire 1 *gdL1 inp_firing $end +$var wire 1 ;HWUJ firing $end +$var wire 1 Ph#@^ out_firing $end +$var wire 1 ;HWUJ" firing_2 $end +$var wire 1 i[~(47), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4", ty: Bool }, width: 1, }, - // at: module-XXXXXXXXXX.rs:8:1 - 3: Copy { - dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4$next", ty: Bool }, - src: StatePartIndex(52), // (0x1) SlotDebugData { name: "", ty: Bool }, - }, // at: module-XXXXXXXXXX.rs:7:1 - 4: Copy { + 3: Copy { dest: StatePartIndex(6), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[4]", ty: Bool }, src: StatePartIndex(47), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:1:1 - 5: Copy { + 4: Copy { dest: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: Clock }, src: StatePartIndex(6), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[4]", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:10:1 - 6: Copy { + 5: Copy { dest: StatePartIndex(53), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_5.clk", ty: Clock }, src: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: Clock }, }, // at: module-XXXXXXXXXX.rs:9:1 - 7: Copy { + 6: Copy { dest: StatePartIndex(55), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_5: sw_reg).sw_reg::clk", ty: Clock }, src: StatePartIndex(53), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_5.clk", ty: Clock }, }, + // at: module-XXXXXXXXXX.rs:6:1 + 7: Copy { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4$next", ty: Bool }, + src: StatePartIndex(47), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:8:1 8: Copy { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4$next", ty: Bool }, + src: StatePartIndex(52), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:9:1 + 9: Copy { dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_3.o", ty: Bool }, src: StatePartIndex(45), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_3: sw_reg).sw_reg::o", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:11:1 - 9: Copy { + 10: Copy { dest: StatePartIndex(5), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[3]", ty: Bool }, src: StatePartIndex(43), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_3.o", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:1:1 - 10: Copy { + 11: Copy { dest: StatePartIndex(51), // (0x0) SlotDebugData { name: "", ty: Clock }, src: StatePartIndex(5), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[3]", ty: Bool }, }, - 11: NotU { + 12: NotU { dest: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2", ty: Bool }, width: 1, }, - // at: module-XXXXXXXXXX.rs:8:1 - 12: Copy { - dest: StatePartIndex(37), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2$next", ty: Bool }, - src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, - }, // at: module-XXXXXXXXXX.rs:7:1 13: Copy { dest: StatePartIndex(4), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[2]", ty: Bool }, @@ -383,241 +384,257 @@ Simulation { dest: StatePartIndex(44), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_3: sw_reg).sw_reg::clk", ty: Clock }, src: StatePartIndex(42), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_3.clk", ty: Clock }, }, + // at: module-XXXXXXXXXX.rs:6:1 17: Copy { + dest: StatePartIndex(37), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2$next", ty: Bool }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:8:1 + 18: Copy { + dest: StatePartIndex(37), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2$next", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:9:1 + 19: Copy { dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_1.o", ty: Bool }, src: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_1: sw_reg).sw_reg::o", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:11:1 - 18: Copy { + 20: Copy { dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[1]", ty: Bool }, src: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_1.o", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:1:1 - 19: Copy { + 21: Copy { dest: StatePartIndex(40), // (0x0) SlotDebugData { name: "", ty: Clock }, src: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[1]", ty: Bool }, }, - 20: NotU { + 22: NotU { dest: StatePartIndex(30), // (0x1) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(24), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0", ty: Bool }, width: 1, }, - // at: module-XXXXXXXXXX.rs:8:1 - 21: Copy { - dest: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0$next", ty: Bool }, - src: StatePartIndex(30), // (0x1) SlotDebugData { name: "", ty: Bool }, - }, // at: module-XXXXXXXXXX.rs:7:1 - 22: Copy { + 23: Copy { dest: StatePartIndex(2), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[0]", ty: Bool }, src: StatePartIndex(24), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:1:1 - 23: Copy { + 24: Copy { dest: StatePartIndex(35), // (0x0) SlotDebugData { name: "", ty: Clock }, src: StatePartIndex(2), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[0]", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:10:1 - 24: Copy { + 25: Copy { dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_1.clk", ty: Clock }, src: StatePartIndex(35), // (0x0) SlotDebugData { name: "", ty: Clock }, }, // at: module-XXXXXXXXXX.rs:9:1 - 25: Copy { + 26: Copy { dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_1: sw_reg).sw_reg::clk", ty: Clock }, src: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_1.clk", ty: Clock }, }, + // at: module-XXXXXXXXXX.rs:6:1 + 27: Copy { + dest: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0$next", ty: Bool }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:8:1 + 28: Copy { + dest: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0$next", ty: Bool }, + src: StatePartIndex(30), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, // at: module-XXXXXXXXXX.rs:1:1 - 26: Const { + 29: Const { dest: StatePartIndex(28), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, value: 0x0, }, - 27: Copy { + 30: Copy { dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: SyncReset }, src: StatePartIndex(28), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, }, - 28: Copy { + 31: Copy { dest: StatePartIndex(26), // (0x1) SlotDebugData { name: ".clk", ty: Clock }, src: StatePartIndex(0), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::clk", ty: Clock }, }, - 29: Copy { + 32: Copy { dest: StatePartIndex(27), // (0x0) SlotDebugData { name: ".rst", ty: SyncReset }, src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: SyncReset }, }, // at: module-XXXXXXXXXX.rs:6:1 - 30: IsNonZeroDestIsSmall { + 33: IsNonZeroDestIsSmall { dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(26), // (0x1) SlotDebugData { name: ".clk", ty: Clock }, }, - 31: AndSmall { + 34: AndSmall { dest: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, rhs: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:1:1 - 32: Copy { + 35: Copy { dest: StatePartIndex(38), // (0x0) SlotDebugData { name: ".clk", ty: Clock }, src: StatePartIndex(40), // (0x0) SlotDebugData { name: "", ty: Clock }, }, - 33: Copy { + 36: Copy { dest: StatePartIndex(39), // (0x0) SlotDebugData { name: ".rst", ty: SyncReset }, src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: SyncReset }, }, // at: module-XXXXXXXXXX.rs:6:1 - 34: IsNonZeroDestIsSmall { + 37: IsNonZeroDestIsSmall { dest: StatePartIndex(5), // (0x0 0) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(38), // (0x0) SlotDebugData { name: ".clk", ty: Clock }, }, - 35: AndSmall { + 38: AndSmall { dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, lhs: StatePartIndex(5), // (0x0 0) SlotDebugData { name: "", ty: Bool }, rhs: StatePartIndex(3), // (0x1 1) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:1:1 - 36: Copy { + 39: Copy { dest: StatePartIndex(49), // (0x0) SlotDebugData { name: ".clk", ty: Clock }, src: StatePartIndex(51), // (0x0) SlotDebugData { name: "", ty: Clock }, }, - 37: Copy { + 40: Copy { dest: StatePartIndex(50), // (0x0) SlotDebugData { name: ".rst", ty: SyncReset }, src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: SyncReset }, }, // at: module-XXXXXXXXXX.rs:6:1 - 38: IsNonZeroDestIsSmall { + 41: IsNonZeroDestIsSmall { dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(49), // (0x0) SlotDebugData { name: ".clk", ty: Clock }, }, - 39: AndSmall { + 42: AndSmall { dest: StatePartIndex(7), // (0x0 0) SlotDebugData { name: "", ty: Bool }, lhs: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, rhs: StatePartIndex(6), // (0x1 1) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:1:1 - 40: Copy { + 43: Copy { dest: StatePartIndex(21), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[5]", ty: Bool }, }, - 41: Shl { + 44: Shl { dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, lhs: StatePartIndex(21), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, rhs: 5, }, - 42: Copy { + 45: Copy { dest: StatePartIndex(18), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, src: StatePartIndex(6), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[4]", ty: Bool }, }, - 43: Shl { + 46: Shl { dest: StatePartIndex(19), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, lhs: StatePartIndex(18), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, rhs: 4, }, - 44: Copy { + 47: Copy { dest: StatePartIndex(15), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, src: StatePartIndex(5), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[3]", ty: Bool }, }, - 45: Shl { + 48: Shl { dest: StatePartIndex(16), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, lhs: StatePartIndex(15), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, rhs: 3, }, - 46: Copy { + 49: Copy { dest: StatePartIndex(12), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, src: StatePartIndex(4), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[2]", ty: Bool }, }, - 47: Shl { + 50: Shl { dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, lhs: StatePartIndex(12), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, rhs: 2, }, - 48: Copy { + 51: Copy { dest: StatePartIndex(9), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, src: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[1]", ty: Bool }, }, - 49: Shl { + 52: Shl { dest: StatePartIndex(10), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, lhs: StatePartIndex(9), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, rhs: 1, }, - 50: Copy { + 53: Copy { dest: StatePartIndex(8), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, src: StatePartIndex(2), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[0]", ty: Bool }, }, - 51: Or { + 54: Or { dest: StatePartIndex(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, lhs: StatePartIndex(8), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, rhs: StatePartIndex(10), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, }, - 52: Or { + 55: Or { dest: StatePartIndex(14), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, lhs: StatePartIndex(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, rhs: StatePartIndex(13), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, }, - 53: Or { + 56: Or { dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, lhs: StatePartIndex(14), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, rhs: StatePartIndex(16), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, }, - 54: Or { + 57: Or { dest: StatePartIndex(20), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, lhs: StatePartIndex(17), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, rhs: StatePartIndex(19), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, }, - 55: Or { + 58: Or { dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, lhs: StatePartIndex(20), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, rhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, }, // at: module-XXXXXXXXXX.rs:5:1 - 56: Copy { + 59: Copy { dest: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::o", ty: UInt<6> }, src: StatePartIndex(23), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, }, // at: module-XXXXXXXXXX.rs:6:1 - 57: BranchIfSmallZero { - target: 59, + 60: BranchIfSmallZero { + target: 62, value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 58: Copy { + 61: Copy { dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0", ty: Bool }, src: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0$next", ty: Bool }, }, - 59: BranchIfSmallZero { - target: 61, + 62: BranchIfSmallZero { + target: 64, value: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 60: Copy { + 63: Copy { dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2", ty: Bool }, src: StatePartIndex(37), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2$next", ty: Bool }, }, - 61: BranchIfSmallZero { - target: 63, + 64: BranchIfSmallZero { + target: 66, value: StatePartIndex(7), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 62: Copy { + 65: Copy { dest: StatePartIndex(47), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4", ty: Bool }, src: StatePartIndex(48), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4$next", ty: Bool }, }, - 63: XorSmallImmediate { + 66: XorSmallImmediate { dest: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, rhs: 0x1, }, - 64: XorSmallImmediate { + 67: XorSmallImmediate { dest: StatePartIndex(3), // (0x1 1) SlotDebugData { name: "", ty: Bool }, lhs: StatePartIndex(5), // (0x0 0) SlotDebugData { name: "", ty: Bool }, rhs: 0x1, }, - 65: XorSmallImmediate { + 68: XorSmallImmediate { dest: StatePartIndex(6), // (0x1 1) SlotDebugData { name: "", ty: Bool }, lhs: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, rhs: 0x1, }, // at: module-XXXXXXXXXX.rs:1:1 - 66: Return, + 69: Return, ], .. }, - pc: 66, + pc: 69, memory_write_log: [], memories: StatePart { value: [], diff --git a/crates/fayalite/tests/sim/expected/shift_register.txt b/crates/fayalite/tests/sim/expected/shift_register.txt index 7dcf26c..2e1b176 100644 --- a/crates/fayalite/tests/sim/expected/shift_register.txt +++ b/crates/fayalite/tests/sim/expected/shift_register.txt @@ -103,137 +103,156 @@ Simulation { dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::q", ty: Bool }, src: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool }, }, - // at: module-XXXXXXXXXX.rs:12:1 + // at: module-XXXXXXXXXX.rs:11:1 1: Copy { + dest: StatePartIndex(12), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool }, + src: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:12:1 + 2: Copy { dest: StatePartIndex(12), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool }, src: StatePartIndex(9), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool }, }, + // at: module-XXXXXXXXXX.rs:9:1 + 3: Copy { + dest: StatePartIndex(10), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool }, + src: StatePartIndex(9), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool }, + }, // at: module-XXXXXXXXXX.rs:10:1 - 2: Copy { + 4: Copy { dest: StatePartIndex(10), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool }, src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool }, }, + // at: module-XXXXXXXXXX.rs:7:1 + 5: Copy { + dest: StatePartIndex(8), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool }, + }, // at: module-XXXXXXXXXX.rs:8:1 - 3: Copy { + 6: Copy { dest: StatePartIndex(8), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool }, src: StatePartIndex(4), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool }, }, - // at: module-XXXXXXXXXX.rs:6:1 - 4: Copy { - dest: StatePartIndex(5), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool }, - src: StatePartIndex(2), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::d", ty: Bool }, - }, // at: module-XXXXXXXXXX.rs:5:1 - 5: IsNonZeroDestIsSmall { + 7: IsNonZeroDestIsSmall { dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst", ty: SyncReset }, }, - 6: IsNonZeroDestIsSmall { + 8: IsNonZeroDestIsSmall { dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(0), // (0x1) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk", ty: Clock }, }, - 7: AndSmall { + 9: AndSmall { dest: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, rhs: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, + 10: Copy { + dest: StatePartIndex(5), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool }, + src: StatePartIndex(4), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:6:1 + 11: Copy { + dest: StatePartIndex(5), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool }, + src: StatePartIndex(2), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::d", ty: Bool }, + }, // at: module-XXXXXXXXXX.rs:1:1 - 8: Const { + 12: Const { dest: StatePartIndex(6), // (0x0) SlotDebugData { name: "", ty: Bool }, value: 0x0, }, // at: module-XXXXXXXXXX.rs:5:1 - 9: BranchIfSmallZero { - target: 14, + 13: BranchIfSmallZero { + target: 18, value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 10: BranchIfSmallNonZero { - target: 13, + 14: BranchIfSmallNonZero { + target: 17, value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 11: Copy { + 15: Copy { dest: StatePartIndex(4), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool }, src: StatePartIndex(5), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool }, }, - 12: Branch { - target: 14, + 16: Branch { + target: 18, }, - 13: Copy { + 17: Copy { dest: StatePartIndex(4), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool }, src: StatePartIndex(6), // (0x0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:7:1 - 14: BranchIfSmallZero { - target: 19, + 18: BranchIfSmallZero { + target: 23, value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 15: BranchIfSmallNonZero { - target: 18, + 19: BranchIfSmallNonZero { + target: 22, value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 16: Copy { + 20: Copy { dest: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool }, src: StatePartIndex(8), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool }, }, - 17: Branch { - target: 19, + 21: Branch { + target: 23, }, - 18: Copy { + 22: Copy { dest: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool }, src: StatePartIndex(6), // (0x0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:9:1 - 19: BranchIfSmallZero { - target: 24, + 23: BranchIfSmallZero { + target: 28, value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 20: BranchIfSmallNonZero { - target: 23, + 24: BranchIfSmallNonZero { + target: 27, value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 21: Copy { + 25: Copy { dest: StatePartIndex(9), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool }, src: StatePartIndex(10), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool }, }, - 22: Branch { - target: 24, + 26: Branch { + target: 28, }, - 23: Copy { + 27: Copy { dest: StatePartIndex(9), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool }, src: StatePartIndex(6), // (0x0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:11:1 - 24: BranchIfSmallZero { - target: 29, + 28: BranchIfSmallZero { + target: 33, value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 25: BranchIfSmallNonZero { - target: 28, + 29: BranchIfSmallNonZero { + target: 32, value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 26: Copy { + 30: Copy { dest: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool }, src: StatePartIndex(12), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool }, }, - 27: Branch { - target: 29, + 31: Branch { + target: 33, }, - 28: Copy { + 32: Copy { dest: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool }, src: StatePartIndex(6), // (0x0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:5:1 - 29: XorSmallImmediate { + 33: XorSmallImmediate { dest: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, rhs: 0x1, }, // at: module-XXXXXXXXXX.rs:1:1 - 30: Return, + 34: Return, ], .. }, - pc: 30, + pc: 34, memory_write_log: [], memories: StatePart { value: [], diff --git a/crates/fayalite/tests/sim/expected/sim_only_connects.txt b/crates/fayalite/tests/sim/expected/sim_only_connects.txt index af41fe2..827f3cc 100644 --- a/crates/fayalite/tests/sim/expected/sim_only_connects.txt +++ b/crates/fayalite/tests/sim/expected/sim_only_connects.txt @@ -212,55 +212,55 @@ Simulation { dest: StatePartIndex(9), // (0x0) SlotDebugData { name: "", ty: Bool }, value: 0x0, }, - // at: module-XXXXXXXXXX.rs:17:1 - 7: Copy { - dest: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty$next", ty: Bool }, - src: StatePartIndex(9), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:16:1 - 8: CloneSimOnly { - dest: StatePartIndex(9), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1$next", ty: SimOnly>> }, - src: StatePartIndex(0), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::inp", ty: SimOnly>> }, - }, // at: module-XXXXXXXXXX.rs:12:1 - 9: CloneSimOnly { + 7: CloneSimOnly { dest: StatePartIndex(1), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::out1", ty: SimOnly>> }, src: StatePartIndex(8), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1", ty: SimOnly>> }, }, // at: module-XXXXXXXXXX.rs:13:1 - 10: BranchIfZero { - target: 12, + 8: BranchIfZero { + target: 10, value: StatePartIndex(6), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:15:1 - 11: CloneSimOnly { + 9: CloneSimOnly { dest: StatePartIndex(1), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::out1", ty: SimOnly>> }, src: StatePartIndex(0), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::inp", ty: SimOnly>> }, }, // at: module-XXXXXXXXXX.rs:11:1 - 12: CloneSimOnly { + 10: CloneSimOnly { dest: StatePartIndex(4), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.inp", ty: SimOnly>> }, src: StatePartIndex(8), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1", ty: SimOnly>> }, }, // at: module-XXXXXXXXXX.rs:13:1 - 13: BranchIfZero { - target: 15, + 11: BranchIfZero { + target: 13, value: StatePartIndex(6), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:14:1 - 14: CloneSimOnly { + 12: CloneSimOnly { dest: StatePartIndex(4), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.inp", ty: SimOnly>> }, src: StatePartIndex(0), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::inp", ty: SimOnly>> }, }, // at: module-XXXXXXXXXX.rs:10:1 - 15: Copy { + 13: Copy { dest: StatePartIndex(2), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.cd.clk", ty: Clock }, src: StatePartIndex(0), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::cd.clk", ty: Clock }, }, - 16: Copy { + 14: Copy { dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.cd.rst", ty: SyncReset }, src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::cd.rst", ty: SyncReset }, }, + // at: module-XXXXXXXXXX.rs:9:1 + 15: Copy { + dest: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty$next", ty: Bool }, + src: StatePartIndex(6), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:17:1 + 16: Copy { + dest: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty$next", ty: Bool }, + src: StatePartIndex(9), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, // at: module-XXXXXXXXXX.rs:1:1 17: Const { dest: StatePartIndex(8), // (0x1) SlotDebugData { name: "", ty: Bool }, @@ -280,91 +280,100 @@ Simulation { lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, rhs: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - // at: module-XXXXXXXXXX.rs:7:1 21: CloneSimOnly { + dest: StatePartIndex(9), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1$next", ty: SimOnly>> }, + src: StatePartIndex(8), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1", ty: SimOnly>> }, + }, + // at: module-XXXXXXXXXX.rs:16:1 + 22: CloneSimOnly { + dest: StatePartIndex(9), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1$next", ty: SimOnly>> }, + src: StatePartIndex(0), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::inp", ty: SimOnly>> }, + }, + // at: module-XXXXXXXXXX.rs:7:1 + 23: CloneSimOnly { dest: StatePartIndex(5), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.out", ty: SimOnly>> }, src: StatePartIndex(7), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects.helper1: sim_only_connects_helper).sim_only_connects_helper::out", ty: SimOnly>> }, }, // at: module-XXXXXXXXXX.rs:18:1 - 22: CloneSimOnly { + 24: CloneSimOnly { dest: StatePartIndex(2), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::out2", ty: SimOnly>> }, src: StatePartIndex(5), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.out", ty: SimOnly>> }, }, // at: module-XXXXXXXXXX.rs:21:1 - 23: CloneSimOnly { + 25: CloneSimOnly { dest: StatePartIndex(11), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper2.inp", ty: SimOnly>> }, src: StatePartIndex(2), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::out2", ty: SimOnly>> }, }, // at: module-XXXXXXXXXX.rs:19:1 - 24: CloneSimOnly { + 26: CloneSimOnly { dest: StatePartIndex(13), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects.helper2: sim_only_connects_helper).sim_only_connects_helper::inp", ty: SimOnly>> }, src: StatePartIndex(11), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper2.inp", ty: SimOnly>> }, }, // at: module-XXXXXXXXXX.rs:7:1 - 25: CloneSimOnly { + 27: CloneSimOnly { dest: StatePartIndex(6), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects.helper1: sim_only_connects_helper).sim_only_connects_helper::inp", ty: SimOnly>> }, src: StatePartIndex(4), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.inp", ty: SimOnly>> }, }, - 26: Copy { + 28: Copy { dest: StatePartIndex(4), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_only_connects.helper1: sim_only_connects_helper).sim_only_connects_helper::cd.clk", ty: Clock }, src: StatePartIndex(2), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.cd.clk", ty: Clock }, }, - 27: Copy { + 29: Copy { dest: StatePartIndex(5), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects.helper1: sim_only_connects_helper).sim_only_connects_helper::cd.rst", ty: SyncReset }, src: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.cd.rst", ty: SyncReset }, }, // at: module-XXXXXXXXXX.rs:8:1 - 28: BranchIfSmallZero { - target: 33, + 30: BranchIfSmallZero { + target: 35, value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 29: BranchIfSmallNonZero { - target: 32, + 31: BranchIfSmallNonZero { + target: 34, value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 30: CloneSimOnly { + 32: CloneSimOnly { dest: StatePartIndex(8), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1", ty: SimOnly>> }, src: StatePartIndex(9), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1$next", ty: SimOnly>> }, }, - 31: Branch { - target: 33, + 33: Branch { + target: 35, }, - 32: CloneSimOnly { + 34: CloneSimOnly { dest: StatePartIndex(8), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1", ty: SimOnly>> }, src: StatePartIndex(10), // ({}) SlotDebugData { name: "", ty: SimOnly>> }, }, // at: module-XXXXXXXXXX.rs:9:1 - 33: BranchIfSmallZero { - target: 38, + 35: BranchIfSmallZero { + target: 40, value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 34: BranchIfSmallNonZero { - target: 37, + 36: BranchIfSmallNonZero { + target: 39, value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 35: Copy { + 37: Copy { dest: StatePartIndex(6), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty", ty: Bool }, src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty$next", ty: Bool }, }, - 36: Branch { - target: 38, + 38: Branch { + target: 40, }, - 37: Copy { + 39: Copy { dest: StatePartIndex(6), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty", ty: Bool }, src: StatePartIndex(8), // (0x1) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:8:1 - 38: XorSmallImmediate { + 40: XorSmallImmediate { dest: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, rhs: 0x1, }, // at: module-XXXXXXXXXX.rs:1:1 - 39: Return, + 41: Return, ], .. }, - pc: 39, + pc: 41, memory_write_log: [], memories: StatePart { value: [],