crates/fayalite/tests/sim.rs

@@ -7,7 +7,7 @@ use fayalite::{
     prelude::*,
     reset::ResetType,
     sim::vcd::VcdWriterDecls,
-    util::RcWriter,
+    util::{RcWriter, ready_valid::queue},
 };
 use std::{collections::BTreeMap, num::NonZeroUsize, rc::Rc};
 
@@ -2565,3 +2565,279 @@ fn test_last_connect() {
         panic!();
     }
 }
+
+#[track_caller]
+#[hdl]
+fn test_queue_helper(
+    capacity: usize,
+    inp_ready_is_comb: bool,
+    out_valid_is_comb: bool,
+    expected_vcd: &str,
+    expected_sim_debug: &str,
+) {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let mut sim = Simulation::new(queue(
+        UInt::<8>::new_static(),
+        NonZeroUsize::new(capacity).expect("capacity should be non-zero"),
+        inp_ready_is_comb,
+        out_valid_is_comb,
+    ));
+    let writer = RcWriter::default();
+    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
+    struct DumpVcdOnDrop {
+        writer: Option<RcWriter>,
+    }
+    impl Drop for DumpVcdOnDrop {
+        fn drop(&mut self) {
+            if let Some(mut writer) = self.writer.take() {
+                let vcd = String::from_utf8(writer.take()).unwrap();
+                println!("####### VCD:\n{vcd}\n#######");
+            }
+        }
+    }
+    let mut writer = DumpVcdOnDrop {
+        writer: Some(writer),
+    };
+    sim.write_clock(sim.io().cd.clk, false);
+    sim.write_reset(sim.io().cd.rst, true);
+    let mut input_value = 0u8;
+    let mut expected_output_value = 0u8;
+    /// deterministic random numbers
+    fn rand(mut v: u32) -> bool {
+        // random 32-bit primes
+        v = v.wrapping_mul(0xF807B7EF).rotate_left(16);
+        v ^= 0xA1E24BBA; // random 32-bit constant
+        v = v.wrapping_mul(0xE9D30017).rotate_left(16);
+        v = v.wrapping_mul(0x3895AFFB).rotate_left(16);
+        v & 1 != 0
+    }
+    for cycle in 0..100u32 {
+        println!("cycle: {cycle}");
+        sim.write(
+            sim.io().inp.data,
+            if rand(cycle) {
+                #[hdl(sim)]
+                HdlSome(input_value)
+            } else {
+                #[hdl(sim)]
+                HdlNone()
+            },
+        );
+        sim.write_bool(sim.io().out.ready, rand(u32::MAX / 2 + cycle));
+        sim.advance_time(SimDuration::from_nanos(500));
+        if !sim.read_reset(sim.io().cd.rst) {
+            let inp_ready = sim.read_bool(sim.io().inp.ready);
+            if inp_ready {
+                #[hdl(sim)]
+                if let HdlSome(v) = sim.read(sim.io().inp.data) {
+                    println!("enqueued {v}, expected {input_value:#x}");
+                    assert_eq!(v.as_int(), input_value);
+                    input_value = input_value.wrapping_add(1);
+                }
+            }
+            let out_valid = #[hdl(sim)]
+            if let HdlSome(v) = sim.read(sim.io().out.data) {
+                if sim.read_bool(sim.io().out.ready) {
+                    println!("dequeued {v}, expected {expected_output_value:#x}");
+                    assert_eq!(v.as_int(), expected_output_value);
+                    expected_output_value = expected_output_value.wrapping_add(1);
+                }
+                true
+            } else {
+                false
+            };
+            assert!(inp_ready || out_valid, "queue isn't making progress");
+        }
+        sim.write_clock(sim.io().cd.clk, true);
+        sim.advance_time(SimDuration::from_nanos(500));
+        sim.write_clock(sim.io().cd.clk, false);
+        sim.write_reset(sim.io().cd.rst, false);
+    }
+    sim.flush_traces().unwrap();
+    let vcd = String::from_utf8(writer.writer.take().unwrap().take()).unwrap();
+    println!("####### VCD:\n{vcd}\n#######");
+    if vcd != expected_vcd {
+        panic!();
+    }
+    let sim_debug = format!("{sim:#?}");
+    println!("#######\n{sim_debug}\n#######");
+    if sim_debug != expected_sim_debug {
+        panic!();
+    }
+}
+
+#[test]
+fn test_queue_1_false_false() {
+    test_queue_helper(
+        1,
+        false,
+        false,
+        include_str!("sim/expected/queue_1_false_false.vcd"),
+        include_str!("sim/expected/queue_1_false_false.txt"),
+    );
+}
+
+#[test]
+fn test_queue_1_false_true() {
+    test_queue_helper(
+        1,
+        false,
+        true,
+        include_str!("sim/expected/queue_1_false_true.vcd"),
+        include_str!("sim/expected/queue_1_false_true.txt"),
+    );
+}
+
+#[test]
+fn test_queue_1_true_false() {
+    test_queue_helper(
+        1,
+        true,
+        false,
+        include_str!("sim/expected/queue_1_true_false.vcd"),
+        include_str!("sim/expected/queue_1_true_false.txt"),
+    );
+}
+
+#[test]
+fn test_queue_1_true_true() {
+    test_queue_helper(
+        1,
+        true,
+        true,
+        include_str!("sim/expected/queue_1_true_true.vcd"),
+        include_str!("sim/expected/queue_1_true_true.txt"),
+    );
+}
+
+#[test]
+fn test_queue_2_false_false() {
+    test_queue_helper(
+        2,
+        false,
+        false,
+        include_str!("sim/expected/queue_2_false_false.vcd"),
+        include_str!("sim/expected/queue_2_false_false.txt"),
+    );
+}
+
+#[test]
+fn test_queue_2_false_true() {
+    test_queue_helper(
+        2,
+        false,
+        true,
+        include_str!("sim/expected/queue_2_false_true.vcd"),
+        include_str!("sim/expected/queue_2_false_true.txt"),
+    );
+}
+
+#[test]
+fn test_queue_2_true_false() {
+    test_queue_helper(
+        2,
+        true,
+        false,
+        include_str!("sim/expected/queue_2_true_false.vcd"),
+        include_str!("sim/expected/queue_2_true_false.txt"),
+    );
+}
+
+#[test]
+fn test_queue_2_true_true() {
+    test_queue_helper(
+        2,
+        true,
+        true,
+        include_str!("sim/expected/queue_2_true_true.vcd"),
+        include_str!("sim/expected/queue_2_true_true.txt"),
+    );
+}
+
+#[test]
+fn test_queue_3_false_false() {
+    test_queue_helper(
+        3,
+        false,
+        false,
+        include_str!("sim/expected/queue_3_false_false.vcd"),
+        include_str!("sim/expected/queue_3_false_false.txt"),
+    );
+}
+
+#[test]
+fn test_queue_3_false_true() {
+    test_queue_helper(
+        3,
+        false,
+        true,
+        include_str!("sim/expected/queue_3_false_true.vcd"),
+        include_str!("sim/expected/queue_3_false_true.txt"),
+    );
+}
+
+#[test]
+fn test_queue_3_true_false() {
+    test_queue_helper(
+        3,
+        true,
+        false,
+        include_str!("sim/expected/queue_3_true_false.vcd"),
+        include_str!("sim/expected/queue_3_true_false.txt"),
+    );
+}
+
+#[test]
+fn test_queue_3_true_true() {
+    test_queue_helper(
+        3,
+        true,
+        true,
+        include_str!("sim/expected/queue_3_true_true.vcd"),
+        include_str!("sim/expected/queue_3_true_true.txt"),
+    );
+}
+
+#[test]
+fn test_queue_4_false_false() {
+    test_queue_helper(
+        4,
+        false,
+        false,
+        include_str!("sim/expected/queue_4_false_false.vcd"),
+        include_str!("sim/expected/queue_4_false_false.txt"),
+    );
+}
+
+#[test]
+fn test_queue_4_false_true() {
+    test_queue_helper(
+        4,
+        false,
+        true,
+        include_str!("sim/expected/queue_4_false_true.vcd"),
+        include_str!("sim/expected/queue_4_false_true.txt"),
+    );
+}
+
+#[test]
+fn test_queue_4_true_false() {
+    test_queue_helper(
+        4,
+        true,
+        false,
+        include_str!("sim/expected/queue_4_true_false.vcd"),
+        include_str!("sim/expected/queue_4_true_false.txt"),
+    );
+}
+
+#[test]
+fn test_queue_4_true_true() {
+    test_queue_helper(
+        4,
+        true,
+        true,
+        include_str!("sim/expected/queue_4_true_true.vcd"),
+        include_str!("sim/expected/queue_4_true_true.txt"),
+    );
+}