Initial work on representing HDL and formal verification in Rocq. #56

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programmerjake merged 3 commits from cesar/fayalite:rocq_hdl into master 2025-12-09 16:34:36 +00:00

3 commits

Author SHA1 Message Date
e4210a672f
Check copyright header in Rocq files.
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If we ever add Verilog files, we can "or" both results, I guess.
2025-12-09 07:45:35 -03:00
e54558d848
Demonstrates state with multiple variables and hidden state.
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2025-12-08 22:00:49 -03:00
46f3519c76
Demonstrate a preliminary mapping from HDL to Rocq.
Starts with a very simple example, including a proof by induction.
2025-12-08 19:32:05 -03:00