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change memory write latency to NonZeroUsize to match read latency being usize

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This commit is contained in:
Jacob Lifshay 2024-12-09 23:01:40 -08:00
parent 9654167ca3
commit cd0dd7b7ee
Signed by: programmerjake
SSH key fingerprint: SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
1 changed files with 8 additions and 8 deletions
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16
crates/fayalite/src/memory.rs
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@ -22,7 +22,7 @@ use std::{
fmt, fmt,
hash::{Hash, Hasher}, hash::{Hash, Hasher},
marker::PhantomData, marker::PhantomData,
num::NonZeroU32, num::NonZeroUsize,
rc::Rc, rc::Rc,
}; };
@ -478,7 +478,7 @@ struct MemImpl<Element: Type, Len: Size, P> {
initial_value: Option<Interned<BitSlice>>, initial_value: Option<Interned<BitSlice>>,
ports: P, ports: P,
read_latency: usize, read_latency: usize,
write_latency: NonZeroU32, write_latency: NonZeroUsize,
read_under_write: ReadUnderWrite, read_under_write: ReadUnderWrite,
port_annotations: Interned<[TargetedAnnotation]>, port_annotations: Interned<[TargetedAnnotation]>,
mem_annotations: Interned<[Annotation]>, mem_annotations: Interned<[Annotation]>,
@ -562,7 +562,7 @@ impl<Element: Type, Len: Size> Mem<Element, Len> {
initial_value: Option<Interned<BitSlice>>, initial_value: Option<Interned<BitSlice>>,
ports: Interned<[MemPort<DynPortType>]>, ports: Interned<[MemPort<DynPortType>]>,
read_latency: usize, read_latency: usize,
write_latency: NonZeroU32, write_latency: NonZeroUsize,
read_under_write: ReadUnderWrite, read_under_write: ReadUnderWrite,
port_annotations: Interned<[TargetedAnnotation]>, port_annotations: Interned<[TargetedAnnotation]>,
mem_annotations: Interned<[Annotation]>, mem_annotations: Interned<[Annotation]>,
@ -645,7 +645,7 @@ impl<Element: Type, Len: Size> Mem<Element, Len> {
pub fn read_latency(self) -> usize { pub fn read_latency(self) -> usize {
self.0.read_latency self.0.read_latency
} }
pub fn write_latency(self) -> NonZeroU32 { pub fn write_latency(self) -> NonZeroUsize {
self.0.write_latency self.0.write_latency
} }
pub fn read_under_write(self) -> ReadUnderWrite { pub fn read_under_write(self) -> ReadUnderWrite {
@ -707,7 +707,7 @@ pub(crate) struct MemBuilderTarget {
pub(crate) initial_value: Option<Interned<BitSlice>>, pub(crate) initial_value: Option<Interned<BitSlice>>,
pub(crate) ports: Vec<MemPort<DynPortType>>, pub(crate) ports: Vec<MemPort<DynPortType>>,
pub(crate) read_latency: usize, pub(crate) read_latency: usize,
pub(crate) write_latency: NonZeroU32, pub(crate) write_latency: NonZeroUsize,
pub(crate) read_under_write: ReadUnderWrite, pub(crate) read_under_write: ReadUnderWrite,
pub(crate) port_annotations: Vec<TargetedAnnotation>, pub(crate) port_annotations: Vec<TargetedAnnotation>,
pub(crate) mem_annotations: Vec<Annotation>, pub(crate) mem_annotations: Vec<Annotation>,
@ -867,7 +867,7 @@ impl<Element: Type, Len: Size> MemBuilder<Element, Len> {
initial_value: None, initial_value: None,
ports: vec![], ports: vec![],
read_latency: 0, read_latency: 0,
write_latency: NonZeroU32::new(1).unwrap(), write_latency: NonZeroUsize::new(1).unwrap(),
read_under_write: ReadUnderWrite::Old, read_under_write: ReadUnderWrite::Old,
port_annotations: vec![], port_annotations: vec![],
mem_annotations: vec![], mem_annotations: vec![],
@ -1030,10 +1030,10 @@ impl<Element: Type, Len: Size> MemBuilder<Element, Len> {
pub fn read_latency(&mut self, read_latency: usize) { pub fn read_latency(&mut self, read_latency: usize) {
self.target.borrow_mut().read_latency = read_latency; self.target.borrow_mut().read_latency = read_latency;
} }
pub fn get_write_latency(&self) -> NonZeroU32 { pub fn get_write_latency(&self) -> NonZeroUsize {
self.target.borrow().write_latency self.target.borrow().write_latency
} }
pub fn write_latency(&mut self, write_latency: NonZeroU32) { pub fn write_latency(&mut self, write_latency: NonZeroUsize) {
self.target.borrow_mut().write_latency = write_latency; self.target.borrow_mut().write_latency = write_latency;
} }
pub fn get_read_under_write(&self) -> ReadUnderWrite { pub fn get_read_under_write(&self) -> ReadUnderWrite {