From cd0dd7b7eed3a67b895b33c775583b24364fe5b4 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Mon, 9 Dec 2024 23:01:40 -0800
Subject: [PATCH] change memory write latency to NonZeroUsize to match read
 latency being usize

---
 crates/fayalite/src/memory.rs | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/crates/fayalite/src/memory.rs b/crates/fayalite/src/memory.rs
index f583a8c..4992cd6 100644
--- a/crates/fayalite/src/memory.rs
+++ b/crates/fayalite/src/memory.rs
@@ -22,7 +22,7 @@ use std::{
     fmt,
     hash::{Hash, Hasher},
     marker::PhantomData,
-    num::NonZeroU32,
+    num::NonZeroUsize,
     rc::Rc,
 };
 
@@ -478,7 +478,7 @@ struct MemImpl<Element: Type, Len: Size, P> {
     initial_value: Option<Interned<BitSlice>>,
     ports: P,
     read_latency: usize,
-    write_latency: NonZeroU32,
+    write_latency: NonZeroUsize,
     read_under_write: ReadUnderWrite,
     port_annotations: Interned<[TargetedAnnotation]>,
     mem_annotations: Interned<[Annotation]>,
@@ -562,7 +562,7 @@ impl<Element: Type, Len: Size> Mem<Element, Len> {
         initial_value: Option<Interned<BitSlice>>,
         ports: Interned<[MemPort<DynPortType>]>,
         read_latency: usize,
-        write_latency: NonZeroU32,
+        write_latency: NonZeroUsize,
         read_under_write: ReadUnderWrite,
         port_annotations: Interned<[TargetedAnnotation]>,
         mem_annotations: Interned<[Annotation]>,
@@ -645,7 +645,7 @@ impl<Element: Type, Len: Size> Mem<Element, Len> {
     pub fn read_latency(self) -> usize {
         self.0.read_latency
     }
-    pub fn write_latency(self) -> NonZeroU32 {
+    pub fn write_latency(self) -> NonZeroUsize {
         self.0.write_latency
     }
     pub fn read_under_write(self) -> ReadUnderWrite {
@@ -707,7 +707,7 @@ pub(crate) struct MemBuilderTarget {
     pub(crate) initial_value: Option<Interned<BitSlice>>,
     pub(crate) ports: Vec<MemPort<DynPortType>>,
     pub(crate) read_latency: usize,
-    pub(crate) write_latency: NonZeroU32,
+    pub(crate) write_latency: NonZeroUsize,
     pub(crate) read_under_write: ReadUnderWrite,
     pub(crate) port_annotations: Vec<TargetedAnnotation>,
     pub(crate) mem_annotations: Vec<Annotation>,
@@ -867,7 +867,7 @@ impl<Element: Type, Len: Size> MemBuilder<Element, Len> {
             initial_value: None,
             ports: vec![],
             read_latency: 0,
-            write_latency: NonZeroU32::new(1).unwrap(),
+            write_latency: NonZeroUsize::new(1).unwrap(),
             read_under_write: ReadUnderWrite::Old,
             port_annotations: vec![],
             mem_annotations: vec![],
@@ -1030,10 +1030,10 @@ impl<Element: Type, Len: Size> MemBuilder<Element, Len> {
     pub fn read_latency(&mut self, read_latency: usize) {
         self.target.borrow_mut().read_latency = read_latency;
     }
-    pub fn get_write_latency(&self) -> NonZeroU32 {
+    pub fn get_write_latency(&self) -> NonZeroUsize {
         self.target.borrow().write_latency
     }
-    pub fn write_latency(&mut self, write_latency: NonZeroU32) {
+    pub fn write_latency(&mut self, write_latency: NonZeroUsize) {
         self.target.borrow_mut().write_latency = write_latency;
     }
     pub fn get_read_under_write(&self) -> ReadUnderWrite {