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Fix typo
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Fixes: #1
This commit is contained in:
Jacob Lifshay 2024-07-22 15:58:05 -07:00
parent 180ecad017
commit 0611044941
Signed by: programmerjake
SSH key fingerprint: SHA256:B1iRVvUJkvd7upMIiMqn6OyxvD2SgJkAH3ZnUOj6z+c
1 changed files with 1 additions and 1 deletions
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crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/wires.rs
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@ -4,7 +4,7 @@
//! they have no memory (they're combinatorial). //! they have no memory (they're combinatorial).
//! You must [connect][`ModuleBuilder::connect`] to all wires, so they have a defined value. //! You must [connect][`ModuleBuilder::connect`] to all wires, so they have a defined value.
//! //!
//! Registers create a Rust variable with type [`Expr<T>`] where `T` is the type of the register. //! Wires create a Rust variable with type [`Expr<T>`] where `T` is the type of the wire.
//! //!
//! Wires follow [connection semantics], which are unlike assignments in software, so you should read it. //! Wires follow [connection semantics], which are unlike assignments in software, so you should read it.
//! //!