From 0611044941cad36876ac12bd8a06d7ae7e553184 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Mon, 22 Jul 2024 15:58:05 -0700 Subject: [PATCH] Fix typo Fixes: #1 --- .../src/_docs/modules/module_bodies/hdl_let_statements/wires.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/wires.rs b/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/wires.rs index 3128e99..882c342 100644 --- a/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/wires.rs +++ b/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/wires.rs @@ -4,7 +4,7 @@ //! they have no memory (they're combinatorial). //! You must [connect][`ModuleBuilder::connect`] to all wires, so they have a defined value. //! -//! Registers create a Rust variable with type [`Expr`] where `T` is the type of the register. +//! Wires create a Rust variable with type [`Expr`] where `T` is the type of the wire. //! //! Wires follow [connection semantics], which are unlike assignments in software, so you should read it. //!