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"Register" in Wire Docs #1

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opened 2024-07-22 22:50:27 +00:00 by cesar · 0 comments
cesar commented 2024-07-22 22:50:27 +00:00
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Found a typo:

Line 7 in 180ecad
//! Registers create a Rust variable with type [`Expr<T>`] where `T` is the type of the register.

Found a typo: https://git.libre-chip.org/libre-chip/fayalite/src/commit/180ecad01762d9f81c6ef8b70afb0c16b76ea802/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/wires.rs#L7
programmerjake referenced this issue from a commit 2024-07-22 22:59:16 +00:00
Fix typo
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Reference: libre-chip/fayalite#1
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