Actions - libre-chip/cpu - Libre-Chip.org

unit::alu_branch: convert *MOp functions to hdl_module

#118 -Commit a3898e8c13 pushed by programmerjake

#14

2026-05-27 03:19:00 +00:00

6m56s

unit::alu_branch: implement for LogicalFlagsMOp

#117 -Commit b25448a275 pushed by programmerjake

#14

2026-05-26 06:50:17 +00:00

6m41s

unit::alu_branch: implement for LogicalFlagsMOp

#116 -Commit 3bff2bd224 pushed by programmerjake

#14

2026-05-26 06:40:26 +00:00

4m40s

make Unit API work with rename_execute_retire and add a rename_execute_retire test using unit::alu_branch

#115 -Commit 7151841af5 pushed by programmerjake

master

2026-05-25 05:58:58 +00:00

7m11s

make Unit API work with rename_execute_retire and add a rename_execute_retire test using unit::alu_branch

#114 -Commit 7151841af5 pushed by programmerjake

#13

2026-05-25 05:36:42 +00:00

6m14s

rename_execute_retire: add reference counting for L1 registers

#113 -Commit 151683fbda pushed by programmerjake

master

2026-05-22 07:05:35 +00:00

7m20s

rename_execute_retire: add reference counting for L1 registers

#112 -Commit 151683fbda pushed by programmerjake

#12

2026-05-22 06:48:42 +00:00

6m29s

rename_execute_retire: add reference counting for L2 registers

#111 -Commit e0dc5d486b pushed by programmerjake

#12

2026-05-22 04:13:14 +00:00

6m3s

move RenameTable and ReorderBuffer into their own mods and add reference counting for l2 registers

#110 -Commit b956a68724 pushed by programmerjake

#12

2026-05-22 03:34:58 +00:00

6m1s

implement register fences and use for L2 reg file writes and when running out of L2 reg file output regs

#109 -Commit bf2cb688c7 pushed by programmerjake

#12

2026-05-22 00:32:46 +00:00

6m25s

WIP fixing deadlock when running rename_execute_retire_save_restore_gprs

#108 -Commit ed331a3a96 pushed by programmerjake

#12

2026-05-21 06:44:32 +00:00

6m1s

rename_execute_retire: generate l2 stores earlier to make more space in units to increase throughput

#107 -Commit 6026df8d7a pushed by programmerjake

#12

2026-05-21 00:55:07 +00:00

5m45s

tests/rename_execute_retire: add and use mock_combinational_unit

#106 -Commit 0d69666b00 pushed by programmerjake

#12

2026-05-20 02:40:34 +00:00

6m19s

tests/rename_execute_retire: make loads/stores take more than one cycle to execute

#105 -Commit 2363e65564 pushed by programmerjake

#12

2026-05-20 01:15:16 +00:00

6m19s

rename_execute_retire: add a `head -n1` test

#104 -Commit 79ac190093 pushed by programmerjake

#12

2026-05-19 05:32:12 +00:00

9m26s

add TraceAsString around instructions and stuff to make the .vcd files much smaller and easier to read

#103 -Commit 0d3c41fa14 pushed by programmerjake

#12

2026-05-15 05:45:57 +00:00

5m45s

WIP: updating for fayalite/redo-trace-as-string

#102 -Commit 4bfb20d1b0 pushed by programmerjake

#12

2026-05-14 06:35:36 +00:00

22s

rename_execute_retire: implement generating L2 reg file writes

#101 -Commit 3fbdab0862 pushed by programmerjake

#12

2026-05-11 06:52:04 +00:00

12m14s

WIP adding new test for L2 reg file store

#100 -Commit 04e924460a pushed by programmerjake

#12

2026-05-09 03:29:49 +00:00

5m42s

WIP adding new test for L2 reg file store

#99 -Commit 3300e7ca01 pushed by programmerjake

#12

2026-05-08 04:50:35 +00:00

5m45s

WIP adding new test for L2 reg file store

#98 -Commit fca2ff8c91 pushed by programmerjake

#12

2026-05-07 03:17:52 +00:00

5m23s

update decode_one_insn.vcd for modified instruction data structures

#97 -Commit 409ca7bf97 pushed by programmerjake

#12

2026-05-06 04:57:57 +00:00

5m14s

update fayalite to fix bug in VCD generation

#96 -Commit 9308e5d195 pushed by programmerjake

#12

2026-05-06 04:34:28 +00:00

5m18s

update next_pc.vcd

#95 -Commit 4d4f8aadd7 pushed by programmerjake

#12

2026-05-06 03:01:04 +00:00

5m10s

group micro ops by the instruction they come from when retiring

#94 -Commit 09c8c194e0 pushed by programmerjake

#12

2026-05-06 02:47:49 +00:00

4m6s

use custom debug

#93 -Commit 83b3f7bac9 pushed by programmerjake

#12

2026-05-04 06:42:18 +00:00

4m1s

update fayalite to include simulator optimizations and custom debug

#92 -Commit ac99caa3b6 pushed by programmerjake

#12

2026-05-01 06:25:24 +00:00

1m54s

update fayalite to include simulator optimizations

#91 -Commit c3679f2718 pushed by programmerjake

#12

2026-05-01 02:27:57 +00:00

4m24s

add support for speculative loads

#90 -Commit 283117d8df pushed by programmerjake

#12

2026-05-01 01:01:08 +00:00

9m21s

add support for speculative loads

#89 -Commit 7ea22dafe2 pushed by programmerjake

#12

2026-05-01 00:51:43 +00:00

26s