Actions - libre-chip/cpu - Libre-Chip.org

update fayalite for libre-chip/fayalite#68 change vcd output to have module contents under instance's name

test.yml #85 -Commit 6ed04c809e pushed by programmerjake

master

2026-03-27 03:08:42 +00:00

22m6s

update fayalite for libre-chip/fayalite#68 change vcd output to have module contents under instance's name

test.yml #84 -Commit 6ed04c809e pushed by programmerjake

#11

2026-03-27 02:46:30 +00:00

21m54s

add sram and main_memory_and_io modules

test.yml #83 -Commit a1147f0f05 pushed by programmerjake

master

2026-03-26 09:50:13 +00:00

23m28s

add sram and main_memory_and_io modules

test.yml #82 -Commit a1147f0f05 pushed by programmerjake

#10

2026-03-26 09:26:26 +00:00

22m26s

add sram and main_memory_and_io modules

test.yml #81 -Commit 5c4ec8127f pushed by programmerjake

#10

2026-03-26 09:02:03 +00:00

22m3s

add fetch::fetch and fetch::l1_i_cache with some testing

test.yml #80 -Commit e69c92c8da pushed by programmerjake

master

2026-02-22 03:21:03 +00:00

22m40s

add fetch::fetch and fetch::l1_i_cache with some testing

test.yml #79 -Commit e69c92c8da pushed by programmerjake

#9

2026-02-22 02:55:15 +00:00

22m37s

add fetch::fetch and fetch::l1_i_cache with some testing

test.yml #78 -Commit 198fa64899 pushed by programmerjake

#9

2026-02-22 02:32:21 +00:00

18m42s

add fetch::fetch and fetch::l1_i_cache with some testing

test.yml #77 -Commit fff8cf32c1 pushed by programmerjake

#9

2026-02-21 01:46:58 +00:00

25m39s

update fayalite to include 1bc835803b for a major speedup of the decoder tests

test.yml #76 -Commit 596440755c pushed by programmerjake

master

2026-02-04 03:27:34 +00:00

24m49s

update fayalite to include 1bc835803b for a major speedup of the decoder tests

test.yml #75 -Commit 596440755c pushed by programmerjake

#8

2026-02-04 03:00:20 +00:00

23m44s

implement decoding mtspr/mfspr/mftb

test.yml #74 -Commit f88346ea37 pushed by programmerjake

master

2026-01-29 02:54:31 +00:00

32m15s

implement decoding mtspr/mfspr/mftb

test.yml #73 -Commit f88346ea37 pushed by programmerjake

#7

2026-01-29 02:07:18 +00:00

31m51s

implement decoding all rotate instructions

test.yml #72 -Commit a42b76b468 pushed by programmerjake

#7

2026-01-28 03:47:43 +00:00

27m13s

reduce the number of wires to have one per form/field pair instead of one per insn/field pair

test.yml #71 -Commit faa8dde774 pushed by programmerjake

#7

2026-01-27 00:43:57 +00:00

30m10s

add shift/rotate MOp definition

test.yml #70 -Commit 59874b9b29 pushed by programmerjake

#7

2026-01-26 05:04:43 +00:00

29m25s

implement decoding 8/16/32/64-bit store instructions -- all of Power ISA v3.1c Book I 3.3.3

test.yml #69 -Commit 0824b63d31 pushed by programmerjake

#7

2026-01-25 23:35:07 +00:00

28m0s

implement decoding 8/16/32/64-bit load instructions -- all of Power ISA v3.1C Book I 3.3.2

test.yml #68 -Commit 706d54ae0d pushed by programmerjake

#7

2026-01-24 00:36:14 +00:00

28m7s

make LogicalFlagsMOp also copy the dest PRegValue.flags into PRegValue.int_fp

test.yml #67 -Commit d361a2b578 pushed by programmerjake

#7

2026-01-23 20:40:41 +00:00

27m17s

implement decoding mcrf

test.yml #66 -Commit 29757a568c pushed by programmerjake

#7

2026-01-23 19:47:50 +00:00

18s

fix & clean up MOp definitions and ensure_reg_fields_are_in_the_same_place

test.yml #65 -Commit e6f876f9af pushed by programmerjake

#7

2026-01-22 16:57:49 +00:00

28m23s

implement decoding mcrxrx

test.yml #64 -Commit 9b8d99e9af pushed by programmerjake

#7

2026-01-22 15:54:03 +00:00

18m42s

mark .vcd files as generated

test.yml #63 -Commit 0433e4f8f1 pushed by programmerjake

#7

2026-01-21 00:48:01 +00:00

27m1s

add tests for and fix decoding branch instructions

test.yml #62 -Commit 85ada6e55a pushed by programmerjake

#7

2026-01-20 07:06:43 +00:00

27m2s

add branch instructions, no tests yet

test.yml #61 -Commit 2e05329c36 pushed by programmerjake

#7

2026-01-20 04:37:55 +00:00

27m32s

update reg_alloc.vcd

test.yml #60 -Commit 62a330ed4d pushed by programmerjake

#7

2026-01-19 07:51:43 +00:00

27m29s

add test that UnitMOp has all the register fields aligned across the different variants

test.yml #59 -Commit c9a3de19b7 pushed by programmerjake

#7

2026-01-19 07:20:45 +00:00

27m1s

add copyright header to build.rs

test.yml #58 -Commit 781dbc6bcb pushed by programmerjake

master

2026-01-09 11:00:38 +00:00

27m22s

add copyright header to build.rs

test.yml #57 -Commit 781dbc6bcb pushed by programmerjake

#6

2026-01-09 10:33:13 +00:00

26m24s

fix vcd to match test output

test.yml #56 -Commit 3b5104c8fa pushed by programmerjake

master

2025-12-17 08:22:07 +00:00

26m57s