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tests/units_formal: implement tests for rest of AddSub[I] instructions

#133 -Commit fb0b07fbb2 pushed by programmerjake

master

2026-06-19 04:27:26 +00:00

30m14s

tests/units_formal: implement tests for rest of AddSub[I] instructions

#132 -Commit fb0b07fbb2 pushed by programmerjake

#15

2026-06-19 03:57:07 +00:00

29m21s

tests/units_formal: split up tests in hopes of making them run faster

#131 -Commit b6bbc97990 pushed by programmerjake

#15

2026-06-19 02:44:47 +00:00

23m25s

tests/units_formal: test more instructions

#130 -Commit ad9ec46aca pushed by programmerjake

#15

2026-06-18 08:13:18 +00:00

56m57s

tests/units_formal: test more instructions

#129 -Commit af87d52bf7 pushed by programmerjake

#15

2026-06-18 03:55:02 +00:00

20m40s

tests/units_formal: prove more addition instructions -- [p]addi and add[c][o][.]

#128 -Commit ebd69089c5 pushed by programmerjake

#15

2026-06-17 04:36:37 +00:00

24m29s

update fayalite to speed up big formal proofs

#127 -Commit 51d71c56f6 pushed by programmerjake

#15

2026-06-15 02:37:56 +00:00

10m59s

update generated vcd

#126 -Commit 999860b507 pushed by programmerjake

#15

2026-06-14 09:10:47 +00:00

22m40s

WIP: add test_power_isa_add_sim

#124 -Commit 9cc556c988 pushed by programmerjake

#15

2026-06-05 10:13:15 +00:00

1h35m8s

unit::alu_branch::compare: implement CmpRBOne/CmpRBTwo/CmpEqB

#121 -Commit 7acfaebfde pushed by programmerjake

master

2026-05-29 02:30:02 +00:00

6m50s

unit::alu_branch::compare: implement CmpRBOne/CmpRBTwo/CmpEqB

#120 -Commit 7acfaebfde pushed by programmerjake

#14

2026-05-29 02:22:30 +00:00

5m56s

redo ShiftRotateMOp and write actual operation definition in doc comment

#119 -Commit 7481d079d5 pushed by programmerjake

#14

2026-05-28 08:51:43 +00:00

6m57s

unit::alu_branch: convert *MOp functions to hdl_module

#118 -Commit a3898e8c13 pushed by programmerjake

#14

2026-05-27 03:19:00 +00:00

6m56s

unit::alu_branch: implement for LogicalFlagsMOp

#117 -Commit b25448a275 pushed by programmerjake

#14

2026-05-26 06:50:17 +00:00

6m41s

make Unit API work with rename_execute_retire and add a rename_execute_retire test using unit::alu_branch

#115 -Commit 7151841af5 pushed by programmerjake

master

2026-05-25 05:58:58 +00:00

7m11s

make Unit API work with rename_execute_retire and add a rename_execute_retire test using unit::alu_branch

#114 -Commit 7151841af5 pushed by programmerjake

#13

2026-05-25 05:36:42 +00:00

6m14s

rename_execute_retire: add reference counting for L1 registers

#113 -Commit 151683fbda pushed by programmerjake

master

2026-05-22 07:05:35 +00:00

7m20s

rename_execute_retire: add reference counting for L1 registers

#112 -Commit 151683fbda pushed by programmerjake

#12

2026-05-22 06:48:42 +00:00

6m29s

rename_execute_retire: add reference counting for L2 registers

#111 -Commit e0dc5d486b pushed by programmerjake

#12

2026-05-22 04:13:14 +00:00

6m3s

implement register fences and use for L2 reg file writes and when running out of L2 reg file output regs

#109 -Commit bf2cb688c7 pushed by programmerjake

#12

2026-05-22 00:32:46 +00:00

6m25s

rename_execute_retire: generate l2 stores earlier to make more space in units to increase throughput

#107 -Commit 6026df8d7a pushed by programmerjake

#12

2026-05-21 00:55:07 +00:00

5m45s

tests/rename_execute_retire: add and use mock_combinational_unit

#106 -Commit 0d69666b00 pushed by programmerjake

#12

2026-05-20 02:40:34 +00:00

6m19s

tests/rename_execute_retire: make loads/stores take more than one cycle to execute

#105 -Commit 2363e65564 pushed by programmerjake

#12

2026-05-20 01:15:16 +00:00

6m19s

rename_execute_retire: add a `head -n1` test

#104 -Commit 79ac190093 pushed by programmerjake

#12

2026-05-19 05:32:12 +00:00

9m26s

add TraceAsString around instructions and stuff to make the .vcd files much smaller and easier to read

#103 -Commit 0d3c41fa14 pushed by programmerjake

#12

2026-05-15 05:45:57 +00:00

5m45s

rename_execute_retire: implement generating L2 reg file writes

#101 -Commit 3fbdab0862 pushed by programmerjake

#12

2026-05-11 06:52:04 +00:00

12m14s

update decode_one_insn.vcd for modified instruction data structures

#97 -Commit 409ca7bf97 pushed by programmerjake

#12

2026-05-06 04:57:57 +00:00

5m14s

update fayalite for libre-chip/fayalite#68 change vcd output to have module contents under instance's name

#85 -Commit 6ed04c809e pushed by programmerjake

master

2026-03-27 03:08:42 +00:00

22m6s

update fayalite for libre-chip/fayalite#68 change vcd output to have module contents under instance's name

#84 -Commit 6ed04c809e pushed by programmerjake

#11

2026-03-27 02:46:30 +00:00

21m54s

add sram and main_memory_and_io modules

#83 -Commit a1147f0f05 pushed by programmerjake

master

2026-03-26 09:50:13 +00:00

23m28s