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master 3d5d8c54b6 · add repository to cache key · Updated 2024-10-31 03:55:02 +00:00

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rocq_hdl a398f8f185 · Define design safety, and prove it for 1-step and 2-step induction. · Updated 2025-12-23 01:30:13 +00:00    cesar	0 184	libre-chip/fayalite#59 Open
rocq_playground c32cdee4f7 · Format, · Updated 2025-12-09 00:49:05 +00:00    cesar	0 179	Compare
fifo-proof 3771cea78e · Gather the FIFO debug ports in a bundle · Updated 2024-12-29 16:17:24 +00:00    cesar	0 72	libre-chip/fayalite#11 Merged
formal_memories 2e7d685dc7 · add module exercising formal verification of memories · Updated 2024-12-08 20:13:26 +00:00    cesar	0 4	libre-chip/fayalite#7 Merged
formal_test_case c1f1a8b749 · Add test module exercising formal verification. · Updated 2024-11-20 21:29:39 +00:00    cesar	0 1	libre-chip/fayalite#2 Merged