26 commits

Author	SHA1	Message	Date
Jacob Lifshay	921cddbe06	disable tests/reg_alloc.rs for now	2025-03-18 17:26:47 -07:00
Jacob Lifshay	b9d68c0019	WIP: splitting reg_alloc	2025-03-14 18:26:34 -07:00
Jacob Lifshay	9199fdf35c	add name_mangling_serde crate	2025-03-08 22:38:30 -08:00
Jacob Lifshay	60341e22af	WIP: add ArrayVec	2025-03-04 00:20:33 -08:00
Jacob Lifshay	518284685f	UnitMOp now has L2RegisterFileMOp after renaming and instead has MoveRegMOp before renaming	2025-02-28 17:45:46 -08:00
Jacob Lifshay	6c91d1b0b0	start adding ROB	2025-02-27 18:22:01 -08:00
Jacob Lifshay	4ff75313e7	add helper functions for creating instructions	2025-02-23 20:51:44 -08:00
Jacob Lifshay	5b15f4a6b4	runs instructions that read other instructions' outputs	2025-02-23 19:51:45 -08:00
Jacob Lifshay	3bd5c77a3f	unit_base is basically finished, implemented AddSub[I], didn't check any tests yet	2025-02-20 20:24:14 -08:00
Jacob Lifshay	3f6e5cc600	WIP implementing unit_base	2025-02-19 23:54:41 -08:00
Jacob Lifshay	2b7e7e4946	WIP adding unit input/output values and insn tracking	2025-02-13 20:55:43 -08:00
Jacob Lifshay	1084278f34	reg_alloc: add writes to rename table	2025-02-11 19:19:06 -08:00
Jacob Lifshay	294e979848	tests/reg_alloc: remove simulator debug output	2025-02-06 21:31:05 -08:00
Jacob Lifshay	7efcd872b5	working on reg_alloc	2025-02-06 21:28:30 -08:00
Jacob Lifshay	88eff5952b	working on reg_alloc -- wire up free_regs_tracker.alloc_out	2025-01-15 19:47:00 -08:00
Jacob Lifshay	5f7766777a	working on reg_alloc -- selected_unit_nums should be correct now	2025-01-12 22:12:58 -08:00
Jacob Lifshay	89717f8916	update to latest version of fayalite	2025-01-09 23:36:23 -08:00
Jacob Lifshay	12481cfab3	start debugging reg_alloc with simulator	2024-12-20 00:28:22 -08:00
Jacob Lifshay	b51109f4f6	WIP implementing reg_alloc	2024-11-05 17:34:31 -08:00
Jacob Lifshay	a305ad51b2	reduce formal proof depth to avoid z3 eating all our memory	2024-10-15 23:50:51 -07:00
Jacob Lifshay	aaa2cb193e	add formal proof for unit_free_regs_tracker	2024-10-15 02:39:56 -07:00
Jacob Lifshay	cb5855589f	WIP adding register allocator	2024-10-14 21:20:42 -07:00
Jacob Lifshay	d7f62737f2	add license headers	2024-10-14 16:29:20 -07:00
Jacob Lifshay	f65fc1d616	add more register stuff	2024-10-13 01:41:45 -07:00
Jacob Lifshay	4c3dd128a3	WIP: adding micro ops	2024-10-10 22:57:11 -07:00
Jacob Lifshay	0f4f067996	start adding cpu data types	2024-10-08 20:22:15 -07:00