forked from libre-chip/cpu
add helper functions for creating instructions
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SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
3 changed files with 188 additions and 94 deletions
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@ -10,6 +10,20 @@ use std::{fmt, marker::PhantomData, ops::Range};
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pub mod power_isa;
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pub trait MOpInto<Target: MOpTrait>: MOpTrait {
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fn mop_into_ty(self) -> Target;
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fn mop_into(this: Expr<Self>) -> Expr<Target>;
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}
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impl<T: MOpTrait> MOpInto<T> for T {
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fn mop_into_ty(self) -> T {
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self
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}
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fn mop_into(this: Expr<Self>) -> Expr<T> {
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this
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}
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}
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pub trait MOpTrait: Type {
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type Mapped<NewDestReg: Type, NewSrcRegWidth: Size>: MOpTrait;
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type DestReg: Type;
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@ -424,6 +438,30 @@ macro_rules! mop_enum {
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)*
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}
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impl<$DestReg: Type, $SrcRegWidth: Size, Target: MOpTrait> MOpInto<Target> for $first_ty
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where
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$MOp<$DestReg, $SrcRegWidth>: MOpInto<Target>
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{
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fn mop_into_ty(self) -> Target {
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MOpInto::mop_into_ty($MOp[MOpTrait::dest_reg_ty(self)][MOpTrait::src_reg_width(self)])
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}
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fn mop_into(this: Expr<Self>) -> Expr<Target> {
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MOpInto::mop_into(MOpInto::<$MOp<$DestReg, $SrcRegWidth>>::mop_into_ty(Expr::ty(this)).$FirstVariant(this))
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}
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}
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$(impl<$DestReg: Type, $SrcRegWidth: Size, Target: MOpTrait> MOpInto<Target> for $ty
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where
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$MOp<$DestReg, $SrcRegWidth>: MOpInto<Target>
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{
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fn mop_into_ty(self) -> Target {
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MOpInto::mop_into_ty($MOp[MOpTrait::dest_reg_ty(self)][MOpTrait::src_reg_width(self)])
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}
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fn mop_into(this: Expr<Self>) -> Expr<Target> {
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MOpInto::mop_into(MOpInto::<$MOp<$DestReg, $SrcRegWidth>>::mop_into_ty(Expr::ty(this)).$Variant(this))
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}
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})*
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impl<$DestReg: Type, $SrcRegWidth: Size> MOpTrait for $MOp<$DestReg, $SrcRegWidth> {
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type Mapped<NewDestReg: Type, NewSrcRegWidth: Size> = $MOp<NewDestReg, NewSrcRegWidth>;
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type DestReg = $DestReg;
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@ -517,6 +555,70 @@ common_mop_struct! {
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}
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}
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impl<DestReg: Type, SrcRegWidth: Size> AddSubMOp<DestReg, SrcRegWidth, ConstUsize<3>> {
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#[hdl]
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pub fn add_sub<Target: MOpTrait>(
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dest: impl ToExpr<Type = DestReg>,
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src: impl ToExpr<Type = Array<UIntType<SrcRegWidth>, 3>>,
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imm: impl ToExpr<Type = SInt<{ COMMON_MOP_3_IMM_WIDTH }>>,
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output_integer_mode: impl ToExpr<Type = OutputIntegerMode>,
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invert_src0: impl ToExpr<Type = Bool>,
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src1_is_carry_in: impl ToExpr<Type = Bool>,
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invert_carry_in: impl ToExpr<Type = Bool>,
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add_pc: impl ToExpr<Type = Bool>,
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) -> Expr<Target>
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where
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Self: MOpInto<Target>,
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{
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MOpInto::mop_into(
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#[hdl]
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AddSubMOp {
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alu_common: #[hdl]
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AluCommonMOp {
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common: CommonMOp::new(0_hdl_u0, dest, src, Expr::as_dyn_int(imm.to_expr())),
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output_integer_mode,
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},
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invert_src0,
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src1_is_carry_in,
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invert_carry_in,
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add_pc,
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},
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)
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}
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}
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impl<DestReg: Type, SrcRegWidth: Size> AddSubMOp<DestReg, SrcRegWidth, ConstUsize<2>> {
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#[hdl]
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pub fn add_sub_i<Target: MOpTrait>(
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dest: impl ToExpr<Type = DestReg>,
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src: impl ToExpr<Type = Array<UIntType<SrcRegWidth>, 2>>,
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imm: impl ToExpr<Type = SInt<{ COMMON_MOP_2_IMM_WIDTH }>>,
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output_integer_mode: impl ToExpr<Type = OutputIntegerMode>,
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invert_src0: impl ToExpr<Type = Bool>,
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src1_is_carry_in: impl ToExpr<Type = Bool>,
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invert_carry_in: impl ToExpr<Type = Bool>,
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add_pc: impl ToExpr<Type = Bool>,
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) -> Expr<Target>
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where
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Self: MOpInto<Target>,
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{
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MOpInto::mop_into(
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#[hdl]
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AddSubMOp {
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alu_common: #[hdl]
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AluCommonMOp {
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common: CommonMOp::new(0_hdl_u0, dest, src, Expr::as_dyn_int(imm.to_expr())),
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output_integer_mode,
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},
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invert_src0,
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src1_is_carry_in,
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invert_carry_in,
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add_pc,
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},
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)
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}
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}
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common_mop_struct! {
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#[mapped(<NewDestReg, NewSrcRegWidth> LogicalMOp<NewDestReg, NewSrcRegWidth>)]
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#[hdl(cmp_eq)]
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@ -527,6 +629,32 @@ common_mop_struct! {
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}
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}
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impl<DestReg: Type, SrcRegWidth: Size> LogicalMOp<DestReg, SrcRegWidth> {
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#[hdl]
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pub fn logical<Target: MOpTrait>(
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dest: impl ToExpr<Type = DestReg>,
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src: impl ToExpr<Type = Array<UIntType<SrcRegWidth>, 2>>,
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imm: impl ToExpr<Type = SInt<{ COMMON_MOP_2_IMM_WIDTH }>>,
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output_integer_mode: impl ToExpr<Type = OutputIntegerMode>,
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lut: impl ToExpr<Type = UInt<4>>,
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) -> Expr<Target>
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where
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Self: MOpInto<Target>,
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{
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MOpInto::mop_into(
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#[hdl]
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LogicalMOp {
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alu_common: #[hdl]
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AluCommonMOp {
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common: CommonMOp::new(0_hdl_u0, dest, src, Expr::as_dyn_int(imm.to_expr())),
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output_integer_mode,
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},
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lut,
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},
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)
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}
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}
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common_mop_struct! {
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#[mapped(<NewDestReg, NewSrcRegWidth> BranchMOp<NewDestReg, NewSrcRegWidth>)]
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#[hdl(cmp_eq)]
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@ -4,7 +4,7 @@
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use crate::{
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config::CpuConfig,
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instruction::{
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mop_enum, AluBranchMOp, L2RegisterFileMOp, LoadStoreMOp, MOpTrait, UnitOutRegNum,
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mop_enum, AluBranchMOp, L2RegisterFileMOp, LoadStoreMOp, MOpInto, MOpTrait, UnitOutRegNum,
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},
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register::{FlagsMode, PRegValue},
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unit::unit_base::UnitToRegAlloc,
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@ -3,10 +3,7 @@
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use cpu::{
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config::{CpuConfig, UnitConfig},
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instruction::{
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AddSubMOp, AluCommonMOp, CommonMOp, LogicalMOp, MOp, MOpDestReg, MOpRegNum,
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OutputIntegerMode, COMMON_MOP_2_IMM_WIDTH, COMMON_MOP_3_IMM_WIDTH,
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},
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instruction::{AddSubMOp, LogicalMOp, MOp, MOpDestReg, MOpRegNum, OutputIntegerMode},
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reg_alloc::{reg_alloc, FetchedDecodedMOp},
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register::{FlagsMode, PRegFlagsPowerISA},
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unit::{GlobalState, UnitKind},
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@ -47,97 +44,66 @@ fn test_reg_alloc() {
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),
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},
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);
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let insns = std::array::from_fn::<_, 4, _>(|i| {
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MOp.AluBranch(MOp.AluBranch.AddSubI(
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let insns_init: [Expr<MOp>; 4] = std::array::from_fn(|i| {
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AddSubMOp::add_sub_i(
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#[hdl]
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AddSubMOp {
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alu_common: #[hdl]
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AluCommonMOp {
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common: CommonMOp::new(
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0_hdl_u0,
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#[hdl]
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MOpDestReg {
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normal_regs: #[hdl]
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[
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#[hdl]
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MOpRegNum { value: i as u8 + 1 },
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MOpRegNum::const_zero(),
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],
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flag_regs: #[hdl]
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[HdlSome(()), HdlNone()],
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},
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[0u8; 2],
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0x12345678u32.cast_to(SInt[COMMON_MOP_2_IMM_WIDTH]),
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),
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output_integer_mode: OutputIntegerMode.DupLow32(),
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},
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invert_src0: false,
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src1_is_carry_in: false,
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invert_carry_in: false,
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add_pc: false,
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MOpDestReg {
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normal_regs: #[hdl]
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[
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#[hdl]
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MOpRegNum { value: i as u8 + 1 },
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MOpRegNum::const_zero(),
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],
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flag_regs: #[hdl]
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[HdlSome(()), HdlNone()],
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},
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))
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})
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.into_iter()
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.chain(
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[
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MOp.AluBranch(MOp.AluBranch.AddSub(
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#[hdl]
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AddSubMOp {
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alu_common: #[hdl]
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AluCommonMOp {
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common: CommonMOp::new(
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0_hdl_u0,
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#[hdl]
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MOpDestReg {
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normal_regs: #[hdl]
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[
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#[hdl]
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MOpRegNum { value: 1u8 },
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MOpRegNum::const_zero(),
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],
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flag_regs: #[hdl]
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[HdlSome(()), HdlNone()],
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},
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[1u8, 0, 0],
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1.cast_to(SInt[COMMON_MOP_3_IMM_WIDTH]),
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),
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output_integer_mode: OutputIntegerMode.Full64(),
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},
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invert_src0: false,
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src1_is_carry_in: false,
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invert_carry_in: false,
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add_pc: false,
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},
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)),
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MOp.AluBranch(MOp.AluBranch.Logical(
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#[hdl]
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LogicalMOp {
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alu_common: #[hdl]
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AluCommonMOp {
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common: CommonMOp::new(
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0_hdl_u0,
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#[hdl]
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MOpDestReg {
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normal_regs: [
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#[hdl]
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MOpRegNum { value: 2u8 },
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MOpRegNum::const_zero(),
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],
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flag_regs: [HdlNone(), HdlSome(())],
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},
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[2u8, 4u8],
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SInt[COMMON_MOP_2_IMM_WIDTH].zero(),
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),
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output_integer_mode: OutputIntegerMode.Full64(),
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},
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lut: 0b0110_hdl_u4,
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},
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)),
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]
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.into_iter()
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.cycle(),
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);
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[0u8; 2],
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0x12345678u32.cast_to_static(),
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OutputIntegerMode.DupLow32(),
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false,
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false,
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false,
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false,
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)
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});
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let insns_loop = [
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AddSubMOp::add_sub(
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#[hdl]
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MOpDestReg {
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normal_regs: #[hdl]
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[
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#[hdl]
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MOpRegNum { value: 1u8 },
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MOpRegNum::const_zero(),
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],
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flag_regs: #[hdl]
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[HdlSome(()), HdlNone()],
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},
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[1u8, 0, 0],
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1.cast_to_static(),
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OutputIntegerMode.Full64(),
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false,
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false,
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false,
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false,
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),
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LogicalMOp::logical(
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#[hdl]
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MOpDestReg {
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normal_regs: [
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#[hdl]
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MOpRegNum { value: 2u8 },
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MOpRegNum::const_zero(),
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],
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flag_regs: [HdlNone(), HdlSome(())],
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},
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[2u8, 4u8],
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0.cast_to_static(),
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OutputIntegerMode.Full64(),
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0b0110_hdl_u4,
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),
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];
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let insns = insns_init.into_iter().chain(insns_loop.into_iter().cycle());
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let mut insn_index = 0;
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for cycle in 0..20 {
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for fetch_index in 0..config.fetch_width.get() {
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