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working on reg_alloc -- wire up free_regs_tracker.alloc_out

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This commit is contained in:
Jacob Lifshay 2025-01-15 19:47:00 -08:00
parent 9781f1f4c5
commit 88eff5952b
Signed by: programmerjake
SSH key fingerprint: SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
4 changed files with 2274 additions and 1866 deletions
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19
crates/cpu/src/reg_alloc.rs
View file

@ -155,9 +155,20 @@ pub fn reg_alloc(config: &CpuConfig) {
unit_free_regs_tracker.free_in[0].data,
HdlOption[UInt[config.out_reg_num_width]].uninit(), // FIXME: just for debugging
);
connect(
unit_free_regs_tracker.alloc_out[0].ready,
Bool.uninit(), // FIXME: just for debugging
);
connect(unit_free_regs_tracker.alloc_out[0].ready, false);
for fetch_index in 0..config.fetch_width.get() {
#[hdl]
if let HdlNone = unit_free_regs_tracker.alloc_out[0].data {
// must come after to override connects in loops above
connect(available_units[fetch_index][unit_index], false);
}
#[hdl]
if let HdlSome(unit_num) = selected_unit_nums[fetch_index] {
#[hdl]
if unit_num.value.cmp_eq(unit_index) {
connect(unit_free_regs_tracker.alloc_out[0].ready, true);
}
}
}
}
}

3767
crates/cpu/tests/expected/reg_alloc.txt
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File diff suppressed because it is too large Load diff

326
crates/cpu/tests/expected/reg_alloc.vcd
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28
crates/cpu/tests/reg_alloc.rs
View file

@ -88,7 +88,7 @@ fn test_reg_alloc() {
},
),
);
for cycle in 0..10 {
for cycle in 0..20 {
sim.advance_time(SimDuration::from_nanos(500));
sim.write_clock(sim.io().cd.clk, true);
sim.advance_time(SimDuration::from_nanos(500));
@ -225,9 +225,29 @@ circuit reg_alloc:
wire _uninit_expr: Ty24
invalidate _uninit_expr
connect unit_0_free_regs_tracker.free_in[0].data, _uninit_expr @[reg_alloc.rs 154:9]
wire _uninit_expr_1: UInt<1>
invalidate _uninit_expr_1
connect unit_0_free_regs_tracker.alloc_out[0].ready, _uninit_expr_1 @[reg_alloc.rs 158:9]
connect unit_0_free_regs_tracker.alloc_out[0].ready, UInt<1>(0h0) @[reg_alloc.rs 158:9]
match unit_0_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 161:13]
HdlNone:
connect available_units[0][0], UInt<1>(0h0) @[reg_alloc.rs 163:17]
HdlSome(_match_arm_value_9):
skip
match selected_unit_nums[0]: @[reg_alloc.rs 166:13]
HdlNone:
skip
HdlSome(_match_arm_value_10):
when eq(_match_arm_value_10.value, UInt<64>(0h0)): @[reg_alloc.rs 168:17]
connect unit_0_free_regs_tracker.alloc_out[0].ready, UInt<1>(0h1) @[reg_alloc.rs 169:21]
match unit_0_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 161:13]
HdlNone:
connect available_units[1][0], UInt<1>(0h0) @[reg_alloc.rs 163:17]
HdlSome(_match_arm_value_11):
skip
match selected_unit_nums[1]: @[reg_alloc.rs 166:13]
HdlNone:
skip
HdlSome(_match_arm_value_12):
when eq(_match_arm_value_12.value, UInt<64>(0h0)): @[reg_alloc.rs 168:17]
connect unit_0_free_regs_tracker.alloc_out[0].ready, UInt<1>(0h1) @[reg_alloc.rs 169:21]
module alu_branch: @[alu_branch.rs 15:1]
input cd: Ty0 @[alu_branch.rs 18:29]
module unit_free_regs_tracker: @[unit_free_regs_tracker.rs 7:1]