NLnet 2024-12-324 memory system: main memory and IO devices
NLnet 2024-12-324 Translate the procedural model to use actual synthesizeable HDL.
NLnet 2024-12-324 Create a model of the instruction fetch/decode control system, using procedural implementations of the most complex HDL modules where appropriate.
NLnet 2024-12-324 Create the PowerISA decoder
NLnet 2024-12-324 Create the fetch and i-cache logic.
NLnet 2024-12-324 Create the next-instruction logic
NLnet 2024-12-324 Translate the procedural model to use actual synthesizeable HDL
NLnet 2024-12-324 Create a model of the whole rename/execute/retire control system, using procedural implementations of the most complex HDL modules where appropriate.
NLnet 2024-12-324 Add to the simulator in Fayalite the ability to transfer non-HDL data (e.g. HashMap) through the digital signalling mechanism, this allows using those data types when writing procedural models.
NLnet 2024-12-324 Add support for the Arty A7 100T since that's what we're using for CI.
NLnet 2024-12-324 Add support for the Orange Crab since both Cesar and Jacob have one.
NLnet 2024-12-324 Write support for board interface descriptions and the code for running the FPGA toolchain (similar to the existing code for running SymbiYosys -- the current formal verification toolchain).
NLnet 2024-12-324 Write the code to do the translation in Fayalite.
NLnet 2024-12-324 Figure out how exactly we should represent HDL in Rocq
fill out grant tracking structure
ok, now CI runs and the only failure is that all the issue numbers aren't filled in (since I'm waiting on @cesar's response before I create all the issues)
fill out grant tracking structure