programmerjake
deleted branch make-vcd-diff-friendly from programmerjake/fayalite
2026-02-24 04:18:28 +00:00
change VCD id generation to be based on hashing the path, making them better for git diff
programmerjake
created branch make-vcd-diff-friendly in programmerjake/fayalite
2026-02-24 04:08:24 +00:00
programmerjake
pushed to make-vcd-diff-friendly at programmerjake/fayalite
2026-02-24 04:08:24 +00:00
NLnet 2024-12-324 memory system: main memory and IO devices
@HaeckseAlex as I mentioned on Zulip:
@**Tobias Alexandra…
NLnet 2024-12-324 Create the fetch and i-cache logic.
In libre-chip/cpu#9 I implemented a direct-mapped L1 I-Cache designed to be integrated into the fetch pipeline control logic from https://git.libre-chip.org/libre-c…
NLnet 2024-12-324 Create the fetch and i-cache logic.
add fetch::fetch and fetch::l1_i_cache with some testing
programmerjake
deleted branch create-fetch-and-i-cache-logic from programmerjake/cpu
2026-02-22 02:58:21 +00:00
programmerjake
pushed to create-fetch-and-i-cache-logic at programmerjake/cpu
2026-02-22 02:32:37 +00:00
programmerjake
pushed to create-fetch-and-i-cache-logic at programmerjake/cpu
2026-02-22 02:13:36 +00:00
add fetch::fetch and fetch::l1_i_cache with some testing
programmerjake
pushed to create-fetch-and-i-cache-logic at programmerjake/cpu
2026-02-21 01:20:53 +00:00
programmerjake
pushed to create-fetch-and-i-cache-logic at programmerjake/cpu
2026-02-21 01:19:10 +00:00
programmerjake
pushed to create-fetch-and-i-cache-logic at programmerjake/cpu
2026-02-20 10:25:52 +00:00
programmerjake
pushed to create-fetch-and-i-cache-logic at programmerjake/cpu
2026-02-20 05:57:38 +00:00
programmerjake
pushed to create-fetch-and-i-cache-logic at programmerjake/cpu
2026-02-19 06:08:13 +00:00