programmerjake
pushed to wip-experimental-rust-port at libre-chip/parse_powerisa_pdf
2026-01-01 03:43:49 +00:00
programmerjake
pushed to wip-experimental-rust-port at libre-chip/parse_powerisa_pdf
2025-12-31 06:49:19 +00:00
programmerjake
created branch wip-experimental-rust-port in libre-chip/parse_powerisa_pdf
2025-12-30 15:29:45 +00:00
programmerjake
pushed to wip-experimental-rust-port at libre-chip/parse_powerisa_pdf
2025-12-30 15:29:45 +00:00
Formally define design safety, and prove it for 1-step and 2-step induction
so I'm clear, I approved this PR which I intend to mean that, if you think the current changes are good, feel free to merge them by clicking the "fast-forward" button.
Formally define design safety, and prove it for 1-step and 2-step induction
It'd be nice to add running Rocq to CI, but that can be left for a future PR
implement "Create the next-instruction logic" and "Create a model of the instruction fetch/decode control system"
NLnet 2024-12-324 Create a model of the instruction fetch/decode control system, using procedural implementations of the most complex HDL modules where appropriate.
NLnet 2024-12-324 Create the next-instruction logic
WIP: implement "Create the next-instruction logic" and "Create a model of the instruction fetch/decode control system"