programmerjake
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  • Joined on 2024-07-08
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programmerjake pushed to adding-simulator at libre-chip/fayalite 2024-12-13 23:05:22 +00:00
2af38de900 add more memory tests
programmerjake pushed to adding-simulator at libre-chip/fayalite 2024-12-13 04:51:11 +00:00
c756aeec70 tests/sim: add test for memory rw port
programmerjake pushed to adding-simulator at libre-chip/fayalite 2024-12-13 03:48:20 +00:00
903ca1bf30 sim: simple memory test works!
programmerjake pushed to adding-simulator at libre-chip/fayalite 2024-12-13 00:27:48 +00:00
8d030ac65d sim/interpreter: add addresses to instruction listing
562c479b62 sim/interpreter: fix StatePartLayout name in debug output
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programmerjake pushed to adding-simulator at libre-chip/fayalite 2024-12-12 07:29:05 +00:00
393f78a14d sim: add WIP memory test
programmerjake pushed to adding-simulator at libre-chip/fayalite 2024-12-11 08:01:40 +00:00
8616ee4737 tests/sim: test_enums works!
5087f16099 sim: fix assignments graph by properly including conditions as assignment inputs
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programmerjake pushed to adding-simulator at libre-chip/fayalite 2024-12-11 07:41:27 +00:00
6b31e6d515 sim: add .dot output for Assignments graph for debugging
564ccb30bc sim/vcd: fix variable identifiers to follow verilog rules
ca759168ff tests/sim: add WIP test for enums
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programmerjake commented on pull request libre-chip/fayalite#3 2024-12-10 07:14:50 +00:00
add a simulator

I think this should be complete enough to merge once I add tests for enums and memories.

there are a few missing minor features still that I probably won't implement before merging:

  • proper…
programmerjake pushed to adding-simulator at libre-chip/fayalite 2024-12-10 07:03:39 +00:00
e4cf66adf8 sim: implement memories, still needs testing
cd0dd7b7ee change memory write latency to NonZeroUsize to match read latency being usize
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programmerjake merged pull request libre-chip/fayalite#7 2024-12-08 21:25:32 +00:00
Add module exercising formal verification of memories
programmerjake pushed to master at libre-chip/fayalite 2024-12-08 21:25:32 +00:00
2e7d685dc7 add module exercising formal verification of memories
programmerjake pushed to adding-simulator at libre-chip/fayalite 2024-12-06 23:53:56 +00:00
9654167ca3 sim: WIP working on memory
programmerjake opened issue libre-chip/fayalite#6 2024-12-06 09:26:05 +00:00
Tracking Issue for FIRRTL or LLVM Circt problems
programmerjake pushed to adding-simulator at libre-chip/fayalite 2024-12-06 05:35:41 +00:00
3ed7827485 sim: WIP adding memory support
programmerjake pushed to adding-simulator at libre-chip/fayalite 2024-12-06 04:32:49 +00:00
e504cfebfe add BoolOrIntType::copy_bits_from_bigint_wrapping and take BigInt arguments by reference
9f42cab471 change to version 0.3.0 for breaking change
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programmerjake pushed to adding-simulator at libre-chip/fayalite 2024-12-06 02:17:31 +00:00
259bee39c2 tests/sim: split expected output text into separate files
programmerjake pushed to adding-simulator at libre-chip/fayalite 2024-12-05 05:04:47 +00:00
643816d5b5 vcd: handle enums with fields
programmerjake pushed to adding-simulator at libre-chip/fayalite 2024-12-05 04:59:26 +00:00
42afd2da0e sim: implement enums (except for connecting unequal enum types)
15bc304bb6 impl ToExpr for TargetBase
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programmerjake pushed to adding-simulator at libre-chip/fayalite 2024-12-03 05:06:43 +00:00
4422157db8 WIP adding enums to simulator
programmerjake commented on pull request libre-chip/fayalite#3 2024-12-02 04:36:05 +00:00
add a simulator

got simulating circuits with registers to work! only things left: enums and memories and a few kinds of expressions