|  | 15bc304bb6 | impl ToExpr for TargetBase | 2024-12-04 20:57:44 -08:00 |  | 
				
					
						|  | 4422157db8 | WIP adding enums to simulator | 2024-12-02 21:06:23 -08:00 |  | 
				
					
						|  | d3f52292a1 | test doc tests in CI | 2024-12-01 20:21:26 -08:00 |  | 
				
					
						|  | fd45465d35 | sim: add support for registers | 2024-12-01 20:14:13 -08:00 |  | 
				
					
						|  | 5e0548db26 | vcd: single bit signals have no spaces in their value changes | 2024-12-01 20:12:43 -08:00 |  | 
				
					
						|  | 12b3ba57f1 | add some ExprCastTo supertraits to ResetType to make generic code easier | 2024-12-01 20:10:25 -08:00 |  | 
				
					
						|  | 965fe53077 | deduce_resets: show more debugging info on assertion failure | 2024-12-01 20:09:17 -08:00 |  | 
				
					
						|  | 3abba7f9eb | simulating circuits with deduced resets works | 2024-11-27 23:52:07 -08:00 |  | 
				
					
						|  | 6446b71afd | deduce_resets works! | 2024-11-27 23:24:11 -08:00 |  | 
				
					
						|  | d36cf92d7f | make ToReset generic over the reset type | 2024-11-27 23:19:55 -08:00 |  | 
				
					
						|  | d744d85c66 | working on deduce_resets | 2024-11-27 01:31:18 -08:00 |  | 
				
					
						|  | 358cdd10c8 | add more expr casts | 2024-11-27 01:30:28 -08:00 |  | 
				
					
						|  | 9128a84284 | Merge remote-tracking branch 'origin/master' into adding-simulator | 2024-11-26 21:28:22 -08:00 |  | 
				
					
						|  | 546010739a | working on deduce_resets | 2024-11-26 21:26:56 -08:00 |  | 
				
					
						|  | 9b5f1218fd | make ClockDomain and Reg generic over reset type | 2024-11-26 20:47:03 -08:00 |  | 
				
					
						|  | 89d84551f8 | add ResetType to the list of recognized type bounds | 2024-11-26 18:52:03 -08:00 |  | 
				
					
						|  | c45624e3c2 | Fix SInt::for_value not accounting for sign bit for positive values Fixes: #4 | 2024-11-26 16:26:29 -08:00 |  | 
				
					
						|  | 7851bf545c | working on deduce_resets.rs | 2024-11-26 00:07:11 -08:00 |  | 
				
					
						|  | 3e3da53bd2 | working on deduce_resets | 2024-11-25 00:01:02 -08:00 |  | 
				
					
						|  | fa50930ff8 | update petgraph dependency to include UnionFind::new_set() | 2024-11-25 00:00:26 -08:00 |  | 
				
					
						|  | 9516fe03a1 | increase rust version in CI too | 2024-11-24 14:46:25 -08:00 |  | 
				
					
						|  | 52ab134673 | increase rust version to support omitting match arms with uninhabited types | 2024-11-24 14:41:39 -08:00 |  | 
				
					
						|  | 698b8adc23 | working on deduce_resets pass | 2024-11-24 14:39:32 -08:00 |  | 
				
					
						|  | 59be3bd645 | WIP working on implementing deduce_resets pass | 2024-11-24 03:44:31 -08:00 |  | 
				
					
						|  | 913baa37e9 | WIP adding deduce_resets pass | 2024-11-22 16:07:18 -08:00 |  | 
				
					
						|  | 11ddbc43c7 | writing VCD for combinatorial circuits works! | 2024-11-20 22:53:54 -08:00 |  | 
				
					
						|  | c4b5d00419 | WIP adding VCD output | 2024-11-20 22:53:54 -08:00 |  | 
				
					
						|  | 09aa9fbc78 | wire up simulator trace writing interface | 2024-11-20 22:53:54 -08:00 |  | 
				
					
						|  | 288a6b71b9 | WIP adding VCD output | 2024-11-20 22:53:54 -08:00 |  | 
				
					
						|  | 0095570f19 | simple combinatorial simulation works! | 2024-11-20 22:53:54 -08:00 |  | 
				
					
						|  | f54e55a143 | Simulation::settle_step() works for simple modules | 2024-11-20 22:53:54 -08:00 |  | 
				
					
						|  | a6e40839ac | simulator WIP: use petgraph for topological sort over assignments | 2024-11-20 22:53:54 -08:00 |  | 
				
					
						|  | 3106a6fff6 | working on simulator... | 2024-11-20 22:53:54 -08:00 |  | 
				
					
						|  | f338f37d3e | working on simulator | 2024-11-20 22:53:54 -08:00 |  | 
				
					
						|  | 277d3e0d4d | working on simulator | 2024-11-20 22:53:54 -08:00 |  | 
				
					
						|  | b288d6f8f2 | add missing copyright headers | 2024-11-20 22:53:54 -08:00 |  | 
				
					
						|  | 479d59b287 | WIP implementing simulator | 2024-11-20 22:53:54 -08:00 |  | 
				
					
						|  | 6f904148c4 | WIP adding simulator | 2024-11-20 22:53:54 -08:00 |  | 
				
					
						|  | 3ea0d98924 | always write formal cache json | 2024-11-20 22:51:40 -08:00 |  | 
				
					
						| 
								
								
									 Cesar Strauss | c1f1a8b749 | Add test module exercising formal verification. | 2024-11-20 18:29:39 -03:00 |  | 
				
					
						|  | 3d5d8c54b6 | add repository to cache key | 2024-10-30 20:55:02 -07:00 |  | 
				
					
						|  | ee15fd2b94 | support #[hdl] type aliases | 2024-10-30 20:47:10 -07:00 |  | 
				
					
						|  | 20cf0abbcc | fix using #[hdl] types like S<{ 1 + 2 }> | 2024-10-30 20:46:11 -07:00 |  | 
				
					
						|  | 5bd0de48b7 | change to version 0.2.1 | 2024-10-30 19:36:05 -07:00 |  | 
				
					
						|  | 0c9c48a066 | split out deps into separate workflow with better caching using deps.yml from cpu.git | 2024-10-17 21:05:18 -07:00 |  | 
				
					
						|  | cb17913004 | limit sby to one thread each since it seems not to respect job count in parallel mode | 2024-10-15 21:32:38 -07:00 |  | 
				
					
						|  | 42effd1132 | switch to using a make job server for managing test parallelism | 2024-10-15 20:32:33 -07:00 |  | 
				
					
						|  | 3d0f95cfe5 | formal: add workaround for wires disappearing because yosys optimizes them out | 2024-10-15 01:48:48 -07:00 |  | 
				
					
						|  | 3939ce2360 | add Bundle and Enum to prelude | 2024-10-14 17:47:58 -07:00 |  | 
				
					
						|  | d0229fbcfb | get #[hdl] struct S<A: KnownSize, B: KnownSize> to work | 2024-10-11 17:30:49 -07:00 |  |