forked from libre-chip/fayalite
writing VCD for combinatorial circuits works!
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parent
c4b5d00419
commit
11ddbc43c7
SSH key fingerprint:
SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
2 changed files with 92 additions and 20 deletions
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@ -3620,6 +3620,7 @@ struct SimulationImpl {
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uninitialized_inputs: HashSet<Target>,
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io_targets: HashMap<Target, CompiledValue<CanonicalType>>,
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made_initial_step: bool,
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needs_settle: bool,
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trace_decls: TraceModule,
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traces: Box<[SimTrace<BitVec>]>,
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trace_writers: Vec<TraceWriterState<DynTraceWriterDecls>>,
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@ -3669,6 +3670,7 @@ impl SimulationImpl {
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uninitialized_inputs: HashSet::new(),
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io_targets: HashMap::new(),
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made_initial_step: false,
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needs_settle: true,
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trace_decls: compiled.base_module.trace_decls,
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traces: Box::from_iter(compiled.traces.iter().map(
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|&SimTrace {
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@ -3804,9 +3806,7 @@ impl SimulationImpl {
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}
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#[track_caller]
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fn advance_time(&mut self, duration: SimDuration) {
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if !self.made_initial_step {
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self.settle_step();
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}
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self.settle_step();
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self.instant += duration;
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self.for_each_trace_writer_storing_error(|this, mut trace_writer_state| {
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match &mut trace_writer_state {
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@ -3825,6 +3825,9 @@ impl SimulationImpl {
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self.uninitialized_inputs.is_empty(),
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"didn't initialize all inputs",
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);
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if !self.needs_settle {
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return;
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}
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self.state.setup_call(0);
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self.state.run();
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if self.made_initial_step {
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@ -3833,6 +3836,7 @@ impl SimulationImpl {
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self.read_traces::<true>();
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}
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self.made_initial_step = true;
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self.needs_settle = false;
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self.for_each_trace_writer_storing_error(|this, trace_writer_state| {
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Ok(match trace_writer_state {
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TraceWriterState::Decls(trace_writer_decls) => TraceWriterState::Running(
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@ -3861,12 +3865,14 @@ impl SimulationImpl {
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panic!("simulator read/write expression must not have dynamic array indexes");
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}
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#[track_caller]
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fn read_bool_or_int<I: BoolOrIntType>(&self, io: Expr<I>) -> I::Value {
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fn read_bool_or_int<I: BoolOrIntType>(&mut self, io: Expr<I>) -> I::Value {
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let Some(target) = io.target() else {
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panic!("can't read from expression that's not a field/element of `Simulation::io()`");
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};
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let compiled_value = self.get_io(*target);
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if !self.made_initial_step {
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if self.made_initial_step {
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self.settle_step();
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} else {
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match target.flow() {
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Flow::Source => {
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panic!("can't read from an output before the simulation has made any steps");
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@ -3906,6 +3912,7 @@ impl SimulationImpl {
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if !self.made_initial_step {
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self.uninitialized_inputs.remove(&*target);
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}
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self.needs_settle = true;
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match compiled_value.range.len() {
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TypeLen::A_SMALL_SLOT => {
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self.state.small_slots[compiled_value.range.small_slots.start] =
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@ -3981,9 +3988,15 @@ impl SimulationImpl {
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retval
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}
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fn close(mut self) -> std::io::Result<()> {
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if self.made_initial_step {
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self.settle_step();
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}
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self.close_all_trace_writers()
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}
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fn flush_traces(&mut self) -> std::io::Result<()> {
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if self.made_initial_step {
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self.settle_step();
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}
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self.for_each_trace_writer_getting_error(
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|this, trace_writer: TraceWriterState<DynTraceWriterDecls>| match trace_writer {
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TraceWriterState::Decls(v) => {
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@ -4068,6 +4081,7 @@ impl<T: BundleType> fmt::Debug for Simulation<T> {
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uninitialized_inputs,
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io_targets,
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made_initial_step,
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needs_settle,
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trace_decls,
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traces,
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trace_writers,
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@ -4084,6 +4098,7 @@ impl<T: BundleType> fmt::Debug for Simulation<T> {
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)
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.field("io_targets", &SortedMapDebug(io_targets))
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.field("made_initial_step", made_initial_step)
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.field("needs_settle", needs_settle)
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.field("trace_decls", trace_decls)
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.field("traces", traces)
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.field("trace_writers", trace_writers)
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@ -4140,7 +4155,7 @@ impl<T: BundleType> Simulation<T> {
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self.sim_impl.advance_time(duration);
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}
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#[track_caller]
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pub fn read_bool_or_int<I: BoolOrIntType>(&self, io: Expr<I>) -> I::Value {
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pub fn read_bool_or_int<I: BoolOrIntType>(&mut self, io: Expr<I>) -> I::Value {
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self.sim_impl.read_bool_or_int(io)
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}
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#[track_caller]
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@ -120,6 +120,7 @@ fn test_connect_const() {
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},
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},
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made_initial_step: true,
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needs_settle: false,
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trace_decls: TraceModule {
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name: "connect_const",
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children: [
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@ -182,7 +183,6 @@ pub fn mod1() {
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connect(o, child);
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}
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#[cfg(todo)]
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#[hdl]
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#[test]
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fn test_mod1() {
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@ -195,10 +195,58 @@ fn test_mod1() {
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sim.advance_time(SimDuration::from_micros(1));
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sim.write_bool_or_int(sim.io().o.i, 0xA_hdl_u4);
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sim.advance_time(SimDuration::from_micros(1));
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sim.flush_traces().unwrap();
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let vcd = String::from_utf8(writer.take()).unwrap();
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println!("####### VCD:\n{vcd}\n#######");
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todo!("generated vcd is incorrect");
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if vcd != r#""# {
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if vcd
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!= r#"$timescale 1 ps $end
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$scope module mod1 $end
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$scope struct o $end
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$var wire 4 ! i $end
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$var wire 2 " o $end
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$var wire 2 # i2 $end
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$var wire 4 $ o2 $end
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$upscope $end
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$scope struct child $end
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$var wire 4 ) i $end
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$var wire 2 * o $end
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$var wire 2 + i2 $end
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$var wire 4 , o2 $end
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$upscope $end
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$scope module mod1_child $end
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$var wire 4 % i $end
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$var wire 2 & o $end
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$var wire 2 ' i2 $end
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$var wire 4 ( o2 $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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$dumpvars
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b11 !
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b11 "
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b10 #
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b1110 $
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b11 %
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b11 &
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b10 '
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b1110 (
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b11 )
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b11 *
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b10 +
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b1110 ,
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$end
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#1000000
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b1010 !
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b10 "
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b1111 $
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b1010 %
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b10 &
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b1111 (
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b1010 )
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b10 *
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b1111 ,
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#2000000
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"# {
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panic!();
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}
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let sim_debug = format!("{sim:#?}");
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@ -718,6 +766,7 @@ fn test_mod1() {
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},
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},
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made_initial_step: true,
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needs_settle: false,
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trace_decls: TraceModule {
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name: "mod1",
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children: [
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@ -887,7 +936,7 @@ fn test_mod1() {
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ty: UInt<4>,
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},
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state: 0xa,
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last_state: 0xa,
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last_state: 0x3,
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},
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SimTrace {
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id: TraceScalarId(1),
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@ -896,7 +945,7 @@ fn test_mod1() {
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ty: SInt<2>,
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},
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state: 0x2,
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last_state: 0x2,
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last_state: 0x3,
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},
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SimTrace {
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id: TraceScalarId(2),
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@ -914,7 +963,7 @@ fn test_mod1() {
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ty: UInt<4>,
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},
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state: 0xf,
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last_state: 0xf,
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last_state: 0xe,
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},
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SimTrace {
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id: TraceScalarId(4),
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@ -923,7 +972,7 @@ fn test_mod1() {
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ty: UInt<4>,
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},
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state: 0xa,
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last_state: 0xa,
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last_state: 0x3,
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},
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SimTrace {
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id: TraceScalarId(5),
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@ -932,7 +981,7 @@ fn test_mod1() {
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ty: SInt<2>,
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},
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state: 0x2,
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last_state: 0x2,
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last_state: 0x3,
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},
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SimTrace {
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id: TraceScalarId(6),
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@ -950,7 +999,7 @@ fn test_mod1() {
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ty: UInt<4>,
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},
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state: 0xf,
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last_state: 0xf,
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last_state: 0xe,
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},
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SimTrace {
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id: TraceScalarId(8),
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@ -959,7 +1008,7 @@ fn test_mod1() {
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ty: UInt<4>,
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},
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state: 0xa,
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last_state: 0xa,
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last_state: 0x3,
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},
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SimTrace {
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id: TraceScalarId(9),
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@ -968,7 +1017,7 @@ fn test_mod1() {
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ty: SInt<2>,
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},
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state: 0x2,
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last_state: 0x2,
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last_state: 0x3,
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},
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SimTrace {
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id: TraceScalarId(10),
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@ -986,11 +1035,19 @@ fn test_mod1() {
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ty: UInt<4>,
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},
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state: 0xf,
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last_state: 0xf,
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last_state: 0xe,
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},
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],
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trace_writers: [],
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instant: 0 s,
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trace_writers: [
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Running(
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VcdWriter {
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finished_init: true,
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timescale: 1 ps,
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..
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},
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),
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],
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instant: 2 μs,
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}"# {
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panic!();
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}
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