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fpga-support-and-arty-a7-100t

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v0.1.0

v0.2.0

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• def406ab52
  
  group all xilinx annotations together fpga-support-and-arty-a7-100t Jacob Lifshay 2025-10-16 04:53:58 -07:00
• a565be1b09
  
  do some clean up Jacob Lifshay 2025-10-16 04:32:56 -07:00
• 676c1e3b7d
  
  WIP adding annotations for generating the .xdc file for yosys-nextpnr-prjxray Jacob Lifshay 2025-10-15 04:11:23 -07:00
• 169be960f8
  
  generate Arty A7 100T .bit file for blinky example in CI Jacob Lifshay 2025-10-14 03:28:31 -07:00
• 2b52799f5c
  
  try building .bit file Jacob Lifshay 2025-10-10 17:58:25 -07:00
• 35f98f3229
  
  fix redirects Jacob Lifshay 2025-10-10 17:11:08 -07:00
• 8a63ea89d0
  
  WIP adding yosys-nextpnr-xray xilinx fpga toolchain -- blinky works on arty a7 100t (except for inverted reset) Jacob Lifshay 2025-10-09 02:22:11 -07:00
• 84c5978eaf
  
  WIP build Xilinx FPGA dependencies in CI Jacob Lifshay 2025-10-10 00:38:32 -07:00
• 42e3179a60
  
  change cache directory name to be fayalite-specific Jacob Lifshay 2025-10-08 03:25:24 -07:00
• 53ae3ff670
  
  mark create-unix-shell-script as incomplete in CLI Jacob Lifshay 2025-10-08 03:24:59 -07:00
• 7af9abfb6f
  
  switch to using new crate::build system Jacob Lifshay 2025-09-28 23:05:24 -07:00
• aacd05378f
  
  WIP converting from cli.rs to build/*.rs Jacob Lifshay 2025-09-24 22:28:25 -07:00
• 908ccef674
  
  added automatically-added dependencies; added caching for external jobs Jacob Lifshay 2025-09-24 00:40:23 -07:00
• 057670c12a
  
  WIP adding FPGA support -- build module should be complete Jacob Lifshay 2025-09-16 01:40:42 -07:00
• f8ac78abd6
  
  Remove extraneous #[automatically_derived] annotations that are causing warnings as reported by Tobias Jacob Lifshay 2025-10-15 04:17:47 -07:00
• 64ec6c0dcc
  
  switch to use server's new actions org Jacob Lifshay 2025-10-09 23:48:17 -07:00
• c06ef56482
  
  add NLnet grant 2024-12-324 to readme master Jacob Lifshay 2025-09-08 23:08:25 -07:00
• db9b1c202c
  
  add simulator support for sim-only values Jacob Lifshay 2025-09-01 04:46:24 -07:00
• d3dd66cbf0
  
  add rust-src component in CI for consistent error messages Jacob Lifshay 2025-09-08 22:16:49 -07:00
• b5b1ee866c
  
  converted to using get_state_part_kinds! Jacob Lifshay 2025-09-05 03:35:40 -07:00
• f0e3aef061
  
  add get_state_part_kinds! macro Jacob Lifshay 2025-09-04 21:41:12 -07:00
• 6d36698adf
  
  move public paths of sim::{Compiled,Compiler} to sim::compiler Jacob Lifshay 2025-08-26 19:23:21 -07:00
• e7e831cf00
  
  split out simulator compiler into a separate module Jacob Lifshay 2025-08-26 19:17:21 -07:00
• 4008c311bf
  
  format code after switching to edition 2024 Jacob Lifshay 2025-08-24 16:35:21 -07:00
• ef85d11327
  
  try to get actions to run Jacob Lifshay 2025-08-24 16:14:03 -07:00
• ae7c4be9dc
  
  remove get_many_mut since it was stabilized in std as get_disjoint_mut Jacob Lifshay 2025-08-24 15:52:36 -07:00
• 65f9ab32f4
  
  switch to edition 2024 Jacob Lifshay 2025-08-24 15:36:50 -07:00
• 67e66ac3bd
  
  upgrade to rust 1.89.0 Jacob Lifshay 2025-08-24 15:13:16 -07:00
• 668e714dc9
  
  actually test always_zero hasher Jacob Lifshay 2025-04-09 21:11:09 -07:00
• 88323a8c16
  
  run some tests with always_zero hasher Jacob Lifshay 2025-04-09 21:03:57 -07:00
• 91e1b619e8
  
  switch to petgraph 0.8.1 now that my PR was merged and released to crates.io Jacob Lifshay 2025-04-09 20:48:40 -07:00
• e2d2d4110b
  
  upgrade hashbrown to 0.15.2 Jacob Lifshay 2025-04-09 20:33:21 -07:00
• b1f9706e4e
  
  add custom hasher for testing Jacob Lifshay 2025-04-09 20:24:39 -07:00
• 4eda4366c8
  
  check types in debug mode in impl Debug for Expr, helping to catch bugs Jacob Lifshay 2025-04-09 20:23:19 -07:00
• 122c08d3cf
  
  add fake which for miri Jacob Lifshay 2025-04-09 20:21:43 -07:00
• b08a747e20
  
  switch to using type aliases for HashMap/HashSet to allow easily switching hashers Jacob Lifshay 2025-04-09 20:03:14 -07:00
• e0c9939147
  
  add test that SimValue can't be interned, since its PartialEq may ignore types Jacob Lifshay 2025-04-09 19:55:09 -07:00
• 07725ab489
  
  switch interning to use HashTable rather than HashMap Jacob Lifshay 2025-04-09 19:30:02 -07:00
• 36f1b9bbb6
  
  add derive(Debug) to all types that are interned Jacob Lifshay 2025-04-09 19:19:25 -07:00
• 9a1b047d2f
  
  change TypeIdMap to not use any unsafe code Jacob Lifshay 2025-04-09 16:25:56 -07:00
• 5967e812a2
  
  fix [SU]IntValue's PartialEq for interning Jacob Lifshay 2025-04-08 21:52:47 -07:00
• 001fd31451
  
  add UIntInRange[Inclusive][Type] Jacob Lifshay 2025-04-04 19:05:04 -07:00
• 57aae7b7fb
  
  implement [de]serializing BaseTypes, SimValues, and support PhantomConst<T> in #[hdl] struct S<T> Jacob Lifshay 2025-04-04 01:04:26 -07:00
• 6929352be7
  
  re-export bitvec and add types useful for simulation to the prelude Jacob Lifshay 2025-04-03 15:59:03 -07:00
• 62058dc141
  
  fix cargo doc warnings -- convert urls to auto links Jacob Lifshay 2025-04-01 22:22:54 -07:00
• c4b6a0fee6
  
  add support for #[hdl(sim)] enum_ty.Variant(value) and #[hdl(sim)] EnumTy::Variant(value) and non-sim variants too Jacob Lifshay 2025-04-01 22:05:42 -07:00
• 9092e45447
  
  fix #[hdl(sim)] match on enums Jacob Lifshay 2025-03-30 01:25:07 -07:00
• a40eaaa2da
  
  expand SimValue support Jacob Lifshay 2025-03-30 00:55:38 -07:00
• 5028401a5a
  
  change SimValue to contain and deref to a value and not just contain bits Jacob Lifshay 2025-03-27 23:44:36 -07:00
• e0f978fbb6
  
  silence unused m variable warning in #[hdl_module] with an empty body. Jacob Lifshay 2025-03-27 23:17:28 -07:00
• ec3a61513b
  
  simulator read/write types must be passive Jacob Lifshay 2025-03-27 23:03:44 -07:00
• fdc73b5f3b
  
  add ripple counter test to test simulating alternating circuits and extern modules Jacob Lifshay 2025-03-25 18:53:46 -07:00
• a115585d5a
  
  simulator: allow external module generators to wait for value changes and/or clock edges Jacob Lifshay 2025-03-25 18:26:48 -07:00
• ab9ff4f2db
  
  simplify setting an extern module simulation Jacob Lifshay 2025-03-21 17:08:29 -07:00
• d1bd176b28
  
  implement simulation of extern modules Jacob Lifshay 2025-03-19 17:11:41 -07:00
• 920d8d875f
  
  add some missing #[track_caller] Jacob Lifshay 2025-03-19 17:10:51 -07:00
• d453755bb2
  
  add ExprPartialEq/ExprPartialOrd impls for PhantomConst Jacob Lifshay 2025-03-10 19:40:03 -07:00
• 450e1004b6
  
  fix using fayalite as a dependency Jacob Lifshay 2025-03-09 23:14:14 -07:00
• c0c5b550bc
  
  add PhantomConst Jacob Lifshay 2025-03-09 21:03:47 -07:00
• 2fa0ea6192
  
  make FillInDefaultedGenerics work with Sizes and not just Types Jacob Lifshay 2025-03-09 20:59:21 -07:00
• bd75fdfefd
  
  add efficient prefix-sums and reductions Jacob Lifshay 2025-03-02 23:04:17 -08:00
• 50c86e18dc
  
  add Expr<ArrayType<T, Len>>: IntoIterator and Expr<Array<T>>: FromIterator<T> Jacob Lifshay 2025-03-02 16:11:05 -08:00
• 60734cc9d1
  
  switch CI to use mirrors Jacob Lifshay 2025-03-02 17:43:29 -08:00
• 3458c21f44
  
  add #[hdl(cmp_eq)] to implement HdlPartialEq automatically Jacob Lifshay 2025-02-16 20:48:16 -08:00
• 43797db36e
  
  sort custom keywords Jacob Lifshay 2025-02-16 20:46:54 -08:00
• cdd84953d0
  
  support unknown trait bounds in type parameters Jacob Lifshay 2025-02-13 18:35:30 -08:00
• 86a1bb46be
  
  add #[hdl] let destructuring and, while at it, tuple patterns Jacob Lifshay 2025-02-10 22:49:41 -08:00
• 209d5b5fe1
  
  fix broken doc links Jacob Lifshay 2025-02-10 22:49:16 -08:00
• d4ea826051
  
  sim: fix "label address not set" bug when the last Assignment is conditional Jacob Lifshay 2025-01-15 19:04:40 -08:00
• 404a2ee043
  
  tests/sim: add test_array_rw Jacob Lifshay 2025-01-12 21:36:54 -08:00
• e3a2ccd41c
  
  properly handle duplicate names in vcd Jacob Lifshay 2025-01-09 22:52:22 -08:00
• 3771cea78e
  
  Gather the FIFO debug ports in a bundle Cesar Strauss 2024-12-29 13:17:24 -03:00
• dcf865caec
  
  Add assertions and debug ports in order for the FIFO to pass induction Cesar Strauss 2024-12-29 13:12:58 -03:00
• 31d01046a8
  
  Initial queue formal proof based on one-entry FIFO equivalence Cesar Strauss 2024-12-29 13:04:01 -03:00
• c16726cee6
  
  fix #[hdl]/#[hdl_module] attributes getting the wrong hygiene when processing #[cfg]s Jacob Lifshay 2024-12-29 00:48:15 -08:00
• b63676d0ca
  
  add test for cfgs Jacob Lifshay 2024-12-27 04:01:53 -08:00
• 7005fa3330
  
  implement handling #[cfg] and #[cfg_attr] in proc macro inputs Jacob Lifshay 2024-12-27 04:02:39 -08:00
• 2ab8428062
  
  upgrade syn version Jacob Lifshay 2024-12-28 23:34:46 -08:00
• 9b06019bf5
  
  make sim::Compiler not print things to stdout unless you ask for it Jacob Lifshay 2024-12-18 21:15:09 -08:00
• 36bad52978
  
  sim: fix sim.write to struct Jacob Lifshay 2024-12-18 20:50:50 -08:00
• 21c73051ec
  
  sim: add SimValue and reading/writing more than just a scalar Jacob Lifshay 2024-12-18 01:39:35 -08:00
• 304d8da0e8
  
  Merge remote-tracking branch 'origin/master' into adding-simulator Jacob Lifshay 2024-12-13 15:06:45 -08:00
• 2af38de900
  
  add more memory tests Jacob Lifshay 2024-12-13 15:04:48 -08:00
• c756aeec70
  
  tests/sim: add test for memory rw port Jacob Lifshay 2024-12-12 20:50:41 -08:00
• 903ca1bf30
  
  sim: simple memory test works! Jacob Lifshay 2024-12-12 19:47:57 -08:00
• 8d030ac65d
  
  sim/interpreter: add addresses to instruction listing Jacob Lifshay 2024-12-12 16:25:38 -08:00
• 562c479b62
  
  sim/interpreter: fix StatePartLayout name in debug output Jacob Lifshay 2024-12-12 15:06:17 -08:00
• 393f78a14d
  
  sim: add WIP memory test Jacob Lifshay 2024-12-11 23:28:15 -08:00
• 8616ee4737
  
  tests/sim: test_enums works! Jacob Lifshay 2024-12-11 00:01:04 -08:00
• 5087f16099
  
  sim: fix assignments graph by properly including conditions as assignment inputs Jacob Lifshay 2024-12-11 00:00:21 -08:00
• 6b31e6d515
  
  sim: add .dot output for Assignments graph for debugging Jacob Lifshay 2024-12-10 23:40:33 -08:00
• 564ccb30bc
  
  sim/vcd: fix variable identifiers to follow verilog rules Jacob Lifshay 2024-12-10 23:39:17 -08:00
• ca759168ff
  
  tests/sim: add WIP test for enums Jacob Lifshay 2024-12-10 23:37:26 -08:00
• e4cf66adf8
  
  sim: implement memories, still needs testing Jacob Lifshay 2024-12-09 23:03:01 -08:00
• cd0dd7b7ee
  
  change memory write latency to NonZeroUsize to match read latency being usize Jacob Lifshay 2024-12-09 23:01:40 -08:00
• 2e7d685dc7 add module exercising formal verification of memories Cesar Strauss 2024-12-08 15:25:21 -03:00
• 9654167ca3
  
  sim: WIP working on memory Jacob Lifshay 2024-12-06 15:53:34 -08:00
• 3ed7827485
  
  sim: WIP adding memory support Jacob Lifshay 2024-12-05 21:35:23 -08:00
• e504cfebfe
  
  add BoolOrIntType::copy_bits_from_bigint_wrapping and take BigInt arguments by reference Jacob Lifshay 2024-12-05 20:27:50 -08:00
• 9f42cab471
  
  change to version 0.3.0 for breaking change Jacob Lifshay 2024-12-05 20:26:28 -08:00