implement simple_uart::simple_uart

add test for simple_uart::receiver
add main_memory_and_io::simple_uart::receiver* and test for receiver_no_queue
2026-02-26 21:34:58 -08:00 · 2026-02-26 17:48:42 -08:00 · 2026-02-25 18:05:50 -08:00 · 2026-02-25 15:22:34 -08:00 · 2026-02-25 00:08:42 -08:00 · 2026-02-25 00:08:42 -08:00
55 changed files with 1059500 additions and 32874 deletions
--- a/.forgejo/workflows/deps.yml
+++ b/.forgejo/workflows/deps.yml
@ -1,77 +0,0 @@
-# SPDX-License-Identifier: LGPL-3.0-or-later
-# See Notices.txt for copyright information
-on:
-  workflow_call:
-    outputs:
-      cache-primary-key:
-        value: ${{ jobs.deps.outputs.cache-primary-key }}
-
-jobs:
-  deps:
-    runs-on: debian-12
-    outputs:
-      cache-primary-key: ${{ steps.restore-deps.outputs.cache-primary-key }}
-    steps:
-      - uses: https://git.libre-chip.org/mirrors/checkout@v3
-        with:
-          fetch-depth: 0
-      - uses: https://git.libre-chip.org/mirrors/cache/restore@v3
-        id: restore-deps
-        with:
-          path: deps
-          key: ${{ github.repository }}-deps-${{ runner.os }}-${{ hashFiles('.forgejo/workflows/deps.yml') }}
-          lookup-only: true
-      - name: Install Apt packages
-        if: steps.restore-deps.outputs.cache-hit != 'true'
-        run: |
-          apt-get update -qq
-          apt-get install -qq \
-            bison \
-            build-essential \
-            ccache \
-            clang \
-            cvc5 \
-            flex \
-            gawk \
-            g++ \
-            git \
-            libboost-filesystem-dev \
-            libboost-python-dev \
-            libboost-system-dev \
-            libffi-dev \
-            libreadline-dev \
-            lld \
-            pkg-config \
-            python3 \
-            python3-click \
-            tcl-dev \
-            zlib1g-dev
-      - name: Install Firtool
-        if: steps.restore-deps.outputs.cache-hit != 'true'
-        run: |
-          mkdir -p deps
-          wget -O deps/firrtl.tar.gz https://github.com/llvm/circt/releases/download/firtool-1.86.0/firrtl-bin-linux-x64.tar.gz
-          sha256sum -c - <<<'bf6f4ab18ae76f135c944efbd81e25391c31c1bd0617c58ab0592640abefee14  deps/firrtl.tar.gz'
-          tar -C deps -xvaf deps/firrtl.tar.gz
-          rm -rf deps/firtool
-          mv deps/firtool-1.86.0 deps/firtool
-      - name: Get SymbiYosys
-        if: steps.restore-deps.outputs.cache-hit != 'true'
-        run: |
-          git clone --depth=1 --branch=yosys-0.45 https://git.libre-chip.org/mirrors/sby deps/sby
-      - name: Build Z3
-        if: steps.restore-deps.outputs.cache-hit != 'true'
-        run: |
-          git clone --depth=1 --recursive --branch=z3-4.13.3 https://git.libre-chip.org/mirrors/z3 deps/z3
-          (cd deps/z3; PYTHON=python3 ./configure --prefix=/usr/local)
-          make -C deps/z3/build -j"$(nproc)"
-      - name: Build Yosys
-        if: steps.restore-deps.outputs.cache-hit != 'true'
-        run: |
-          git clone --depth=1 --recursive --branch=0.45 https://git.libre-chip.org/mirrors/yosys deps/yosys
-          make -C deps/yosys -j"$(nproc)"
-      - uses: https://git.libre-chip.org/mirrors/cache/save@v3
-        if: steps.restore-deps.outputs.cache-hit != 'true'
-        with:
-          path: deps
-          key: ${{ steps.restore-deps.outputs.cache-primary-key }}
--- a/.forgejo/workflows/test.yml
+++ b/.forgejo/workflows/test.yml
@ -3,57 +3,18 @@
 on: [push, pull_request]

 jobs:
-  deps:
-    runs-on: debian-12
-    uses: ./.forgejo/workflows/deps.yml
  test:
    runs-on: debian-12
-    needs: deps
+    container:
+      image: git.libre-chip.org/libre-chip/fayalite-deps:latest
    steps:
-      - uses: https://git.libre-chip.org/mirrors/checkout@v3
+      - uses: actions/checkout@v3
        with:
          fetch-depth: 0
      - run: |
          scripts/check-copyright.sh
-      - run: |
-          apt-get update -qq
-          apt-get install -qq \
-            bison \
-            build-essential \
-            ccache \
-            clang \
-            cvc5 \
-            flex \
-            gawk \
-            git \
-            libboost-filesystem-dev \
-            libboost-python-dev \
-            libboost-system-dev \
-            libffi-dev \
-            libreadline-dev \
-            lld \
-            pkg-config \
-            python3 \
-            python3-click \
-            tcl-dev \
-            z3 \
-            zlib1g-dev
-      - run: |
-          curl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs | sh -s -- -y --default-toolchain 1.89.0
-          source "$HOME/.cargo/env"
-          echo "$PATH" >> "$GITHUB_PATH"
-      - uses: https://git.libre-chip.org/mirrors/cache/restore@v3
-        with:
-          path: deps
-          key: ${{ needs.deps.outputs.cache-primary-key }}
-          fail-on-cache-miss: true
-      - run: |
-          make -C deps/z3/build install
-          make -C deps/sby install
-          make -C deps/yosys install
-          export PATH="$(realpath deps/firtool/bin):$PATH"
-          echo "$PATH" >> "$GITHUB_PATH"
      - uses: https://git.libre-chip.org/mirrors/rust-cache@v2
        with:
          save-if: ${{ github.ref == 'refs/heads/master' }}
+      - run: rustup override set 1.93.0
      - run: cargo test
--- a/.gitattributes
+++ b/.gitattributes
@ -0,0 +1,3 @@
+# SPDX-License-Identifier: LGPL-3.0-or-later
+# See Notices.txt for copyright information
+*.vcd linguist-generated=true
--- a/.gitignore
+++ b/.gitignore
@ -1,3 +1,4 @@
 # SPDX-License-Identifier: LGPL-3.0-or-later
 # See Notices.txt for copyright information
 /target
+OPF_PowerISA_v3.1C.pdf
--- a/Cargo.lock
+++ b/Cargo.lock
@ -1,17 +1,20 @@
 # This file is automatically @generated by Cargo.
 # It is not intended for manual editing.
-version = 3
+version = 4

 [[package]]
-name = "ahash"
-version = "0.8.11"
+name = "adler2"
+version = "2.0.1"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "e89da841a80418a9b391ebaea17f5c112ffaaa96f621d2c285b5174da76b9011"
+checksum = "320119579fcad9c21884f5c4861d16174d0e06250625266f50fe6898340abefa"
+
+[[package]]
+name = "aho-corasick"
+version = "1.1.4"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "ddd31a130427c27518df266943a5308ed92d4b226cc639f5a8f1002816174301"
 dependencies = [
- "cfg-if",
- "once_cell",
- "version_check",
- "zerocopy",
+ "memchr",
 ]

 [[package]]
@ -93,6 +96,36 @@ version = "0.2.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "4c7f02d4ea65f2c1853089ffd8d2787bdbc63de2f0d29dedbcf8ccdfa0ccd4cf"

+[[package]]
+name = "base16ct"
+version = "1.0.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "fd307490d624467aa6f74b0eabb77633d1f758a7b25f12bceb0b22e08d9726f6"
+
+[[package]]
+name = "base64"
+version = "0.22.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "72b3254f16251a8381aa12e40e3c4d2f0199f8c6508fbecb9d91f575e0fbb8c6"
+
+[[package]]
+name = "bindgen"
+version = "0.71.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "5f58bf3d7db68cfbac37cfc485a8d711e87e064c3d0fe0435b92f7a407f9d6b3"
+dependencies = [
+ "bitflags",
+ "cexpr",
+ "clang-sys",
+ "itertools",
+ "proc-macro2",
+ "quote",
+ "regex",
+ "rustc-hash",
+ "shlex",
+ "syn",
+]
+
 [[package]]
 name = "bitflags"
 version = "2.6.0"
@ -136,20 +169,47 @@ dependencies = [
 ]

 [[package]]
-name = "cc"
-version = "1.1.28"
+name = "bytes"
+version = "1.11.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "2e80e3b6a3ab07840e1cae9b0666a63970dc28e8ed5ffbcdacbfc760c281bfc1"
+checksum = "b35204fbdc0b3f4446b89fc1ac2cf84a8a68971995d0bf2e925ec7cd960f9cb3"
+
+[[package]]
+name = "cc"
+version = "1.2.51"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "7a0aeaff4ff1a90589618835a598e545176939b97874f7abc7851caa0618f203"
 dependencies = [
+ "find-msvc-tools",
 "shlex",
 ]

+[[package]]
+name = "cexpr"
+version = "0.6.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "6fac387a98bb7c37292057cffc56d62ecb629900026402633ae9160df93a8766"
+dependencies = [
+ "nom",
+]
+
 [[package]]
 name = "cfg-if"
 version = "1.0.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "baf1de4339761588bc0619e3cbc0120ee582ebb74b53b4efbf79117bd2da40fd"

+[[package]]
+name = "clang-sys"
+version = "1.8.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "0b023947811758c97c59bf9d1c188fd619ad4718dcaa767947df1cadb14f39f4"
+dependencies = [
+ "glob",
+ "libc",
+ "libloading",
+]
+
 [[package]]
 name = "clap"
 version = "4.5.20"
@ -172,6 +232,15 @@ dependencies = [
 "strsim",
 ]

+[[package]]
+name = "clap_complete"
+version = "4.5.59"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "2348487adcd4631696ced64ccdb40d38ac4d31cae7f2eec8817fcea1b9d1c43c"
+dependencies = [
+ "clap",
+]
+
 [[package]]
 name = "clap_derive"
 version = "4.5.18"
@ -206,7 +275,17 @@ checksum = "7c74b8349d32d297c9134b8c88677813a227df8f779daa29bfc29c183fe3dca6"
 name = "cpu"
 version = "0.1.0"
 dependencies = [
+ "base16ct 1.0.0",
 "fayalite",
+ "hex-literal",
+ "parse_powerisa_pdf",
+ "regex",
+ "roxmltree",
+ "serde",
+ "sha2",
+ "simple-mermaid",
+ "ureq",
+ "which",
 ]

 [[package]]
@ -218,6 +297,15 @@ dependencies = [
 "libc",
 ]

+[[package]]
+name = "crc32fast"
+version = "1.5.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "9481c1c90cbf2ac953f07c8d4a58aa3945c425b7185c9154d67a65e4230da511"
+dependencies = [
+ "cfg-if",
+]
+
 [[package]]
 name = "crypto-common"
 version = "0.1.6"
@ -273,12 +361,12 @@ checksum = "5443807d6dff69373d433ab9ef5378ad8df50ca6298caf15de6e52e24aaf54d5"

 [[package]]
 name = "errno"
-version = "0.3.9"
+version = "0.3.14"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "534c5cf6194dfab3db3242765c03bbe257cf92f22b38f6bc0c58d59108a820ba"
+checksum = "39cab71617ae0d63f51a36d69f866391735b51691dbda63cf6f96d042b63efeb"
 dependencies = [
 "libc",
- "windows-sys 0.52.0",
+ "windows-sys 0.61.2",
 ]

 [[package]]
@ -300,23 +388,27 @@ checksum = "e8c02a5121d4ea3eb16a80748c74f5549a5665e4c21333c6098f283870fbdea6"
 [[package]]
 name = "fayalite"
 version = "0.3.0"
-source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#bd75fdfefd642f6dd2210cfb003fa63f9dce114e"
+source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#dbed947408ddb6a4bcc734c79a60ab87b2f97cc6"
 dependencies = [
+ "base64",
 "bitvec",
 "blake3",
 "clap",
+ "clap_complete",
 "ctor",
 "eyre",
 "fayalite-proc-macros",
 "fayalite-visit-gen",
- "hashbrown",
+ "hashbrown 0.15.5",
 "jobslot",
 "num-bigint",
 "num-traits",
- "os_pipe",
+ "once_cell",
+ "ordered-float",
 "petgraph",
 "serde",
 "serde_json",
+ "sha2",
 "tempfile",
 "vec_map",
 "which",
@ -325,7 +417,7 @@ dependencies = [
 [[package]]
 name = "fayalite-proc-macros"
 version = "0.3.0"
-source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#bd75fdfefd642f6dd2210cfb003fa63f9dce114e"
+source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#dbed947408ddb6a4bcc734c79a60ab87b2f97cc6"
 dependencies = [
 "fayalite-proc-macros-impl",
 ]
@ -333,9 +425,9 @@ dependencies = [
 [[package]]
 name = "fayalite-proc-macros-impl"
 version = "0.3.0"
-source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#bd75fdfefd642f6dd2210cfb003fa63f9dce114e"
+source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#dbed947408ddb6a4bcc734c79a60ab87b2f97cc6"
 dependencies = [
- "base16ct",
+ "base16ct 0.2.0",
 "num-bigint",
 "prettyplease",
 "proc-macro2",
@ -348,7 +440,7 @@ dependencies = [
 [[package]]
 name = "fayalite-visit-gen"
 version = "0.3.0"
-source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#bd75fdfefd642f6dd2210cfb003fa63f9dce114e"
+source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#dbed947408ddb6a4bcc734c79a60ab87b2f97cc6"
 dependencies = [
 "indexmap",
 "prettyplease",
@ -360,12 +452,34 @@ dependencies = [
 "thiserror",
 ]

+[[package]]
+name = "find-msvc-tools"
+version = "0.1.6"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "645cbb3a84e60b7531617d5ae4e57f7e27308f6445f5abf653209ea76dec8dff"
+
 [[package]]
 name = "fixedbitset"
 version = "0.5.7"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "1d674e81391d1e1ab681a28d99df07927c6d4aa5b027d7da16ba32d1d21ecd99"

+[[package]]
+name = "flate2"
+version = "1.1.5"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "bfe33edd8e85a12a67454e37f8c75e730830d83e313556ab9ebf9ee7fbeb3bfb"
+dependencies = [
+ "crc32fast",
+ "miniz_oxide",
+]
+
+[[package]]
+name = "foldhash"
+version = "0.1.5"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "d9c4f5dac5e15c24eb999c26181a6ca40b39fe946cbe4c263c7209467bc83af2"
+
 [[package]]
 name = "funty"
 version = "2.0.0"
@ -384,9 +498,9 @@ dependencies = [

 [[package]]
 name = "getrandom"
-version = "0.2.15"
+version = "0.2.16"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "c4567c8db10ae91089c99af84c68c38da3ec2f087c3f82960bcdbf3656b6f4d7"
+checksum = "335ff9f135e4384c8150d6f27c6daed433577f86b4750418338c01a1a2528592"
 dependencies = [
 "cfg-if",
 "libc",
@ -394,21 +508,52 @@ dependencies = [
 ]

 [[package]]
-name = "hashbrown"
-version = "0.14.5"
+name = "getrandom"
+version = "0.3.4"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "e5274423e17b7c9fc20b6e7e208532f9b19825d82dfd615708b70edd83df41f1"
+checksum = "899def5c37c4fd7b2664648c28120ecec138e4d395b459e5ca34f9cce2dd77fd"
 dependencies = [
- "ahash",
- "allocator-api2",
+ "cfg-if",
+ "libc",
+ "r-efi",
+ "wasip2",
 ]

+[[package]]
+name = "glob"
+version = "0.3.3"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "0cc23270f6e1808e30a928bdc84dea0b9b4136a8bc82338574f23baf47bbd280"
+
+[[package]]
+name = "hashbrown"
+version = "0.15.5"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "9229cfe53dfd69f0609a49f65461bd93001ea1ef889cd5529dd176593f5338a1"
+dependencies = [
+ "allocator-api2",
+ "equivalent",
+ "foldhash",
+]
+
+[[package]]
+name = "hashbrown"
+version = "0.16.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "841d1cc9bed7f9236f321df977030373f4a4163ae1a7dbfe1a51a2c1a51d9100"
+
 [[package]]
 name = "heck"
 version = "0.5.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "2304e00983f87ffb38b55b444b5e3b60a884b5d30c0fca7d82fe33449bbe55ea"

+[[package]]
+name = "hex-literal"
+version = "1.1.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "e712f64ec3850b98572bffac52e2c6f282b29fe6c5fa6d42334b30be438d95c1"
+
 [[package]]
 name = "home"
 version = "0.5.9"
@ -418,6 +563,22 @@ dependencies = [
 "windows-sys 0.52.0",
 ]

+[[package]]
+name = "http"
+version = "1.4.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "e3ba2a386d7f85a81f119ad7498ebe444d2e22c2af0b86b069416ace48b3311a"
+dependencies = [
+ "bytes",
+ "itoa",
+]
+
+[[package]]
+name = "httparse"
+version = "1.10.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "6dbf3de79e51f3d586ab4cb9d5c3e2c14aa28ed23d180cf89b4df0454a69cc87"
+
 [[package]]
 name = "indenter"
 version = "0.3.3"
@ -426,13 +587,14 @@ checksum = "ce23b50ad8242c51a442f3ff322d56b02f08852c77e4c0b4d3fd684abc89c683"

 [[package]]
 name = "indexmap"
-version = "2.5.0"
+version = "2.13.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "68b900aa2f7301e21c36462b170ee99994de34dff39a4a6a528e80e7376d07e5"
+checksum = "7714e70437a7dc3ac8eb7e6f8df75fd8eb422675fc7678aff7364301092b1017"
 dependencies = [
 "equivalent",
- "hashbrown",
+ "hashbrown 0.16.1",
 "serde",
+ "serde_core",
 ]

 [[package]]
@ -441,6 +603,15 @@ version = "1.70.1"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "7943c866cc5cd64cbc25b2e01621d07fa8eb2a1a23160ee81ce38704e97b8ecf"

+[[package]]
+name = "itertools"
+version = "0.13.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "413ee7dfc52ee1a4949ceeb7dbc8a33f2d6c088194d9f922fb8318faf1f01186"
+dependencies = [
+ "either",
+]
+
 [[package]]
 name = "itoa"
 version = "1.0.11"
@ -449,23 +620,39 @@ checksum = "49f1f14873335454500d59611f1cf4a4b0f786f9ac11f4312a78e4cf2566695b"

 [[package]]
 name = "jobslot"
-version = "0.2.19"
+version = "0.2.23"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "fe10868679d7a24c2c67d862d0e64a342ce9aef7cdde9ce8019bd35d353d458d"
+checksum = "58715c67c327da7f1558708348d68c207fd54900c4ae0529e29305d04d795b8c"
 dependencies = [
 "cfg-if",
 "derive_destructure2",
- "getrandom",
+ "getrandom 0.3.4",
 "libc",
 "scopeguard",
- "windows-sys 0.59.0",
+ "windows-sys 0.61.2",
 ]

 [[package]]
 name = "libc"
-version = "0.2.159"
+version = "0.2.180"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "561d97a539a36e26a9a5fad1ea11a3039a67714694aaa379433e580854bc3dc5"
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 [[package]]
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 checksum = "78b3ae25bc7c8c38cec158d1f2757ee79e9b3740fbc7ccf0e59e4b08d793fa89"

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+
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 checksum = "78ca9ab1a0babb1e7d5695e3530886289c18cf2f87ec19a575a0abdce112e3a3"

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+dependencies = [
+ "adler2",
+ "simd-adler32",
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+
+[[package]]
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+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "13e9a0d4e844ab50315d43312f3d62f72c77205b07c8ee21cbd4b52bdc2a9910"
+dependencies = [
+ "bindgen",
+ "cc",
+ "pkg-config",
+ "regex",
+ "zerocopy",
+]
+
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+dependencies = [
+ "memchr",
+ "minimal-lexical",
+]
+
 [[package]]
 name = "num-bigint"
 version = "0.4.6"
@ -509,29 +741,56 @@ dependencies = [

 [[package]]
 name = "once_cell"
-version = "1.20.2"
+version = "1.21.3"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "1261fe7e33c73b354eab43b1273a57c8f967d0391e80353e51f764ac02cf6775"
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 [[package]]
-name = "os_pipe"
-version = "1.2.1"
+name = "ordered-float"
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-checksum = "5ffd2b0a5634335b135d5728d84c5e0fd726954b87111f7506a61c502280d982"
+checksum = "7f4779c6901a562440c3786d08192c6fbda7c1c2060edd10006b05ee35d10f2d"
 dependencies = [
- "libc",
- "windows-sys 0.59.0",
+ "num-traits",
+ "rand",
+ "serde",
 ]

+[[package]]
+name = "parse_powerisa_pdf"
+version = "0.1.0"
+source = "git+https://git.libre-chip.org/libre-chip/parse_powerisa_pdf.git?branch=master#38a1fb328bd44f26389c28fbf66716154f4113dc"
+dependencies = [
+ "indexmap",
+ "libm",
+ "mupdf-sys",
+ "quick-xml",
+]
+
+[[package]]
+name = "percent-encoding"
+version = "2.3.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "9b4f627cb1b25917193a259e49bdad08f671f8d9708acfd5fe0a8c1455d87220"
+
 [[package]]
 name = "petgraph"
-version = "0.6.5"
-source = "git+https://github.com/programmerjake/petgraph.git?rev=258ea8071209a924b73fe96f9f87a3b7b45cbc9f#258ea8071209a924b73fe96f9f87a3b7b45cbc9f"
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+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "8701b58ea97060d5e5b155d383a69952a60943f0e6dfe30b04c287beb0b27455"
 dependencies = [
 "fixedbitset",
+ "hashbrown 0.15.5",
 "indexmap",
+ "serde",
 ]

+[[package]]
+name = "pkg-config"
+version = "0.3.32"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "7edddbd0b52d732b21ad9a5fab5c704c14cd949e5e9a1ec5929a24fded1b904c"
+
 [[package]]
 name = "prettyplease"
 version = "0.2.22"
@ -551,6 +810,15 @@ dependencies = [
 "unicode-ident",
 ]

+[[package]]
+name = "quick-xml"
+version = "0.38.4"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "b66c2058c55a409d601666cffe35f04333cf1013010882cec174a7467cd4e21c"
+dependencies = [
+ "memchr",
+]
+
 [[package]]
 name = "quote"
 version = "1.0.37"
@ -560,12 +828,95 @@ dependencies = [
 "proc-macro2",
 ]

+[[package]]
+name = "r-efi"
+version = "5.3.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "69cdb34c158ceb288df11e18b4bd39de994f6657d83847bdffdbd7f346754b0f"
+
 [[package]]
 name = "radium"
 version = "0.7.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "dc33ff2d4973d518d823d61aa239014831e521c75da58e3df4840d3f47749d09"

+[[package]]
+name = "rand"
+version = "0.8.5"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "34af8d1a0e25924bc5b7c43c079c942339d8f0a8b57c39049bef581b46327404"
+dependencies = [
+ "rand_core",
+ "serde",
+]
+
+[[package]]
+name = "rand_core"
+version = "0.6.4"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "ec0be4795e2f6a28069bec0b5ff3e2ac9bafc99e6a9a7dc3547996c5c816922c"
+dependencies = [
+ "serde",
+]
+
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+version = "1.12.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "843bc0191f75f3e22651ae5f1e72939ab2f72a4bc30fa80a066bd66edefc24d4"
+dependencies = [
+ "aho-corasick",
+ "memchr",
+ "regex-automata",
+ "regex-syntax",
+]
+
+[[package]]
+name = "regex-automata"
+version = "0.4.13"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "5276caf25ac86c8d810222b3dbb938e512c55c6831a10f3e6ed1c93b84041f1c"
+dependencies = [
+ "aho-corasick",
+ "memchr",
+ "regex-syntax",
+]
+
+[[package]]
+name = "regex-syntax"
+version = "0.8.8"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "7a2d987857b319362043e95f5353c0535c1f58eec5336fdfcf626430af7def58"
+
+[[package]]
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+version = "0.17.14"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "a4689e6c2294d81e88dc6261c768b63bc4fcdb852be6d1352498b114f61383b7"
+dependencies = [
+ "cc",
+ "cfg-if",
+ "getrandom 0.2.16",
+ "libc",
+ "untrusted",
+ "windows-sys 0.52.0",
+]
+
+[[package]]
+name = "roxmltree"
+version = "0.21.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "f1964b10c76125c36f8afe190065a4bf9a87bf324842c05701330bba9f1cacbb"
+dependencies = [
+ "memchr",
+]
+
+[[package]]
+name = "rustc-hash"
+version = "2.1.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "357703d41365b4b27c590e3ed91eabb1b663f07c4c084095e60cbed4362dff0d"
+
 [[package]]
 name = "rustix"
 version = "0.38.37"
@ -579,6 +930,41 @@ dependencies = [
 "windows-sys 0.52.0",
 ]

+[[package]]
+name = "rustls"
+version = "0.23.36"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "c665f33d38cea657d9614f766881e4d510e0eda4239891eea56b4cadcf01801b"
+dependencies = [
+ "log",
+ "once_cell",
+ "ring",
+ "rustls-pki-types",
+ "rustls-webpki",
+ "subtle",
+ "zeroize",
+]
+
+[[package]]
+name = "rustls-pki-types"
+version = "1.13.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "21e6f2ab2928ca4291b86736a8bd920a277a399bba1589409d72154ff87c1282"
+dependencies = [
+ "zeroize",
+]
+
+[[package]]
+name = "rustls-webpki"
+version = "0.103.8"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "2ffdfa2f5286e2247234e03f680868ac2815974dc39e00ea15adc445d0aafe52"
+dependencies = [
+ "ring",
+ "rustls-pki-types",
+ "untrusted",
+]
+
 [[package]]
 name = "ryu"
 version = "1.0.18"
@ -593,18 +979,28 @@ checksum = "94143f37725109f92c262ed2cf5e59bce7498c01bcc1502d7b9afe439a4e9f49"

 [[package]]
 name = "serde"
-version = "1.0.210"
+version = "1.0.228"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "c8e3592472072e6e22e0a54d5904d9febf8508f65fb8552499a1abc7d1078c3a"
+checksum = "9a8e94ea7f378bd32cbbd37198a4a91436180c5bb472411e48b5ec2e2124ae9e"
+dependencies = [
+ "serde_core",
+ "serde_derive",
+]
+
+[[package]]
+name = "serde_core"
+version = "1.0.228"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "41d385c7d4ca58e59fc732af25c3983b67ac852c1a25000afe1175de458b67ad"
 dependencies = [
 "serde_derive",
 ]

 [[package]]
 name = "serde_derive"
-version = "1.0.210"
+version = "1.0.228"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "243902eda00fad750862fc144cea25caca5e20d615af0a81bee94ca738f1df1f"
+checksum = "d540f220d3187173da220f885ab66608367b6574e925011a9353e4badda91d79"
 dependencies = [
 "proc-macro2",
 "quote",
@ -626,9 +1022,9 @@ dependencies = [

 [[package]]
 name = "sha2"
-version = "0.10.8"
+version = "0.10.9"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "793db75ad2bcafc3ffa7c68b215fee268f537982cd901d132f89c6343f3a3dc8"
+checksum = "a7507d819769d01a365ab707794a4084392c824f54a7a6a7862f8c3d0892b283"
 dependencies = [
 "cfg-if",
 "cpufeatures",
@ -641,12 +1037,30 @@ version = "1.3.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "0fda2ff0d084019ba4d7c6f371c95d8fd75ce3524c3cb8fb653a3023f6323e64"

+[[package]]
+name = "simd-adler32"
+version = "0.3.8"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "e320a6c5ad31d271ad523dcf3ad13e2767ad8b1cb8f047f75a8aeaf8da139da2"
+
+[[package]]
+name = "simple-mermaid"
+version = "0.2.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "589144a964b4b30fe3a83b4bb1a09e2475aac194ec832a046a23e75bddf9eb29"
+
 [[package]]
 name = "strsim"
 version = "0.11.1"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "7da8b5736845d9f2fcb837ea5d9e2628564b3b043a70948a3f0b778838c5fb4f"

+[[package]]
+name = "subtle"
+version = "2.6.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "13c2bddecc57b384dee18652358fb23172facb8a2c51ccc10d74c157bdea3292"
+
 [[package]]
 name = "syn"
 version = "2.0.96"
@ -709,6 +1123,47 @@ version = "1.0.13"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "e91b56cd4cadaeb79bbf1a5645f6b4f8dc5bde8834ad5894a8db35fda9efa1fe"

+[[package]]
+name = "untrusted"
+version = "0.9.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "8ecb6da28b8a351d773b68d5825ac39017e680750f980f3a1a85cd8dd28a47c1"
+
+[[package]]
+name = "ureq"
+version = "3.1.4"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "d39cb1dbab692d82a977c0392ffac19e188bd9186a9f32806f0aaa859d75585a"
+dependencies = [
+ "base64",
+ "flate2",
+ "log",
+ "percent-encoding",
+ "rustls",
+ "rustls-pki-types",
+ "ureq-proto",
+ "utf-8",
+ "webpki-roots",
+]
+
+[[package]]
+name = "ureq-proto"
+version = "0.5.3"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "d81f9efa9df032be5934a46a068815a10a042b494b6a58cb0a1a97bb5467ed6f"
+dependencies = [
+ "base64",
+ "http",
+ "httparse",
+ "log",
+]
+
+[[package]]
+name = "utf-8"
+version = "0.7.6"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "09cc8ee72d2a9becf2f2febe0205bbed8fc6615b7cb429ad062dc7b7ddd036a9"
+
 [[package]]
 name = "utf8parse"
 version = "0.2.2"
@ -729,9 +1184,27 @@ checksum = "0b928f33d975fc6ad9f86c8f283853ad26bdd5b10b7f1542aa2fa15e2289105a"

 [[package]]
 name = "wasi"
-version = "0.11.0+wasi-snapshot-preview1"
+version = "0.11.1+wasi-snapshot-preview1"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "9c8d87e72b64a3b4db28d11ce29237c246188f4f51057d65a7eab63b7987e423"
+checksum = "ccf3ec651a847eb01de73ccad15eb7d99f80485de043efb2f370cd654f4ea44b"
+
+[[package]]
+name = "wasip2"
+version = "1.0.1+wasi-0.2.4"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "0562428422c63773dad2c345a1882263bbf4d65cf3f42e90921f787ef5ad58e7"
+dependencies = [
+ "wit-bindgen",
+]
+
+[[package]]
+name = "webpki-roots"
+version = "1.0.5"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "12bed680863276c63889429bfd6cab3b99943659923822de1c8a39c49e4d722c"
+dependencies = [
+ "rustls-pki-types",
+]

 [[package]]
 name = "which"
@ -741,10 +1214,17 @@ checksum = "b4ee928febd44d98f2f459a4a79bd4d928591333a494a10a868418ac1b39cf1f"
 dependencies = [
 "either",
 "home",
+ "regex",
 "rustix",
 "winsafe",
 ]

+[[package]]
+name = "windows-link"
+version = "0.2.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "f0805222e57f7521d6a62e36fa9163bc891acd422f971defe97d64e70d0a4fe5"
+
 [[package]]
 name = "windows-sys"
 version = "0.52.0"
@ -763,6 +1243,15 @@ dependencies = [
 "windows-targets",
 ]

+[[package]]
+name = "windows-sys"
+version = "0.61.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "ae137229bcbd6cdf0f7b80a31df61766145077ddf49416a728b02cb3921ff3fc"
+dependencies = [
+ "windows-link",
+]
+
 [[package]]
 name = "windows-targets"
 version = "0.52.6"
@ -833,6 +1322,12 @@ version = "0.0.19"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "d135d17ab770252ad95e9a872d365cf3090e3be864a34ab46f48555993efc904"

+[[package]]
+name = "wit-bindgen"
+version = "0.46.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "f17a85883d4e6d00e8a97c586de764dabcc06133f7f1d55dce5cdc070ad7fe59"
+
 [[package]]
 name = "wyz"
 version = "0.5.1"
@ -844,20 +1339,26 @@ dependencies = [

 [[package]]
 name = "zerocopy"
-version = "0.7.35"
+version = "0.8.27"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "1b9b4fd18abc82b8136838da5d50bae7bdea537c574d8dc1a34ed098d6c166f0"
+checksum = "0894878a5fa3edfd6da3f88c4805f4c8558e2b996227a3d864f47fe11e38282c"
 dependencies = [
 "zerocopy-derive",
 ]

 [[package]]
 name = "zerocopy-derive"
-version = "0.7.35"
+version = "0.8.27"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "fa4f8080344d4671fb4e831a13ad1e68092748387dfc4f55e356242fae12ce3e"
+checksum = "88d2b8d9c68ad2b9e4340d7832716a4d21a22a1154777ad56ea55c51a9cf3831"
 dependencies = [
 "proc-macro2",
 "quote",
 "syn",
 ]
+
+[[package]]
+name = "zeroize"
+version = "1.8.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "b97154e67e32c85465826e8bcc1c59429aaaf107c1e4a9e53c8d8ccd5eff88d0"
--- a/Cargo.toml
+++ b/Cargo.toml
@ -11,10 +11,19 @@ edition = "2024"
 repository = ""
 keywords = []
 categories = []
-rust-version = "1.89.0"
+rust-version = "1.93.0"

 [workspace.dependencies]
+base16ct = "1.0.0"
 fayalite = { git = "https://git.libre-chip.org/libre-chip/fayalite.git", version = "0.3.0", branch = "master" }
+hex-literal = "1.1.0"
+parse_powerisa_pdf = { git = "https://git.libre-chip.org/libre-chip/parse_powerisa_pdf.git", version = "0.1.0", branch = "master" }
+roxmltree = "0.21.1"
+serde = { version = "1.0.202", features = ["derive"] }
+sha2 = "0.10.9"
+simple-mermaid = "0.2.0"
+ureq = "3.1.4"
+which = { version = "6.0.3", features = ["regex"] }

 [profile.dev]
 opt-level = 1
--- a/README.md
+++ b/README.md
@ -0,0 +1,15 @@
+<!--
+SPDX-License-Identifier: LGPL-3.0-or-later
+See Notices.txt for copyright information
+-->
+# Libre-Chip's CPU
+
+<https://libre-chip.org/first_arch/index.html>
+
+# Funding
+
+## NLnet Grants
+
+* [Libre-Chip CPU with proof of No Spectre bugs](https://nlnet.nl/project/Libre-Chip-proof/) 2024-12-324 [(progress)](https://git.libre-chip.org/libre-chip/grant-tracking/src/branch/master/nlnet-2024-12-324/progress.md)
+
+This project was funded through the [NGI0 Commons Fund](https://nlnet.nl/commonsfund), a fund established by [NLnet](https://nlnet.nl/) with financial support from the European Commission's [Next Generation Internet](https://ngi.eu) programme, under the aegis of [DG Communications Networks, Content and Technology](https://commission.europa.eu/about-european-commission/departments-and-executive-agencies/communications-networks-content-and-technology_en) under grant agreement &numero; [101135429](https://cordis.europa.eu/project/id/101135429). Additional funding is made available by the [Swiss State Secretariat for Education, Research and Innovation](https://www.sbfi.admin.ch/sbfi/en/home.html) (SERI).
--- a/crates/cpu/Cargo.toml
+++ b/crates/cpu/Cargo.toml
@ -16,3 +16,20 @@ version.workspace = true

 [dependencies]
 fayalite.workspace = true
+roxmltree.workspace = true
+serde.workspace = true
+simple-mermaid.workspace = true
+
+[build-dependencies]
+base16ct.workspace = true
+hex-literal.workspace = true
+parse_powerisa_pdf.workspace = true
+sha2.workspace = true
+ureq.workspace = true
+
+[dev-dependencies]
+base16ct.workspace = true
+hex-literal.workspace = true
+regex = "1.12.2"
+sha2.workspace = true
+which.workspace = true
--- a/crates/cpu/README.md
+++ b/crates/cpu/README.md
@ -0,0 +1 @@
+../../README.md
--- a/crates/cpu/build.rs
+++ b/crates/cpu/build.rs
@ -0,0 +1,96 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+
+use parse_powerisa_pdf::parse_powerisa_pdf_and_generate_xml;
+use sha2::{Digest, Sha256};
+use std::{
+    error::Error,
+    io::{ErrorKind, Read},
+    path::Path,
+};
+
+const EXPECTED_FILE_SIZE: u64 = 6425593;
+const EXPECTED_FILE_HASH: &[u8; 32] =
+    &hex_literal::hex!("56372d23ece7e9e2c1b381a639443982a3e16e38109df1c141d655b779b61fdb");
+
+fn verify_powerisa_file(file: impl std::io::Read) -> Result<Vec<u8>, Box<dyn Error>> {
+    let mut buf = Vec::with_capacity(usize::try_from(EXPECTED_FILE_SIZE)? + 1);
+    file.take(EXPECTED_FILE_SIZE + 1).read_to_end(&mut buf)?;
+    if buf.len() > EXPECTED_FILE_SIZE as usize {
+        Err(format!("file is bigger than the expected length {EXPECTED_FILE_SIZE}").into())
+    } else if buf.len() < EXPECTED_FILE_SIZE as usize {
+        Err(format!(
+            "file is smaller than the expected length {EXPECTED_FILE_SIZE}: actual length {}",
+            buf.len()
+        )
+        .into())
+    } else {
+        let hash = Sha256::digest(&buf);
+        let hash = &*hash;
+        if hash != EXPECTED_FILE_HASH {
+            Err(format!(
+                "file's SHA256 hash doesn't match the expected hash: expected: {:x} got: {:x}",
+                base16ct::HexDisplay(EXPECTED_FILE_HASH),
+                base16ct::HexDisplay(hash)
+            )
+            .into())
+        } else {
+            Ok(buf)
+        }
+    }
+}
+
+fn is_powerisa_pdf(path: impl AsRef<Path>) -> Result<bool, Box<dyn Error>> {
+    let path = path.as_ref();
+    let metadata = match std::fs::metadata(path) {
+        Err(e) if e.kind() == ErrorKind::NotFound => return Ok(false),
+        v => v?,
+    };
+    if !metadata.is_file() {
+        return Ok(false);
+    }
+    let file = std::fs::File::open(path)?;
+    verify_powerisa_file(file)?;
+    Ok(true)
+}
+
+fn out_dir() -> String {
+    std::env::var("OUT_DIR").expect("OUT_DIR env var is not set or invalid")
+}
+
+fn get_powerisa_pdf_name_and_dir<'a>(
+    out_dir: &'a str,
+) -> Result<(&'static str, &'a Path), Box<dyn Error>> {
+    const FILE_NAME: &str = "OPF_PowerISA_v3.1C.pdf";
+    let out_dir = Path::new(out_dir);
+    if is_powerisa_pdf(FILE_NAME)? {
+        println!("cargo::rerun-if-changed={FILE_NAME}");
+        return Ok((FILE_NAME, Path::new(".")));
+    }
+    let full_path = out_dir.join(FILE_NAME);
+    let full_path = full_path
+        .into_os_string()
+        .into_string()
+        .expect("should be valid UTF-8");
+    if is_powerisa_pdf(&full_path)? {
+        println!("cargo::rerun-if-changed={full_path}");
+        return Ok((FILE_NAME, out_dir));
+    }
+    const URL: &str = "https://libre-chip.org/OPF_PowerISA_v3.1C.pdf";
+    println!("cargo::warning={FILE_NAME} not found locally, downloading from {URL}");
+    let buf = verify_powerisa_file(ureq::get(URL).call()?.into_body().into_reader())?;
+    std::fs::write(&full_path, buf)?;
+    println!("cargo::rerun-if-changed={full_path}");
+    Ok((FILE_NAME, out_dir))
+}
+
+fn main() -> Result<(), Box<dyn Error>> {
+    let out_dir = out_dir();
+    let (pdf_name, pdf_dir) = get_powerisa_pdf_name_and_dir(&out_dir)?;
+    let old_dir = std::env::current_dir()?;
+    std::env::set_current_dir(pdf_dir)?;
+    let xml = parse_powerisa_pdf_and_generate_xml(pdf_name, None, false)?;
+    std::env::set_current_dir(old_dir)?;
+    std::fs::write(Path::new(&out_dir).join("powerisa-instructions.xml"), xml)?;
+    Ok(())
+}
--- a/crates/cpu/src/config.rs
+++ b/crates/cpu/src/config.rs
@ -8,9 +8,10 @@ use crate::{
    },
 };
 use fayalite::prelude::*;
+use serde::{Deserialize, Serialize};
 use std::num::NonZeroUsize;

-#[derive(Clone, Eq, PartialEq, Hash, Debug)]
+#[derive(Clone, Eq, PartialEq, Hash, Debug, Serialize, Deserialize)]
 #[non_exhaustive]
 pub struct UnitConfig {
    pub kind: UnitKind,
@ -27,12 +28,18 @@ impl UnitConfig {
    }
 }

-#[derive(Clone, Eq, PartialEq, Hash, Debug)]
+#[derive(Clone, Eq, PartialEq, Hash, Debug, Serialize, Deserialize)]
 #[non_exhaustive]
 pub struct CpuConfig {
    pub units: Vec<UnitConfig>,
    pub out_reg_num_width: usize,
    pub fetch_width: NonZeroUsize,
+    pub max_branches_per_fetch: NonZeroUsize,
+    pub max_fetches_in_flight: NonZeroUsize,
+    pub log2_fetch_width_in_bytes: u8,
+    pub log2_cache_line_size_in_bytes: u8,
+    pub log2_l1_i_cache_line_count: u8,
+    pub l1_i_cache_max_misses_in_flight: NonZeroUsize,
    /// default value for [`UnitConfig::max_in_flight`]
    pub default_unit_max_in_flight: NonZeroUsize,
    pub rob_size: NonZeroUsize,
@ -46,6 +53,27 @@ impl CpuConfig {
        };
        v
    };
+    pub const DEFAULT_MAX_BRANCHES_PER_FETCH: NonZeroUsize = {
+        let Some(v) = NonZeroUsize::new(1) else {
+            unreachable!();
+        };
+        v
+    };
+    pub const DEFAULT_MAX_FETCHES_IN_FLIGHT: NonZeroUsize = {
+        let Some(v) = NonZeroUsize::new(16) else {
+            unreachable!();
+        };
+        v
+    };
+    pub const DEFAULT_LOG2_FETCH_WIDTH_IN_BYTES: u8 = 3;
+    pub const DEFAULT_LOG2_CACHE_LINE_SIZE_IN_BYTES: u8 = 6;
+    pub const DEFAULT_LOG2_L1_I_CACHE_LINE_COUNT: u8 = 8;
+    pub const DEFAULT_L1_I_CACHE_MAX_MISSES_IN_FLIGHT: NonZeroUsize = {
+        let Some(v) = NonZeroUsize::new(2) else {
+            unreachable!();
+        };
+        v
+    };
    pub const DEFAULT_UNIT_MAX_IN_FLIGHT: NonZeroUsize = {
        let Some(v) = NonZeroUsize::new(8) else {
            unreachable!();
@ -57,6 +85,12 @@ impl CpuConfig {
            units,
            out_reg_num_width: Self::DEFAULT_OUT_REG_NUM_WIDTH,
            fetch_width: Self::DEFAULT_FETCH_WIDTH,
+            max_branches_per_fetch: Self::DEFAULT_MAX_BRANCHES_PER_FETCH,
+            max_fetches_in_flight: Self::DEFAULT_MAX_FETCHES_IN_FLIGHT,
+            log2_fetch_width_in_bytes: Self::DEFAULT_LOG2_FETCH_WIDTH_IN_BYTES,
+            log2_cache_line_size_in_bytes: Self::DEFAULT_LOG2_CACHE_LINE_SIZE_IN_BYTES,
+            log2_l1_i_cache_line_count: Self::DEFAULT_LOG2_L1_I_CACHE_LINE_COUNT,
+            l1_i_cache_max_misses_in_flight: Self::DEFAULT_L1_I_CACHE_MAX_MISSES_IN_FLIGHT,
            default_unit_max_in_flight: Self::DEFAULT_UNIT_MAX_IN_FLIGHT,
            rob_size,
        }
@ -116,4 +150,100 @@ impl CpuConfig {
        UnitToRegAlloc[mop_ty][extra_out_ty][self.unit_num_width()][self.out_reg_num_width]
            [self.non_const_unit_nums().len()]
    }
+    pub fn fetch_width_in_bytes(&self) -> usize {
+        1usize
+            .checked_shl(self.log2_fetch_width_in_bytes.into())
+            .expect("log2_fetch_width_in_bytes is too big")
    }
+    pub fn cache_line_size_in_bytes(&self) -> usize {
+        1usize
+            .checked_shl(self.log2_cache_line_size_in_bytes.into())
+            .expect("log2_cache_line_size_in_bytes is too big")
+    }
+    pub fn log2_fetches_per_cache_line(&self) -> usize {
+        self.log2_cache_line_size_in_bytes
+            .checked_sub(self.log2_fetch_width_in_bytes)
+            .expect("cache line size in bytes must not be smaller than fetch width in bytes")
+            .into()
+    }
+    pub fn fetches_per_cache_line(&self) -> usize {
+        self.log2_fetches_per_cache_line()
+            .try_into()
+            .ok()
+            .and_then(|v| 1usize.checked_shl(v))
+            .expect("log2_fetches_per_cache_line is too big")
+    }
+    pub fn l1_i_cache_line_count(&self) -> usize {
+        1usize
+            .checked_shl(self.log2_l1_i_cache_line_count.into())
+            .expect("log2_l1_i_cache_line_count is too big")
+    }
+    pub fn log2_l1_i_cache_size_in_bytes(&self) -> usize {
+        self.log2_l1_i_cache_line_count as usize + self.log2_cache_line_size_in_bytes as usize
+    }
+    pub fn l1_i_cache_size_in_bytes(&self) -> usize {
+        1usize
+            .checked_shl(self.log2_l1_i_cache_size_in_bytes() as _)
+            .expect("L1 I-Cache is too big")
+    }
+}
+
+#[hdl(get(|c| c.fetch_width.get()))]
+pub type CpuConfigFetchWidth<C: PhantomConstGet<CpuConfig>> = DynSize;
+
+#[hdl(get(|c| c.fetch_width.get() * 2))]
+pub type TwiceCpuConfigFetchWidth<C: PhantomConstGet<CpuConfig>> = DynSize;
+
+#[hdl(get(|c| c.max_branches_per_fetch.get()))]
+pub type CpuConfigMaxBranchesPerFetch<C: PhantomConstGet<CpuConfig>> = DynSize;
+
+#[hdl(get(|c| c.max_fetches_in_flight.get()))]
+pub type CpuConfigMaxFetchesInFlight<C: PhantomConstGet<CpuConfig>> = DynSize;
+
+#[hdl(get(|c| c.log2_fetch_width_in_bytes.into()))]
+pub type CpuConfigLog2FetchWidthInBytes<C: PhantomConstGet<CpuConfig>> = DynSize;
+
+#[hdl(get(|c| c.fetch_width_in_bytes()))]
+pub type CpuConfigFetchWidthInBytes<C: PhantomConstGet<CpuConfig>> = DynSize;
+
+#[hdl(get(|c| c.log2_fetches_per_cache_line()))]
+pub type CpuConfigLog2FetchesPerCacheLine<C: PhantomConstGet<CpuConfig>> = DynSize;
+
+#[hdl(get(|c| c.fetches_per_cache_line()))]
+pub type CpuConfigFetchesPerCacheLine<C: PhantomConstGet<CpuConfig>> = DynSize;
+
+#[hdl(get(|c| c.log2_cache_line_size_in_bytes.into()))]
+pub type CpuConfigLog2CacheLineSizeInBytes<C: PhantomConstGet<CpuConfig>> = DynSize;
+
+#[hdl(get(|c| c.cache_line_size_in_bytes()))]
+pub type CpuConfigCacheLineSizeInBytes<C: PhantomConstGet<CpuConfig>> = DynSize;
+
+#[hdl(get(|c| c.log2_l1_i_cache_line_count.into()))]
+pub type CpuConfigLog2L1ICacheLineCount<C: PhantomConstGet<CpuConfig>> = DynSize;
+
+#[hdl(get(|c| c.l1_i_cache_line_count()))]
+pub type CpuConfigL1ICacheLineCount<C: PhantomConstGet<CpuConfig>> = DynSize;
+
+#[hdl(get(|c| c.log2_l1_i_cache_size_in_bytes()))]
+pub type CpuConfigLog2L1ICacheSizeInBytes<C: PhantomConstGet<CpuConfig>> = DynSize;
+
+#[hdl(get(|c| c.l1_i_cache_size_in_bytes()))]
+pub type CpuConfigL1ICacheSizeInBytes<C: PhantomConstGet<CpuConfig>> = DynSize;
+
+#[hdl(get(|c| c.l1_i_cache_max_misses_in_flight.get()))]
+pub type CpuConfigL1ICacheMaxMissesInFlight<C: PhantomConstGet<CpuConfig>> = DynSize;
+
+#[hdl(get(|c| c.rob_size.get()))]
+pub type CpuConfigRobSize<C: PhantomConstGet<CpuConfig>> = DynSize;
+
+pub trait PhantomConstCpuConfig:
+    PhantomConstGet<CpuConfig>
+    + Into<PhantomConst<CpuConfig>>
+    + From<PhantomConst<CpuConfig>>
+    + Type
+    + ToSimValue<Type = Self>
+    + ToExpr<Type = Self>
+{
+}
+
+impl PhantomConstCpuConfig for PhantomConst<CpuConfig> {}
--- a/crates/cpu/src/decoder.rs
+++ b/crates/cpu/src/decoder.rs
@ -0,0 +1,4 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+
+pub mod simple_power_isa;
--- a/crates/cpu/src/decoder/simple_power_isa.rs
+++ b/crates/cpu/src/decoder/simple_power_isa.rs
--- a/crates/cpu/src/fetch.rs
+++ b/crates/cpu/src/fetch.rs
--- a/crates/cpu/src/instruction.rs
+++ b/crates/cpu/src/instruction.rs
--- a/crates/cpu/src/instruction/power_isa.rs
+++ b/crates/cpu/src/instruction/power_isa.rs
@ -27,26 +27,432 @@ pub struct PowerIsaCrBitNum {

 impl MOpRegNum {
    pub const POWER_ISA_LR_REG_NUM: u32 = 1;
+    #[hdl]
+    pub fn power_isa_lr_reg() -> Expr<Self> {
+        #[hdl]
+        Self {
+            value: Self::POWER_ISA_LR_REG_NUM.cast_to_static::<UInt<_>>(),
+        }
+    }
    pub const POWER_ISA_CTR_REG_NUM: u32 = 2;
+    #[hdl]
+    pub fn power_isa_ctr_reg() -> Expr<Self> {
+        #[hdl]
+        Self {
+            value: Self::POWER_ISA_CTR_REG_NUM.cast_to_static::<UInt<_>>(),
+        }
+    }
    pub const POWER_ISA_TAR_REG_NUM: u32 = 3;
-    /// XER bits are stored in [`PRegValue.flags`], bits that don't exist in [`PRegValue.flags`] are stored in [`PRegValue.int_fp`]
+    #[hdl]
+    pub fn power_isa_tar_reg() -> Expr<Self> {
+        #[hdl]
+        Self {
+            value: Self::POWER_ISA_TAR_REG_NUM.cast_to_static::<UInt<_>>(),
+        }
+    }
+
+    /// SO, OV, and OV32 XER bits -- in [`PRegValue.flags`]
    ///
    /// [`PRegValue.flags`]: struct@crate::register::PRegValue
-    /// [`PRegValue.int_fp`]: struct@crate::register::PRegValue
-    pub const POWER_ISA_XER_REG_NUM: u32 = 4;
+    pub const POWER_ISA_XER_SO_OV_OV32_REG_NUM: u32 =
+        range_u32_nth_or_panic(&Self::FLAG_REG_NUMS, 0);
+    /// CA and CA32 XER bits -- in [`PRegValue.flags`]
+    ///
+    /// [`PRegValue.flags`]: struct@crate::register::PRegValue
+    pub const POWER_ISA_XER_CA_CA32_REG_NUM: u32 = 4;
+    /// only the XER bits that don't exist in [`PRegValue.flags`]
+    ///
+    /// [`PRegValue.flags`]: struct@crate::register::PRegValue
+    pub const POWER_ISA_XER_OTHER_REG_NUM: u32 = 5;

-    pub const POWER_ISA_CR_REG_NUMS: Range<u32> = 8..16;
+    /// used as a temporary for things like computing the effective address before loading/storing memory
+    pub const POWER_ISA_TEMP_REG_NUM: u32 = 8;
+    #[hdl]
+    pub fn power_isa_temp_reg() -> Expr<Self> {
+        #[hdl]
+        Self {
+            value: Self::POWER_ISA_TEMP_REG_NUM.cast_to_static::<UInt<_>>(),
+        }
+    }
+
+    /// SO, OV, and OV32 XER bits -- in [`PRegValue.flags`]
+    ///
+    /// [`PRegValue.flags`]: struct@crate::register::PRegValue
+    #[hdl]
+    pub fn power_isa_xer_so_ov_ov32_reg() -> Expr<Self> {
+        #[hdl]
+        Self {
+            value: Self::POWER_ISA_XER_SO_OV_OV32_REG_NUM.cast_to_static::<UInt<_>>(),
+        }
+    }
+    /// CA and CA32 XER bits -- in [`PRegValue.flags`]
+    ///
+    /// [`PRegValue.flags`]: struct@crate::register::PRegValue
+    #[hdl]
+    pub fn power_isa_xer_ca_ca32_reg() -> Expr<Self> {
+        #[hdl]
+        Self {
+            value: Self::POWER_ISA_XER_CA_CA32_REG_NUM.cast_to_static::<UInt<_>>(),
+        }
+    }
+    /// only the XER bits that don't exist in [`PRegValue.flags`]
+    ///
+    /// [`PRegValue.flags`]: struct@crate::register::PRegValue
+    #[hdl]
+    pub fn power_isa_xer_other_reg() -> Expr<Self> {
+        #[hdl]
+        Self {
+            value: Self::POWER_ISA_XER_OTHER_REG_NUM.cast_to_static::<UInt<_>>(),
+        }
+    }
+
+    pub const POWER_ISA_CR_0_REG_NUM: u32 = range_u32_nth_or_panic(&Self::FLAG_REG_NUMS, 1);
+    pub const POWER_ISA_CR_1_THRU_7_REG_NUMS: Range<u32> = 9..16;
    pub const fn power_isa_cr_reg_num(index: usize) -> u32 {
-        range_u32_nth_or_panic(&Self::POWER_ISA_CR_REG_NUMS, index)
+        if index == 0 {
+            Self::POWER_ISA_CR_0_REG_NUM
+        } else {
+            range_u32_nth_or_panic(&Self::POWER_ISA_CR_1_THRU_7_REG_NUMS, index - 1)
+        }
+    }
+    #[hdl]
+    pub fn power_isa_cr_reg(field_num: Expr<UInt<3>>) -> Expr<Self> {
+        #[hdl]
+        let power_isa_cr_reg: Self = wire();
+        #[hdl]
+        if field_num.cmp_eq(0u8) {
+            connect_any(power_isa_cr_reg.value, Self::POWER_ISA_CR_0_REG_NUM);
+        } else {
+            connect_any(
+                power_isa_cr_reg.value,
+                Self::POWER_ISA_CR_1_THRU_7_REG_NUMS.start - 1 + field_num,
+            );
+        }
+        power_isa_cr_reg
+    }
+    #[hdl]
+    pub fn power_isa_cr_reg_imm(index: usize) -> Expr<Self> {
+        #[hdl]
+        Self {
+            value: Self::power_isa_cr_reg_num(index).cast_to_static::<UInt<_>>(),
+        }
+    }
+    #[hdl]
+    pub fn power_isa_cr_reg_sim(field_num: &SimValue<UInt<3>>) -> SimValue<Self> {
+        #[hdl(sim)]
+        Self {
+            value: Self::power_isa_cr_reg_num(
+                field_num.cast_to_static::<UInt<8>>().as_int() as usize
+            )
+            .cast_to_static::<UInt<_>>(),
+        }
    }

    pub const POWER_ISA_GPR_REG_NUMS: Range<u32> = 32..64;
    pub const fn power_isa_gpr_reg_num(index: usize) -> u32 {
        range_u32_nth_or_panic(&Self::POWER_ISA_GPR_REG_NUMS, index)
    }
+    #[hdl]
+    pub fn power_isa_gpr_reg(reg_num: Expr<UInt<5>>) -> Expr<Self> {
+        #[hdl]
+        Self {
+            value: (Self::POWER_ISA_GPR_REG_NUMS.start + reg_num).cast_to_static::<UInt<_>>(),
+        }
+    }
+    #[hdl]
+    pub fn power_isa_gpr_reg_imm(index: usize) -> Expr<Self> {
+        #[hdl]
+        Self {
+            value: Self::power_isa_gpr_reg_num(index).cast_to_static::<UInt<_>>(),
+        }
+    }
+    #[hdl]
+    pub fn power_isa_gpr_reg_sim(reg_num: &SimValue<UInt<5>>) -> SimValue<Self> {
+        #[hdl(sim)]
+        Self {
+            value: (Self::POWER_ISA_GPR_REG_NUMS.start + reg_num).cast_to_static::<UInt<_>>(),
+        }
+    }
+    pub const fn power_isa_gpr_or_zero_reg_num(index: usize) -> u32 {
+        if index == 0 {
+            Self::CONST_ZERO_REG_NUM
+        } else {
+            Self::power_isa_gpr_reg_num(index)
+        }
+    }
+    #[hdl]
+    pub fn power_isa_gpr_or_zero_reg(reg_num: Expr<UInt<5>>) -> Expr<Self> {
+        #[hdl]
+        let power_isa_gpr_or_zero_reg: Self = wire();
+        connect(power_isa_gpr_or_zero_reg, Self::power_isa_gpr_reg(reg_num));
+        #[hdl]
+        if reg_num.cmp_eq(0u8) {
+            connect(power_isa_gpr_or_zero_reg, Self::const_zero());
+        }
+        power_isa_gpr_or_zero_reg
+    }
+    #[hdl]
+    pub fn power_isa_gpr_or_zero_reg_sim(reg_num: &SimValue<UInt<5>>) -> SimValue<Self> {
+        #[hdl(sim)]
+        Self {
+            value: Self::power_isa_gpr_or_zero_reg_num(
+                reg_num.cast_to_static::<UInt<8>>().as_int() as usize,
+            )
+            .cast_to_static::<UInt<_>>(),
+        }
+    }

    pub const POWER_ISA_FPR_REG_NUMS: Range<u32> = 64..96;
    pub const fn power_isa_fpr_reg_num(index: usize) -> u32 {
        range_u32_nth_or_panic(&Self::POWER_ISA_FPR_REG_NUMS, index)
    }
+    #[hdl]
+    pub fn power_isa_fpr_reg(reg_num: Expr<UInt<5>>) -> Expr<Self> {
+        #[hdl]
+        Self {
+            value: (Self::POWER_ISA_FPR_REG_NUMS.start + reg_num).cast_to_static::<UInt<_>>(),
+        }
+    }
+    #[hdl]
+    pub fn power_isa_fpr_reg_sim(reg_num: &SimValue<UInt<5>>) -> SimValue<Self> {
+        #[hdl(sim)]
+        Self {
+            value: (Self::POWER_ISA_FPR_REG_NUMS.start + reg_num).cast_to_static::<UInt<_>>(),
+        }
+    }
+}
+
+#[hdl(cmp_eq)]
+pub struct PowerIsaSpr {
+    pub num: UInt<10>,
+}
+
+macro_rules! make_spr_enum {
+    (
+        $(#[$enum_meta:meta])*
+        $enum_vis:vis enum $PowerIsaSprEnum:ident {
+            $($enum_body:tt)*
+        }
+    ) => {
+        $(#[$enum_meta])*
+        $enum_vis enum $PowerIsaSprEnum {
+            $($enum_body)*
+            Unknown(u16),
+        }
+
+        make_spr_enum! {
+            @impl
+            $enum_vis enum $PowerIsaSprEnum {
+                $($enum_body)*
+            }
+        }
+    };
+    (
+        @impl
+        $enum_vis:vis enum $PowerIsaSprEnum:ident {
+            $(
+                $(#[$variant_meta:meta])*
+                $Variant:ident = $value:literal,
+            )+
+        }
+    ) => {
+        impl $PowerIsaSprEnum {
+            pub const VARIANTS: &[Self; 1 << 10] = &{
+                let mut retval = [Self::Unknown(0); 1 << 10];
+                let mut i = 0;
+                while i < retval.len() {
+                    retval[i] = Self::Unknown(i as u16);
+                    i += 1;
+                }
+                let mut last_value = None;
+                #[track_caller]
+                const fn add_variant(
+                    values: &mut [$PowerIsaSprEnum; 1 << 10],
+                    last_value: &mut Option<u16>,
+                    variant: $PowerIsaSprEnum,
+                    value: u16,
+                ) {
+                    assert!(value < 1 << 10, "variant value out of range");
+                    if let Some(last_value) = *last_value {
+                        assert!(last_value < value, "variants must be in ascending order with no duplicates");
+                    }
+                    *last_value = Some(value);
+                    values[value as usize] = variant;
+                }
+                $(add_variant(&mut retval, &mut last_value, Self::$Variant, $value);)+
+                retval
+            };
+            pub const fn value(self) -> u16 {
+                match self {
+                    $(Self::$Variant => $value,)+
+                    Self::Unknown(v) => v,
+                }
+            }
+        }
+    };
+}
+
+make_spr_enum! {
+    #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+    #[repr(u16)]
+    pub enum PowerIsaSprEnum {
+        Xer = 1,
+        UserDscr = 3,
+        Lr = 8,
+        Ctr = 9,
+        UserAmr = 13,
+        Dscr = 17,
+        Dsisr = 18,
+        Dar = 19,
+        Dec = 22,
+        Srr0 = 26,
+        Srr1 = 27,
+        Cfar = 28,
+        Amr = 29,
+        Pidr = 48,
+        Iamr = 61,
+        ReadCtrl = 136,
+        WriteCtrl = 152,
+        Fscr = 153,
+        Uamor = 157,
+        Pspb = 159,
+        Dpdes = 176,
+        Dawr0 = 180,
+        Dawr1 = 181,
+        Rpr = 186,
+        Ciabr = 187,
+        Dawrx0 = 188,
+        Dawrx1 = 189,
+        Hfscr = 190,
+        Vrsave = 256,
+        UserSprg3 = 259,
+        Tb = 268,
+        Tbu = 269,
+        Sprg0 = 272,
+        Sprg1 = 273,
+        Sprg2 = 274,
+        Sprg3 = 275,
+        Tbl = 284,
+        WriteTbu = 285,
+        Tbu40 = 286,
+        Pvr = 287,
+        Hsprg0 = 304,
+        Hsprg1 = 305,
+        Hdsisr = 306,
+        Hdar = 307,
+        Spurr = 308,
+        Purr = 309,
+        Hdec = 310,
+        Hrmor = 313,
+        Hsrr0 = 314,
+        Hsrr1 = 315,
+        Lpcr = 318,
+        Lpidr = 319,
+        Hmer = 336,
+        Hmeer = 337,
+        Pcr = 338,
+        Heir = 339,
+        Amor = 349,
+        Tir = 446,
+        UserHdexcr = 455,
+        Ptcr = 464,
+        Hashkeyr = 468,
+        Hashpkeyr = 469,
+        Hdexcr = 471,
+        Usprg0 = 496,
+        Usprg1 = 497,
+        Urmor = 505,
+        Usrr0 = 506,
+        Usrr1 = 507,
+        Smfctrl = 511,
+        UserSier2 = 736,
+        UserSier3 = 737,
+        UserMmcr3 = 738,
+        Sier2 = 752,
+        Sier3 = 753,
+        Mmcr3 = 754,
+        UserSier = 768,
+        Mmcr2 = 769,
+        Mmcra = 770,
+        Pmc1 = 771,
+        Pmc2 = 772,
+        Pmc3 = 773,
+        Pmc4 = 774,
+        Pmc5 = 775,
+        Pmc6 = 776,
+        Mmcr0 = 779,
+        Siar = 780,
+        Sdar = 781,
+        Mmcr1 = 782,
+        Sier = 784,
+        PrivMmcr2 = 785,
+        PrivMmcra = 786,
+        PrivPmc1 = 787,
+        PrivPmc2 = 788,
+        PrivPmc3 = 789,
+        PrivPmc4 = 790,
+        PrivPmc5 = 791,
+        PrivPmc6 = 792,
+        PrivMmcr0 = 795,
+        PrivSiar = 796,
+        PrivSdar = 797,
+        PrivMmcr1 = 798,
+        Bescrs15 = 800,
+        Bescrsu16 = 801,
+        Bescrr15 = 802,
+        Bescrru16 = 803,
+        Ebbhr = 804,
+        Ebbrr = 805,
+        Bescr = 806,
+        Reserved808 = 808,
+        Reserved809 = 809,
+        Reserved810 = 810,
+        Reserved811 = 811,
+        UserDexcr = 812,
+        Tar = 815,
+        Asdr = 816,
+        Psscr = 823,
+        Dexcr = 828,
+        Ic = 848,
+        Vtb = 849,
+        HyperPsscr = 855,
+        Ppr = 896,
+        Ppr32 = 898,
+        Pir = 1023,
+    }
+}
+
+impl ValueType for PowerIsaSprEnum {
+    type Type = PowerIsaSpr;
+    type ValueCategory = fayalite::expr::value_category::ValueCategoryValue;
+
+    fn ty(&self) -> Self::Type {
+        PowerIsaSpr
+    }
+}
+
+impl ToExpr for PowerIsaSprEnum {
+    #[hdl]
+    fn to_expr(&self) -> Expr<Self::Type> {
+        #[hdl]
+        PowerIsaSpr {
+            num: self.value().cast_to_static::<UInt<_>>(),
+        }
+    }
+}
+
+impl ToSimValueWithType<PowerIsaSpr> for PowerIsaSprEnum {
+    fn to_sim_value_with_type(&self, _ty: PowerIsaSpr) -> SimValue<PowerIsaSpr> {
+        self.to_sim_value()
+    }
+}
+
+impl ToSimValue for PowerIsaSprEnum {
+    #[hdl]
+    fn to_sim_value(&self) -> SimValue<Self::Type> {
+        #[hdl(sim)]
+        PowerIsaSpr {
+            num: self.value().cast_to_static::<UInt<_>>(),
+        }
+    }
 }
--- a/crates/cpu/src/lib.rs
+++ b/crates/cpu/src/lib.rs
@ -1,7 +1,12 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
 pub mod config;
+pub mod decoder;
+pub mod fetch;
 pub mod instruction;
+pub mod main_memory_and_io;
+pub mod next_pc;
+pub mod powerisa_instructions_xml;
 pub mod reg_alloc;
 pub mod register;
 pub mod unit;
--- a/crates/cpu/src/main_memory_and_io.rs
+++ b/crates/cpu/src/main_memory_and_io.rs
@ -0,0 +1,59 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+
+use crate::{
+    config::{
+        CpuConfig, CpuConfigFetchWidthInBytes, CpuConfigMaxFetchesInFlight, PhantomConstCpuConfig,
+    },
+    next_pc::FETCH_BLOCK_ID_WIDTH,
+    util::array_vec::ArrayVec,
+};
+use fayalite::{prelude::*, util::ready_valid::ReadyValid};
+
+pub mod simple_uart;
+
+#[hdl]
+pub enum MemoryOperationKind {
+    Read,
+    Write,
+}
+
+#[hdl(no_static)]
+pub struct MemoryOperationStart<C: PhantomConstGet<CpuConfig> + PhantomConstCpuConfig> {
+    pub kind: MemoryOperationKind,
+    pub addr: UInt<64>,
+    pub write_data: ArrayType<UInt<8>, CpuConfigFetchWidthInBytes<C>>,
+    pub rw_mask: ArrayType<Bool, CpuConfigFetchWidthInBytes<C>>,
+    pub fetch_block_id: UInt<{ FETCH_BLOCK_ID_WIDTH }>, // for debugging
+    pub config: C,
+}
+
+#[hdl]
+pub enum MemoryOperationErrorKind {
+    Generic,
+}
+
+#[hdl]
+pub enum MemoryOperationFinishKind {
+    Success(MemoryOperationKind),
+    Error(MemoryOperationErrorKind),
+}
+
+#[hdl(no_static)]
+pub struct MemoryOperationFinish<C: PhantomConstGet<CpuConfig> + PhantomConstCpuConfig> {
+    pub kind: MemoryOperationFinishKind,
+    pub read_data: ArrayType<UInt<8>, CpuConfigFetchWidthInBytes<C>>,
+    pub config: C,
+}
+
+#[hdl(no_static)]
+pub struct MemoryInterface<C: PhantomConstGet<CpuConfig> + PhantomConstCpuConfig> {
+    pub start: ReadyValid<MemoryOperationStart<C>>,
+    #[hdl(flip)]
+    pub finish: ReadyValid<MemoryOperationFinish<C>>,
+    /// for debugging
+    #[hdl(flip)]
+    pub next_fetch_block_ids:
+        HdlOption<ArrayVec<UInt<{ FETCH_BLOCK_ID_WIDTH }>, CpuConfigMaxFetchesInFlight<C>>>,
+    pub config: C,
+}
--- a/crates/cpu/src/main_memory_and_io/simple_uart.rs
+++ b/crates/cpu/src/main_memory_and_io/simple_uart.rs
@ -0,0 +1,587 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+
+use std::num::NonZeroUsize;
+
+use crate::{
+    config::{CpuConfig, PhantomConstCpuConfig},
+    main_memory_and_io::{
+        MemoryInterface, MemoryOperationErrorKind, MemoryOperationFinish,
+        MemoryOperationFinishKind, MemoryOperationKind, MemoryOperationStart,
+    },
+    util::array_vec::ArrayVec,
+};
+use fayalite::{
+    int::UIntInRange,
+    prelude::*,
+    util::ready_valid::{ReadyValid, queue},
+};
+
+const TICKS_PER_BAUD: usize = 16;
+const PRECISION_BITS: usize = 16;
+
+#[hdl_module]
+pub fn uart_clock_gen(
+    clock_input_properties: PhantomConst<peripherals::ClockInputProperties>,
+    baud_rate: f64,
+) {
+    #[hdl]
+    let cd: ClockDomain = m.input();
+    #[hdl]
+    let tick: Bool = m.output();
+
+    let divisor =
+        clock_input_properties.get().frequency.into_inner() / (baud_rate * TICKS_PER_BAUD as f64);
+    type NumeratorType = u128;
+    let numerator: NumeratorType = 1 << PRECISION_BITS;
+    let denominator: NumeratorType = (divisor * numerator as f64).round() as _;
+    let remainder_ty = UInt::range(0..denominator);
+
+    #[hdl]
+    let remainder_reg = reg_builder().clock_domain(cd).reset(remainder_ty.zero());
+
+    #[hdl]
+    let sum = wire((remainder_reg + numerator).ty());
+    connect_any(sum, remainder_reg + numerator);
+
+    #[hdl]
+    let tick_reg = reg_builder().clock_domain(cd).reset(false);
+    connect(tick_reg, false);
+
+    #[hdl]
+    let next_remainder = wire(remainder_ty);
+    connect(remainder_reg, next_remainder);
+
+    #[hdl]
+    if sum.cmp_ge(denominator) {
+        connect_any(next_remainder, sum - denominator);
+        connect(tick_reg, true);
+    } else {
+        connect(next_remainder, sum);
+    }
+
+    connect(tick, tick_reg);
+}
+
+#[hdl_module]
+pub fn transmitter() {
+    #[hdl]
+    let cd: ClockDomain = m.input();
+    #[hdl]
+    let tick: Bool = m.input();
+    #[hdl]
+    let tx: Bool = m.output();
+    #[hdl]
+    let input_byte: ReadyValid<UInt<8>> = m.input();
+
+    #[hdl]
+    let not_tx_reg: Bool = reg_builder().clock_domain(cd).reset(false);
+
+    connect(tx, !not_tx_reg);
+
+    #[hdl]
+    let input_buf_reg: HdlOption<UInt<8>> = reg_builder().clock_domain(cd).reset(HdlNone());
+
+    const BYTE_ON_WIRE_WIDTH: usize = 10;
+
+    #[hdl]
+    let shift_reg: Array<HdlOption<Bool>, _> = reg_builder()
+        .clock_domain(cd)
+        .reset([HdlNone(); BYTE_ON_WIRE_WIDTH]);
+
+    #[hdl]
+    if let HdlSome(v) = shift_reg[0] {
+        connect(not_tx_reg, !v);
+    } else {
+        connect(not_tx_reg, false);
+    }
+
+    #[hdl]
+    let tick_count_reg = reg_builder()
+        .clock_domain(cd)
+        .reset(0u8.cast_to_static::<UIntInRange<0, { TICKS_PER_BAUD }>>());
+
+    #[hdl]
+    let next_tick_count = wire(tick_count_reg.ty());
+
+    connect(tick_count_reg, next_tick_count);
+
+    #[hdl]
+    if !tick {
+        connect(next_tick_count, tick_count_reg);
+    } else if tick_count_reg.cmp_ge(TICKS_PER_BAUD - 1) {
+        connect(next_tick_count, 0u8.cast_to(next_tick_count.ty()));
+    } else {
+        connect(
+            next_tick_count,
+            (tick_count_reg.cast_to(UInt[tick_count_reg.ty().bit_width()]) + 1u8)
+                .cast_to(next_tick_count.ty()),
+        );
+    }
+
+    #[hdl]
+    if tick & tick_count_reg.cmp_eq(0u8) {
+        #[hdl]
+        if let HdlSome(_) = shift_reg[0] {
+            for v in shift_reg.windows(2) {
+                connect(v[0], v[1]);
+            }
+            connect(shift_reg.last().expect("known to be non-empty"), HdlNone());
+        }
+        #[hdl]
+        if let HdlNone = shift_reg[1] {
+            // when shift_reg[1] is HdlNone that means shift_reg would be completely empty in the next clock
+            // cycle, so instead fill it with the next byte if there is one.
+            #[hdl]
+            if let HdlSome(byte) = input_buf_reg {
+                connect(input_buf_reg, HdlNone());
+                connect(shift_reg, [HdlSome(true); _]);
+                connect(shift_reg[0], HdlSome(false));
+                for (i, v) in (*shift_reg)[1..][..8].iter().enumerate() {
+                    connect(v, HdlSome(byte[i]));
+                }
+            }
+        }
+    }
+
+    #[hdl]
+    if let HdlSome(_) = input_buf_reg {
+        connect(input_byte.ready, false);
+    } else {
+        connect(input_byte.ready, true);
+        connect(input_buf_reg, input_byte.data);
+    }
+}
+
+/// `rx_synchronized` is [`peripherals::Uart::rx`], but after being synchronized to `cd.clk`.
+/// `output_byte` is `HdlSome` for 1 clock cycle for every received byte.
+#[hdl_module]
+pub fn receiver_no_queue() {
+    #[hdl]
+    let cd: ClockDomain = m.input();
+    #[hdl]
+    let tick: Bool = m.input();
+    #[hdl]
+    let rx_synchronized: Bool = m.input();
+    #[hdl]
+    let output_byte: HdlOption<UInt<8>> = m.output();
+
+    const BITS_PER_BYTE: usize = 8;
+
+    #[hdl]
+    let output_byte_reg: HdlOption<UInt<{ BITS_PER_BYTE }>> =
+        reg_builder().clock_domain(cd).reset(HdlNone());
+
+    connect(output_byte, output_byte_reg);
+    connect(output_byte_reg, HdlNone()); // by default always reset to HdlNone()
+
+    #[hdl]
+    let tick_count_reg = reg_builder()
+        .clock_domain(cd)
+        .reset(0u8.cast_to(UInt::range(0..TICKS_PER_BAUD)));
+
+    #[hdl]
+    let shift_reg: UInt<{ BITS_PER_BYTE }> = reg_builder().clock_domain(cd).reset(0u8);
+
+    #[hdl]
+    enum State {
+        WaitingForStartBit,
+        StartBit,
+        DataBits(UIntInRange<0, { BITS_PER_BYTE }>),
+        StopBit,
+    }
+
+    #[hdl]
+    let state_reg = reg_builder()
+        .clock_domain(cd)
+        .reset(State.WaitingForStartBit());
+
+    #[hdl]
+    if tick {
+        #[hdl]
+        match state_reg {
+            State::WaitingForStartBit => {
+                connect(tick_count_reg, tick_count_reg.ty().zero());
+                #[hdl]
+                if !rx_synchronized {
+                    connect(state_reg, State.StartBit());
+                }
+            }
+            State::StartBit =>
+            {
+                #[hdl]
+                if tick_count_reg.cmp_eq(TICKS_PER_BAUD - 1) {
+                    connect(tick_count_reg, tick_count_reg.ty().zero());
+                    connect(state_reg, State.DataBits(0u8.cast_to(State.DataBits)));
+                } else {
+                    connect_any(tick_count_reg, tick_count_reg + 1u8);
+                }
+            }
+            State::DataBits(count) => {
+                #[hdl]
+                if tick_count_reg.cmp_eq(TICKS_PER_BAUD - 1) {
+                    connect(tick_count_reg, tick_count_reg.ty().zero());
+                    #[hdl]
+                    if count.cmp_eq(BITS_PER_BYTE - 1) {
+                        connect(state_reg, State.StopBit());
+                        connect(output_byte_reg, HdlSome(shift_reg));
+                    } else {
+                        connect(
+                            state_reg,
+                            State.DataBits((count.cast_to(UInt[8]) + 1u8).cast_to(State.DataBits)),
+                        );
+                    }
+                } else {
+                    connect_any(tick_count_reg, tick_count_reg + 1u8);
+                }
+                #[hdl]
+                if tick_count_reg.cmp_eq(TICKS_PER_BAUD / 2) {
+                    connect_any(
+                        shift_reg,
+                        (shift_reg >> 1) | (rx_synchronized.cast_to_static::<UInt<1>>() << 7),
+                    );
+                }
+            }
+            State::StopBit => {
+                #[hdl]
+                if tick_count_reg.cmp_eq(TICKS_PER_BAUD / 2) {
+                    // go to WaitingForStartBit in the middle of the stop bit so we can adjust if the sender is faster than us.
+                    connect(tick_count_reg, tick_count_reg.ty().zero());
+                    connect(state_reg, State.WaitingForStartBit());
+                } else {
+                    connect_any(tick_count_reg, tick_count_reg + 1u8);
+                }
+            }
+        }
+    }
+}
+
+#[hdl]
+pub enum ReceiverQueueStatus {
+    QueueEmpty,
+    QueueNotEmpty,
+    QueueAlmostFull,
+    QueueFull,
+    QueueOverflowed,
+}
+
+impl ReceiverQueueStatus {
+    pub fn sim_as_u8(this: impl ToSimValue<Type = Self>) -> u8 {
+        SimValue::bits(&this.into_sim_value())
+            .cast_to_static::<UInt<8>>()
+            .as_int()
+    }
+    #[hdl]
+    pub fn for_queue_len_sim(current_count: usize, queue_size: NonZeroUsize) -> SimValue<Self> {
+        if current_count == 0 {
+            #[hdl(sim)]
+            ReceiverQueueStatus.QueueEmpty()
+        } else if current_count == queue_size.get() {
+            #[hdl(sim)]
+            ReceiverQueueStatus.QueueFull()
+        } else if current_count == queue_size.get() - 1 {
+            #[hdl(sim)]
+            ReceiverQueueStatus.QueueAlmostFull()
+        } else if current_count > queue_size.get() {
+            #[hdl(sim)]
+            ReceiverQueueStatus.QueueOverflowed()
+        } else {
+            #[hdl(sim)]
+            ReceiverQueueStatus.QueueNotEmpty()
+        }
+    }
+    #[hdl]
+    pub fn for_queue_len_as_u8(current_count: usize, queue_size: NonZeroUsize) -> u8 {
+        Self::sim_as_u8(Self::for_queue_len_sim(current_count, queue_size))
+    }
+}
+
+/// `rx_synchronized` is [`peripherals::Uart::rx`], but after being synchronized to `cd.clk`.
+#[hdl_module]
+pub fn receiver(queue_capacity: NonZeroUsize) {
+    #[hdl]
+    let cd: ClockDomain = m.input();
+    #[hdl]
+    let tick: Bool = m.input();
+    #[hdl]
+    let rx_synchronized: Bool = m.input();
+    #[hdl]
+    let output_byte: ReadyValid<UInt<8>> = m.output();
+    #[hdl]
+    let queue_status: ReceiverQueueStatus = m.output();
+
+    #[hdl]
+    let queue = instance(queue(UInt::<8>::new_static(), queue_capacity, false, false));
+
+    connect(queue.cd, cd);
+    connect(output_byte, queue.out);
+
+    #[hdl]
+    let queue_overflowed_reg = reg_builder().clock_domain(cd).reset(false);
+
+    #[hdl]
+    if queue_overflowed_reg {
+        connect(queue_status, ReceiverQueueStatus.QueueOverflowed());
+    } else if queue.count.cmp_eq(0u8) {
+        connect(queue_status, ReceiverQueueStatus.QueueEmpty());
+    } else if queue.count.cmp_eq(queue_capacity) {
+        connect(queue_status, ReceiverQueueStatus.QueueFull());
+    } else if queue.count.cmp_eq(queue_capacity.get() - 1) {
+        connect(queue_status, ReceiverQueueStatus.QueueAlmostFull());
+    } else {
+        connect(queue_status, ReceiverQueueStatus.QueueNotEmpty());
+    }
+
+    #[hdl]
+    if ReadyValid::firing(output_byte) {
+        // clear overflow when a byte is read from the queue
+        connect(queue_overflowed_reg, false);
+    }
+
+    // we ignore queue.inp.ready other than noting an overflow when there was data but the queue wasn't ready
+    #[hdl]
+    if !queue.inp.ready {
+        #[hdl]
+        if let HdlSome(_) = queue.inp.data {
+            connect(queue_overflowed_reg, true);
+        }
+    }
+
+    #[hdl]
+    let inner = instance(receiver_no_queue());
+    connect(inner.cd, cd);
+    connect(inner.tick, tick);
+    connect(inner.rx_synchronized, rx_synchronized);
+    connect(queue.inp.data, inner.output_byte);
+}
+
+pub const SIMPLE_UART_RECEIVE_OFFSET: u64 = 0;
+pub const SIMPLE_UART_TRANSMIT_OFFSET: u64 = 0;
+pub const SIMPLE_UART_STATUS_OFFSET: u64 = 1;
+pub const SIMPLE_UART_SIZE: u64 = 2;
+
+#[hdl(no_static)]
+struct Operation<C: PhantomConstGet<CpuConfig> + PhantomConstCpuConfig> {
+    start: MemoryOperationStart<C>,
+    finish: HdlOption<MemoryOperationFinish<C>>,
+}
+
+#[hdl_module]
+pub fn simple_uart(
+    config: PhantomConst<CpuConfig>,
+    clock_input_properties: PhantomConst<peripherals::ClockInputProperties>,
+    baud_rate: f64,
+    receiver_queue_size: NonZeroUsize,
+) {
+    #[hdl]
+    let cd: ClockDomain = m.input();
+    #[hdl]
+    let memory_interface: MemoryInterface<PhantomConst<CpuConfig>> =
+        m.input(MemoryInterface[config]);
+    #[hdl]
+    let uart: peripherals::Uart = m.output();
+
+    #[hdl]
+    let rx_sync_intermediate_reg: Bool = reg_builder().clock_domain(cd).reset(true);
+    annotate(rx_sync_intermediate_reg, DontTouchAnnotation);
+    #[hdl]
+    let rx_sync_final_reg: Bool = reg_builder().clock_domain(cd).reset(true);
+    annotate(rx_sync_final_reg, DontTouchAnnotation);
+    connect(rx_sync_intermediate_reg, uart.rx);
+    connect(rx_sync_final_reg, rx_sync_intermediate_reg);
+    #[hdl]
+    let rx_synchronized: Bool = wire();
+    annotate(rx_synchronized, DontTouchAnnotation);
+    connect(rx_synchronized, rx_sync_final_reg);
+
+    #[hdl]
+    let clk_gen = instance(uart_clock_gen(clock_input_properties, baud_rate));
+    connect(clk_gen.cd, cd);
+
+    #[hdl]
+    let transmitter = instance(transmitter());
+    connect(transmitter.cd, cd);
+    connect(transmitter.tick, clk_gen.tick);
+    connect(uart.tx, transmitter.tx);
+
+    #[hdl]
+    let receiver = instance(receiver(receiver_queue_size));
+    connect(receiver.cd, cd);
+    connect(receiver.tick, clk_gen.tick);
+    connect(receiver.rx_synchronized, rx_synchronized);
+
+    #[hdl]
+    let operation_reg = reg_builder()
+        .clock_domain(cd)
+        .reset(HdlOption[Operation[config]].HdlNone());
+
+    let next_fetch_block_ids_ty = memory_interface.ty().next_fetch_block_ids.HdlSome;
+    #[hdl]
+    if let HdlSome(operation) = operation_reg {
+        #[hdl]
+        let MemoryInterface::<_> {
+            start,
+            finish,
+            next_fetch_block_ids,
+            config: _,
+        } = memory_interface;
+        connect(start.ready, false);
+        connect(finish.data, operation.finish);
+        connect(
+            next_fetch_block_ids,
+            HdlSome(ArrayVec::from_parts_unchecked(
+                repeat(
+                    operation.start.fetch_block_id,
+                    next_fetch_block_ids_ty.capacity(),
+                ),
+                1u8.cast_to(next_fetch_block_ids_ty.len_ty()),
+            )),
+        );
+        connect(transmitter.input_byte.data, HdlNone());
+        connect(receiver.output_byte.ready, false);
+        #[hdl]
+        if let HdlSome(_) = operation.finish {
+            #[hdl]
+            if finish.ready {
+                connect(operation_reg, operation_reg.ty().HdlNone());
+            }
+        } else {
+            #[hdl]
+            let MemoryOperationStart::<_> {
+                kind,
+                addr,
+                write_data,
+                rw_mask,
+                fetch_block_id: _,
+                config: _,
+            } = operation.start;
+            #[hdl]
+            let valid_addr = wire();
+            connect(valid_addr, true);
+            #[hdl]
+            let all_ready = wire();
+            connect(all_ready, true);
+            #[hdl]
+            let read_data = wire(write_data.ty());
+            for (byte_index, ((rw_mask, write_data), read_data)) in rw_mask
+                .into_iter()
+                .zip(write_data)
+                .zip(read_data)
+                .enumerate()
+            {
+                let byte_addr = (addr | byte_index).cast_to_static::<UInt<64>>();
+                connect(read_data, 0u8);
+                #[hdl]
+                if rw_mask {
+                    #[hdl]
+                    match kind {
+                        MemoryOperationKind::Read => {
+                            #[hdl]
+                            if byte_addr.cmp_eq(SIMPLE_UART_RECEIVE_OFFSET) {
+                                connect(receiver.output_byte.ready, valid_addr);
+                                #[hdl]
+                                if let HdlSome(byte) = receiver.output_byte.data {
+                                    connect(read_data, byte);
+                                }
+                                // if there is no byte ready yet, we read a zero to avoid blocking the CPU on external inputs.
+                            } else if byte_addr.cmp_eq(SIMPLE_UART_STATUS_OFFSET) {
+                                connect(
+                                    read_data,
+                                    receiver
+                                        .queue_status
+                                        .cast_to_bits()
+                                        .cast_to_static::<UInt<8>>(),
+                                );
+                            } else {
+                                connect(valid_addr, false);
+                            }
+                        }
+                        MemoryOperationKind::Write => {
+                            #[hdl]
+                            if byte_addr.cmp_eq(SIMPLE_UART_TRANSMIT_OFFSET) {
+                                #[hdl]
+                                if !transmitter.input_byte.ready {
+                                    connect(all_ready, false);
+                                }
+                                #[hdl]
+                                if valid_addr {
+                                    connect(transmitter.input_byte.data, HdlSome(write_data));
+                                }
+                            } else {
+                                connect(valid_addr, false);
+                            }
+                        }
+                    }
+                }
+            }
+            #[hdl]
+            if !valid_addr {
+                connect(
+                    operation_reg,
+                    HdlSome(
+                        #[hdl]
+                        Operation::<_> {
+                            start: operation.start,
+                            finish: HdlSome(
+                                #[hdl]
+                                MemoryOperationFinish::<_> {
+                                    kind: MemoryOperationFinishKind
+                                        .Error(MemoryOperationErrorKind.Generic()),
+                                    read_data,
+                                    config,
+                                },
+                            ),
+                        },
+                    ),
+                );
+            } else if all_ready {
+                connect(
+                    operation_reg,
+                    HdlSome(
+                        #[hdl]
+                        Operation::<_> {
+                            start: operation.start,
+                            finish: HdlSome(
+                                #[hdl]
+                                MemoryOperationFinish::<_> {
+                                    kind: MemoryOperationFinishKind.Success(kind),
+                                    read_data,
+                                    config,
+                                },
+                            ),
+                        },
+                    ),
+                );
+            }
+        }
+    } else {
+        #[hdl]
+        let MemoryInterface::<_> {
+            start,
+            finish,
+            next_fetch_block_ids,
+            config: _,
+        } = memory_interface;
+        connect(start.ready, true);
+        connect(finish.data, finish.ty().data.HdlNone());
+        connect(
+            next_fetch_block_ids,
+            HdlSome(next_fetch_block_ids_ty.new_sim(next_fetch_block_ids_ty.element().zero())),
+        );
+        #[hdl]
+        if let HdlSome(start) = start.data {
+            connect(
+                operation_reg,
+                HdlSome(
+                    #[hdl]
+                    Operation::<_> {
+                        start,
+                        finish: operation_reg.ty().HdlSome.finish.HdlNone(),
+                    },
+                ),
+            );
+        }
+        connect(transmitter.input_byte.data, HdlNone());
+        connect(receiver.output_byte.ready, false);
+    }
+}
--- a/crates/cpu/src/next_pc.rs
+++ b/crates/cpu/src/next_pc.rs
--- a/crates/cpu/src/next_pc/next_pc.mermaid
+++ b/crates/cpu/src/next_pc/next_pc.mermaid
@ -0,0 +1,24 @@
+%% SPDX-License-Identifier: LGPL-3.0-or-later
+%% See Notices.txt for copyright information
+stateDiagram-v2
+    direction LR
+
+    state "Next PC" as next_pc
+    [*] --> next_pc
+
+    state "Fetch/Decode" as fetch_decode
+    next_pc --> fetch_decode
+
+    state "Branch Predictor" as br_pred
+    next_pc --> br_pred
+    br_pred --> next_pc: cancel following
+
+    state "Post-decode" as post_decode
+    fetch_decode --> post_decode
+    br_pred --> post_decode
+    post_decode --> next_pc: cancel following
+
+    state "Execute/Retire" as execute_retire
+    post_decode --> execute_retire
+    execute_retire --> [*]
+    execute_retire --> next_pc: cancel following
--- a/crates/cpu/src/powerisa_instructions_xml.rs
+++ b/crates/cpu/src/powerisa_instructions_xml.rs
--- a/crates/cpu/src/reg_alloc.rs
+++ b/crates/cpu/src/reg_alloc.rs
@ -241,7 +241,7 @@ pub fn reg_alloc(config: &CpuConfig) {
        // TODO: finish
        connect(
            rob.renamed_insns_in[fetch_index].data,
-            Expr::ty(rob).renamed_insns_in.element().data.HdlNone(),
+            rob.ty().renamed_insns_in.element().data.HdlNone(),
        );
        // TODO: finish
        connect(
@ -263,7 +263,7 @@ pub fn reg_alloc(config: &CpuConfig) {
        );
        connect(
            renamed_mops[fetch_index],
-            Expr::ty(renamed_mops).element().HdlNone(),
+            renamed_mops.ty().element().HdlNone(),
        );
        #[hdl]
        struct RenameTableReadPort<T> {
@ -332,7 +332,7 @@ pub fn reg_alloc(config: &CpuConfig) {
                let write_port = wire_with_loc(
                    &format!("{table_name}_{fetch_index}_{}", reg_kind.reg_name()),
                    SourceLocation::caller(),
-                    Expr::ty(write_port_),
+                    write_port_.ty(),
                );
                connect(write_port_, write_port);
                write_ports.push_back(write_port);
@ -343,7 +343,7 @@ pub fn reg_alloc(config: &CpuConfig) {
                        addr: 0_hdl_u0,
                        en: false,
                        clk: cd.clk,
-                        data: Expr::ty(write_port.data).uninit(),
+                        data: write_port.data.ty().uninit(),
                        mask: splat_mask(config.p_reg_num(), true.to_expr()),
                    },
                );
@ -375,7 +375,7 @@ pub fn reg_alloc(config: &CpuConfig) {
                    config.renamed_mop_in_unit().TransformedMove,
                    |renamed_mop, renamed_move_op: Expr<MoveRegMOp<_, _>>| {
                        // TODO: finish handling MoveRegMOp
-                        connect(renamed_mop, Expr::ty(renamed_mop).HdlNone());
+                        connect(renamed_mop, renamed_mop.ty().HdlNone());
                    },
                );
                connect(
@ -429,7 +429,7 @@ pub fn reg_alloc(config: &CpuConfig) {
                    );
                    connect(
                        selected_unit_index_leaf,
-                        Expr::ty(selected_unit_index_leaf).HdlNone(),
+                        selected_unit_index_leaf.ty().HdlNone(),
                    );
                    let unit_index_wire = wire_with_loc(
                        &format!("unit_index_{fetch_index}_{unit_index}"),
@ -447,7 +447,7 @@ pub fn reg_alloc(config: &CpuConfig) {
                    let selected_unit_index_node = wire_with_loc(
                        &format!("selected_unit_index_node_{fetch_index}_{state}"),
                        SourceLocation::caller(),
-                        Expr::ty(l),
+                        l.ty(),
                    );
                    *state += 1;
                    connect(selected_unit_index_node, l);
@ -516,7 +516,7 @@ pub fn reg_alloc(config: &CpuConfig) {
        connect(unit_free_regs_tracker.alloc_out[0].ready, false);
        connect(
            unit_to_reg_alloc.input.data,
-            Expr::ty(unit_to_reg_alloc.input).data.HdlNone(),
+            unit_to_reg_alloc.input.ty().data.HdlNone(),
        );
        for fetch_index in 0..config.fetch_width.get() {
            #[hdl]
@ -550,7 +550,7 @@ pub fn reg_alloc(config: &CpuConfig) {
                    } else {
                        connect(
                            unit_to_reg_alloc.input.data,
-                            HdlSome(Expr::ty(unit_to_reg_alloc.input).data.HdlSome.uninit()),
+                            HdlSome(unit_to_reg_alloc.input.ty().data.HdlSome.uninit()),
                        );
                        // FIXME: add hdl_assert(cd.clk, false.to_expr(), "");
                    }
@ -578,7 +578,8 @@ pub fn reg_alloc(config: &CpuConfig) {
        connect(unit_to_reg_alloc.unit_forwarding_info, unit_forwarding_info);
        connect(
            unit_forwarding_info.unit_output_writes[unit_index],
-            Expr::ty(unit_forwarding_info)
+            unit_forwarding_info
+                .ty()
                .unit_output_writes
                .element()
                .HdlNone(),
--- a/crates/cpu/src/reg_alloc/unit_free_regs_tracker.rs
+++ b/crates/cpu/src/reg_alloc/unit_free_regs_tracker.rs
@ -73,7 +73,7 @@ pub fn unit_free_regs_tracker(
            let reduced_alloc_nums = wire_with_loc(
                &format!("reduced_alloc_nums_{}_{}", range.start, range.end),
                SourceLocation::caller(),
-                Array[UInt[Expr::ty(l.alloc_nums).element().width() + 1]][alloc_at_once.get()],
+                Array[UInt[l.alloc_nums.ty().element().width() + 1]][alloc_at_once.get()],
            );
            for alloc_index in 0..alloc_at_once.get() {
                #[hdl]
@ -120,10 +120,7 @@ pub fn unit_free_regs_tracker(
 #[cfg(test)]
 mod tests {
    use super::*;
-    use fayalite::{
-        cli::FormalMode, firrtl::ExportOptions,
-        module::transform::simplify_enums::SimplifyEnumsKind, testing::assert_formal,
-    };
+    use fayalite::{firrtl::ExportOptions, module::transform::simplify_enums::SimplifyEnumsKind};
    use std::num::NonZero;

    fn test_unit_free_regs_tracker(
@ -198,7 +195,7 @@ mod tests {
                }
            }
            #[hdl]
-            let free_before_alloc_array = wire(Array[Expr::ty(free_reg)][alloc_at_once.get() + 1]);
+            let free_before_alloc_array = wire(Array[free_reg.ty()][alloc_at_once.get() + 1]);
            connect(free_before_alloc_array[0], free_reg);
            #[hdl]
            let expected_alloc = wire(Array[HdlOption[reg_num_ty]][alloc_at_once.get()]);
--- a/crates/cpu/src/register.rs
+++ b/crates/cpu/src/register.rs
@ -1,6 +1,14 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
-use fayalite::prelude::*;
+
+use crate::instruction::ConditionMode;
+use fayalite::{
+    expr::CastToImpl,
+    int::{BoolOrIntType, UIntInRange},
+    prelude::*,
+    ty::StaticType,
+};
+use std::fmt;

 #[hdl]
 pub enum FlagsMode {
@ -8,95 +16,645 @@ pub enum FlagsMode {
    X86(PRegFlagsX86),
 }

+trait PRegFlagsViewTraitSealed {
+    type UnusedInner<T>: AsRef<[T]>
+        + AsMut<[T]>
+        + IntoIterator<
+            Item = T,
+            IntoIter: DoubleEndedIterator<Item = T>
+                          + ExactSizeIterator
+                          + std::iter::FusedIterator
+                          + Default,
+        >;
+    const UNUSED_INNER_LEN: usize;
+    fn unused_inner_map<T, R>(
+        v: Self::UnusedInner<T>,
+        f: impl FnMut(T) -> R,
+    ) -> Self::UnusedInner<R>;
+    fn unused_inner_from_fn<T>(f: impl FnMut(usize) -> T) -> Self::UnusedInner<T>;
+    fn unused_inner_each_ref<T>(v: &Self::UnusedInner<T>) -> Self::UnusedInner<&T>;
+    fn unused_inner_each_mut<T>(v: &mut Self::UnusedInner<T>) -> Self::UnusedInner<&mut T>;
+}
+
+#[expect(private_bounds)]
+pub trait PRegFlagsViewTrait: Type + PRegFlagsViewTraitSealed {
+    type View<T>;
+    fn view<T: Type>(flags: impl ToExpr<Type = PRegFlags<T>>) -> Self::View<Expr<T>>;
+    fn view_sim<T: Type>(flags: impl ToSimValue<Type = PRegFlags<T>>) -> Self::View<SimValue<T>>;
+    fn view_sim_ref<T: Type>(flags: &SimValue<PRegFlags<T>>) -> Self::View<&SimValue<T>>;
+    fn view_sim_mut<T: Type>(flags: &mut SimValue<PRegFlags<T>>) -> Self::View<&mut SimValue<T>>;
+    fn from_view<T: ToExpr>(view: Self::View<T>) -> Expr<PRegFlags<T::Type>>;
+    fn from_view_sim<T: ToSimValue>(view: Self::View<T>) -> SimValue<PRegFlags<T::Type>>;
+    fn view_unused_into_view<T>(unused: ViewUnused<T, PRegFlagsAllUnused>) -> Self::View<T>;
+    fn view_into_view_unused<T>(view: Self::View<T>) -> ViewUnused<T, PRegFlagsAllUnused>;
+}
+
+pub struct ViewUnused<T, V: PRegFlagsViewTrait>(V::UnusedInner<T>);
+
+pub struct ViewUnusedIntoIter<T, V: PRegFlagsViewTrait>(
+    <V::UnusedInner<T> as IntoIterator>::IntoIter,
+);
+
+impl<T, V: PRegFlagsViewTrait> Iterator for ViewUnusedIntoIter<T, V> {
+    type Item = T;
+
+    fn next(&mut self) -> Option<Self::Item> {
+        self.0.next()
+    }
+
+    fn size_hint(&self) -> (usize, Option<usize>) {
+        self.0.size_hint()
+    }
+
+    fn fold<B, F>(self, init: B, f: F) -> B
+    where
+        F: FnMut(B, Self::Item) -> B,
+    {
+        self.0.fold(init, f)
+    }
+
+    fn count(self) -> usize {
+        self.0.count()
+    }
+
+    fn last(self) -> Option<Self::Item> {
+        self.0.last()
+    }
+}
+
+impl<T, V: PRegFlagsViewTrait> DoubleEndedIterator for ViewUnusedIntoIter<T, V> {
+    fn next_back(&mut self) -> Option<Self::Item> {
+        self.0.next_back()
+    }
+
+    fn rfold<B, F>(self, init: B, f: F) -> B
+    where
+        F: FnMut(B, Self::Item) -> B,
+    {
+        self.0.rfold(init, f)
+    }
+}
+
+impl<T, V: PRegFlagsViewTrait> ExactSizeIterator for ViewUnusedIntoIter<T, V> {
+    fn len(&self) -> usize {
+        self.0.len()
+    }
+}
+
+impl<T, V: PRegFlagsViewTrait> std::iter::FusedIterator for ViewUnusedIntoIter<T, V> {}
+
+impl<T, V: PRegFlagsViewTrait> Default for ViewUnusedIntoIter<T, V> {
+    fn default() -> Self {
+        Self(Default::default())
+    }
+}
+
+impl<T: Clone, V: PRegFlagsViewTrait> Clone for ViewUnusedIntoIter<T, V>
+where
+    <V::UnusedInner<T> as IntoIterator>::IntoIter: Clone,
+{
+    fn clone(&self) -> Self {
+        Self(self.0.clone())
+    }
+}
+
+impl<T, V: PRegFlagsViewTrait> IntoIterator for ViewUnused<T, V> {
+    type Item = T;
+    type IntoIter = ViewUnusedIntoIter<T, V>;
+
+    fn into_iter(self) -> Self::IntoIter {
+        ViewUnusedIntoIter(self.0.into_iter())
+    }
+}
+
+impl<T: Default, V: PRegFlagsViewTrait> Default for ViewUnused<T, V> {
+    fn default() -> Self {
+        Self::from_fn(|_| T::default())
+    }
+}
+
+impl<T, V: PRegFlagsViewTrait> ViewUnused<T, V> {
+    pub fn iter(&self) -> std::slice::Iter<'_, T> {
+        self.into_iter()
+    }
+    pub fn iter_mut(&mut self) -> std::slice::IterMut<'_, T> {
+        self.into_iter()
+    }
+    pub fn from_fn(f: impl FnMut(usize) -> T) -> Self {
+        ViewUnused(V::unused_inner_from_fn(f))
+    }
+    pub fn each_ref(&self) -> ViewUnused<&T, V> {
+        ViewUnused(V::unused_inner_each_ref(&self.0))
+    }
+    pub fn each_mut(&mut self) -> ViewUnused<&mut T, V> {
+        ViewUnused(V::unused_inner_each_mut(&mut self.0))
+    }
+    pub fn map<R>(self, f: impl FnMut(T) -> R) -> ViewUnused<R, V> {
+        ViewUnused(V::unused_inner_map(self.0, f))
+    }
+    pub fn zip<U>(self, other: ViewUnused<U, V>) -> ViewUnused<(T, U), V> {
+        let mut iter = self.into_iter().zip(other);
+        ViewUnused::from_fn(|_| iter.next().expect("known to be Some"))
+    }
+    pub fn splat(v: T) -> Self
+    where
+        T: Clone,
+    {
+        let mut v = Some(v);
+        Self::from_fn(|i| {
+            let v = if i == V::UNUSED_INNER_LEN - 1 {
+                v.take()
+            } else {
+                v.clone()
+            };
+            let Some(v) = v else {
+                unreachable!();
+            };
+            v
+        })
+    }
+    pub fn splat_copied(v: T) -> Self
+    where
+        T: Copy,
+    {
+        Self::from_fn(|_| v)
+    }
+}
+
+impl<T: BoolOrIntType, V: PRegFlagsViewTrait> ViewUnused<SimValue<T>, V> {
+    pub fn clear(&mut self) {
+        for i in self.iter_mut() {
+            SimValue::bits_mut(i).bits_mut().fill(false);
+        }
+    }
+}
+
+impl<T: BoolOrIntType, V: PRegFlagsViewTrait> ViewUnused<&'_ mut SimValue<T>, V> {
+    pub fn clear(&mut self) {
+        for i in self.iter_mut() {
+            SimValue::bits_mut(i).bits_mut().fill(false);
+        }
+    }
+}
+
+impl<T: BoolOrIntType, V: PRegFlagsViewTrait> ViewUnused<Expr<T>, V>
+where
+    UInt: CastToImpl<T, ValueOutput: ToExpr>,
+{
+    pub fn clear(self) {
+        for i in self {
+            connect(i, UInt::new_dyn(i.ty().width()).zero().cast_to(i.ty()));
+        }
+    }
+}
+
+impl<'a, T, V: PRegFlagsViewTrait> IntoIterator for &'a ViewUnused<T, V> {
+    type Item = &'a T;
+    type IntoIter = std::slice::Iter<'a, T>;
+
+    fn into_iter(self) -> Self::IntoIter {
+        self.0.as_ref().iter()
+    }
+}
+
+impl<'a, T, V: PRegFlagsViewTrait> IntoIterator for &'a mut ViewUnused<T, V> {
+    type Item = &'a mut T;
+    type IntoIter = std::slice::IterMut<'a, T>;
+
+    fn into_iter(self) -> Self::IntoIter {
+        self.0.as_mut().iter_mut()
+    }
+}
+
+impl<T: Clone, V: PRegFlagsViewTrait> Clone for ViewUnused<T, V>
+where
+    V::UnusedInner<T>: Clone,
+{
+    fn clone(&self) -> Self {
+        Self(self.0.clone())
+    }
+}
+
+impl<T: Copy, V: PRegFlagsViewTrait> Copy for ViewUnused<T, V> where V::UnusedInner<T>: Copy {}
+
+impl<T: fmt::Debug, V: PRegFlagsViewTrait> fmt::Debug for ViewUnused<T, V>
+where
+    V::UnusedInner<T>: fmt::Debug,
+{
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        f.debug_tuple("ViewUnused").field(&self.0).finish()
+    }
+}
+
+macro_rules! impl_view_trait {
+    (
+        $(#[$flags_mode_meta:meta])*
+        $flags_mode_vis:vis struct $FlagsMode:ident {}
+
+        $(#[$view_meta:meta])*
+        $view_vis:vis struct $View:ident {
+            $(#[$unused_field_meta:meta])*
+            $unused_vis:vis $unused:ident: ViewUnused([$($unused_field:ident),* $(,)?]),
+            $($(#[$view_field_meta:meta])*
+            $view_field_vis:vis $view_field:ident: $flags_field:ident,)*
+        }
+    ) => {
+        $(#[$flags_mode_meta])*
+        $flags_mode_vis struct $FlagsMode {}
+
+        $(#[$view_meta])*
+        $view_vis struct $View<T> {
+            $(#[$unused_field_meta])*
+            $unused_vis $unused: ViewUnused<T, $FlagsMode>,
+            $($(#[$view_field_meta])*
+            $view_field_vis $view_field: T,)*
+        }
+
+        impl<T> $View<&'_ mut T> {
+            $view_vis const fn reborrow<'a>(&'a mut self) -> $View<&'a mut T> {
+                let $View {
+                    $unused: ViewUnused([$($unused_field,)*]),
+                    $($view_field: $flags_field,)*
+                } = self;
+                $View {
+                    $unused: ViewUnused([$(&mut **$unused_field,)*]),
+                    $($view_field: &mut **$flags_field,)*
+                }
+            }
+        }
+        impl<T> $View<T> {
+            $view_vis fn splat(v: T) -> Self
+            where
+                T: Clone,
+            {
+                $View {
+                    $($view_field: v.clone(),)*
+                    $unused: ViewUnused::splat(v),
+                }
+            }
+            $view_vis const fn splat_copied(v: T) -> Self
+            where
+                T: Copy,
+            {
+                $View {
+                    $($view_field: v,)*
+                    $unused: ViewUnused([v; _]),
+                }
+            }
+            $view_vis fn map<R>(self, mut f: impl FnMut(T) -> R) -> $View<R> {
+                #![allow(unused_mut)]
+                let $View {
+                    $unused,
+                    $($view_field,)*
+                } = self;
+                $View {
+                    $($view_field: f($view_field),)*
+                    $unused: $unused.map(f),
+                }
+            }
+            $view_vis fn zip<U>(self, other: $View<U>) -> $View<(T, U)> {
+                struct Fields<T> {
+                    $($unused_field: T,)*
+                    $($flags_field: T,)*
+                }
+                let $View {
+                    $unused: ViewUnused([$($unused_field,)*]),
+                    $($view_field: $flags_field,)*
+                } = self;
+                let this = Fields {
+                    $($unused_field,)*
+                    $($flags_field,)*
+                };
+                let $View {
+                    $unused: ViewUnused([$($unused_field,)*]),
+                    $($view_field: $flags_field,)*
+                } = other;
+                let other = Fields {
+                    $($unused_field,)*
+                    $($flags_field,)*
+                };
+                $View {
+                    $unused: ViewUnused([$((this.$unused_field, other.$unused_field),)*]),
+                    $($view_field: (this.$flags_field, other.$flags_field),)*
+                }
+            }
+        }
+
+        impl PRegFlagsViewTraitSealed for $FlagsMode {
+            type UnusedInner<T> = [T; Self::UNUSED_INNER_LEN];
+            const UNUSED_INNER_LEN: usize = {
+                let v: &[&str] = &[$(stringify!($unused_field),)*];
+                v.len()
+            };
+            fn unused_inner_map<T, R>(
+                v: Self::UnusedInner<T>,
+                f: impl FnMut(T) -> R,
+            ) -> Self::UnusedInner<R> {
+                v.map(f)
+            }
+            fn unused_inner_from_fn<T>(f: impl FnMut(usize) -> T) -> Self::UnusedInner<T> {
+                std::array::from_fn(f)
+            }
+            fn unused_inner_each_ref<T>(
+                v: &Self::UnusedInner<T>,
+            ) -> Self::UnusedInner<&T> {
+                v.each_ref()
+            }
+            fn unused_inner_each_mut<T>(
+                v: &mut Self::UnusedInner<T>,
+            ) -> Self::UnusedInner<&mut T> {
+                v.each_mut()
+            }
+        }
+
+        impl PRegFlagsViewTrait for $FlagsMode {
+            type View<T> = $View<T>;
+
+            #[hdl]
+            fn view<T: Type>(flags: impl ToExpr<Type = PRegFlags<T>>) -> Self::View<Expr<T>> {
+                #[hdl]
+                let PRegFlags::<T> {
+                    $($unused_field,)*
+                    $($flags_field,)*
+                } = flags.to_expr();
+                $View {
+                    $unused: ViewUnused([$($unused_field,)*]),
+                    $($view_field: $flags_field,)*
+                }
+            }
+
+            #[hdl]
+            fn view_sim<T: Type>(flags: impl ToSimValue<Type = PRegFlags<T>>) -> Self::View<SimValue<T>> {
+                #[hdl(sim)]
+                let PRegFlags::<T> {
+                    $($unused_field,)*
+                    $($flags_field,)*
+                } = flags.into_sim_value();
+                $View {
+                    $unused: ViewUnused([$($unused_field,)*]),
+                    $($view_field: $flags_field,)*
+                }
+            }
+
+            #[hdl]
+            fn view_sim_ref<T: Type>(flags: &SimValue<PRegFlags<T>>) -> Self::View<&SimValue<T>> {
+                #[hdl(sim)]
+                let PRegFlags::<T> {
+                    $($unused_field,)*
+                    $($flags_field,)*
+                } = flags;
+                $View {
+                    $unused: ViewUnused([$($unused_field,)*]),
+                    $($view_field: $flags_field,)*
+                }
+            }
+
+            #[hdl]
+            fn view_sim_mut<T: Type>(flags: &mut SimValue<PRegFlags<T>>) -> Self::View<&mut SimValue<T>> {
+                #[hdl(sim)]
+                let PRegFlags::<T> {
+                    $($unused_field,)*
+                    $($flags_field,)*
+                } = flags;
+                $View {
+                    $unused: ViewUnused([$($unused_field,)*]),
+                    $($view_field: $flags_field,)*
+                }
+            }
+
+            #[hdl]
+            fn from_view<T: ToExpr>(view: Self::View<T>) -> Expr<PRegFlags<T::Type>> {
+                let $View {
+                    $unused: ViewUnused([$($unused_field,)*]),
+                    $($view_field: $flags_field,)*
+                } = view;
+                #[hdl]
+                PRegFlags::<_> {
+                    $($unused_field,)*
+                    $($flags_field,)*
+                }
+            }
+
+            #[hdl]
+            fn from_view_sim<T: ToSimValue>(view: Self::View<T>) -> SimValue<PRegFlags<T::Type>> {
+                let $View {
+                    $unused: ViewUnused([$($unused_field,)*]),
+                    $($view_field: $flags_field,)*
+                } = view;
+                #[hdl(sim)]
+                PRegFlags::<_> {
+                    $($unused_field,)*
+                    $($flags_field,)*
+                }
+            }
+
+            fn view_unused_into_view<T>(unused: ViewUnused<T, PRegFlagsAllUnused>) -> Self::View<T> {
+                let fields = Fields::from_view_unused(unused);
+                $View {
+                    $unused: ViewUnused([$(fields.$unused_field,)*]),
+                    $($view_field: fields.$flags_field,)*
+                }
+            }
+
+            fn view_into_view_unused<T>(view: Self::View<T>) -> ViewUnused<T, PRegFlagsAllUnused> {
+                let $View {
+                    $unused: ViewUnused([$($unused_field,)*]),
+                    $($view_field: $flags_field,)*
+                } = view;
+                let fields = Fields {
+                    $($unused_field,)*
+                    $($flags_field,)*
+                };
+                fields.into_view_unused()
+            }
+        }
+    };
+}
+
+impl_view_trait! {
    #[hdl(cmp_eq)]
    pub struct PRegFlagsPowerISA {}

-impl PRegFlagsPowerISA {
-    pub fn xer_ca(flags: impl ToExpr<Type = PRegFlags>) -> Expr<Bool> {
-        flags.to_expr().pwr_ca_x86_cf
-    }
-    pub fn xer_ca32(flags: impl ToExpr<Type = PRegFlags>) -> Expr<Bool> {
-        flags.to_expr().pwr_ca32_x86_af
-    }
-    pub fn xer_ov(flags: impl ToExpr<Type = PRegFlags>) -> Expr<Bool> {
-        flags.to_expr().pwr_ov_x86_of
-    }
-    pub fn xer_ov32(flags: impl ToExpr<Type = PRegFlags>) -> Expr<Bool> {
-        flags.to_expr().pwr_ov32_x86_df
-    }
+    #[derive(Copy, Clone, Debug)]
+    #[non_exhaustive]
+    pub struct PRegFlagsPowerISAView {
+        pub unused: ViewUnused([]),
+        pub xer_ca: pwr_ca_x86_cf,
+        pub xer_ca32: pwr_ca32_x86_af,
+        pub xer_ov: pwr_ov_x86_of,
+        pub xer_ov32: pwr_ov32_x86_df,
+        pub cr_lt: pwr_cr_lt_x86_sf,
+        pub cr_gt: pwr_cr_gt_x86_pf,
+        pub cr_eq: pwr_cr_eq_x86_zf,
        /// both `CR<N>.SO` and `XER.SO` since instructions that write to both always write the same value
-    pub fn so(flags: impl ToExpr<Type = PRegFlags>) -> Expr<Bool> {
-        flags.to_expr().pwr_so
-    }
-    pub fn cr_lt(flags: impl ToExpr<Type = PRegFlags>) -> Expr<Bool> {
-        flags.to_expr().pwr_cr_lt_x86_sf
-    }
-    pub fn cr_gt(flags: impl ToExpr<Type = PRegFlags>) -> Expr<Bool> {
-        flags.to_expr().pwr_cr_gt_x86_pf
-    }
-    pub fn cr_eq(flags: impl ToExpr<Type = PRegFlags>) -> Expr<Bool> {
-        flags.to_expr().pwr_cr_eq_x86_zf
-    }
-    #[hdl]
-    pub fn clear_unused(flags: impl ToExpr<Type = PRegFlags>) {
-        // list all flags explicitly so we don't miss handling any new flags
-        #[hdl]
-        let PRegFlags {
-            pwr_ca_x86_cf: _,
-            pwr_ca32_x86_af: _,
-            pwr_ov_x86_of: _,
-            pwr_ov32_x86_df: _,
-            pwr_cr_lt_x86_sf: _,
-            pwr_cr_gt_x86_pf: _,
-            pwr_cr_eq_x86_zf: _,
-            pwr_so: _,
-        } = flags;
+        pub so: pwr_so,
    }
 }

+impl PRegFlagsPowerISAView<Option<usize>> {
+    pub const CR_BIT_LE_INDEXES: Self = {
+        let mut v = Self::splat_copied(None);
+        let bits = v.cr_bits_lsb0_mut();
+        let mut i = 0;
+        while i < bits.len() {
+            *bits[i] = Some(i);
+            i += 1;
+        }
+        v
+    };
+    pub const CR_BIT_BE_INDEXES: Self = {
+        let mut v = Self::splat_copied(None);
+        let bits = v.cr_bits_msb0_mut();
+        let mut i = 0;
+        while i < bits.len() {
+            *bits[i] = Some(i);
+            i += 1;
+        }
+        v
+    };
+}
+
+impl PRegFlagsPowerISAView<Option<SimValue<ConditionMode>>> {
+    pub fn cr_condition_modes_sim() -> Self {
+        PRegFlagsPowerISAView::cr_condition_modes().map(|v| v.map(ToSimValue::into_sim_value))
+    }
+}
+
+impl PRegFlagsPowerISAView<Option<Expr<ConditionMode>>> {
+    pub fn cr_condition_modes() -> Self {
+        Self {
+            unused: ViewUnused([]),
+            xer_ca: None,
+            xer_ca32: None,
+            xer_ov: None,
+            xer_ov32: None,
+            cr_lt: Some(ConditionMode.SLt()),
+            cr_gt: Some(ConditionMode.SGt()),
+            cr_eq: Some(ConditionMode.Eq()),
+            so: Some(ConditionMode.Overflow()),
+        }
+    }
+}
+
+impl<T> PRegFlagsPowerISAView<T> {
+    pub fn into_cr_bits_msb0(self) -> [T; 4] {
+        [self.cr_lt, self.cr_gt, self.cr_eq, self.so]
+    }
+    pub const fn cr_bits_msb0_ref(&self) -> [&T; 4] {
+        [&self.cr_lt, &self.cr_gt, &self.cr_eq, &self.so]
+    }
+    pub const fn cr_bits_msb0_mut(&mut self) -> [&mut T; 4] {
+        [
+            &mut self.cr_lt,
+            &mut self.cr_gt,
+            &mut self.cr_eq,
+            &mut self.so,
+        ]
+    }
+    pub fn into_cr_bits_lsb0(self) -> [T; 4] {
+        let mut retval = self.into_cr_bits_msb0();
+        retval.reverse();
+        retval
+    }
+    pub const fn cr_bits_lsb0_ref(&self) -> [&T; 4] {
+        let [b0, b1, b2, b3] = self.cr_bits_msb0_ref();
+        [b3, b2, b1, b0]
+    }
+    pub const fn cr_bits_lsb0_mut(&mut self) -> [&mut T; 4] {
+        let [b0, b1, b2, b3] = self.cr_bits_msb0_mut();
+        [b3, b2, b1, b0]
+    }
+}
+
+impl PRegFlagsPowerISA {
+    pub fn cr_condition_modes_msb0() -> [Expr<ConditionMode>; 4] {
+        PRegFlagsPowerISAView::cr_condition_modes()
+            .into_cr_bits_msb0()
+            .map(|v| v.expect("known to be Some"))
+    }
+    pub fn cr_condition_modes_lsb0() -> [Expr<ConditionMode>; 4] {
+        PRegFlagsPowerISAView::cr_condition_modes()
+            .into_cr_bits_lsb0()
+            .map(|v| v.expect("known to be Some"))
+    }
+    pub fn cr_condition_modes_msb0_sim() -> [SimValue<ConditionMode>; 4] {
+        PRegFlagsPowerISAView::cr_condition_modes_sim()
+            .into_cr_bits_msb0()
+            .map(|v| v.expect("known to be Some"))
+    }
+    pub fn cr_condition_modes_lsb0_sim() -> [SimValue<ConditionMode>; 4] {
+        PRegFlagsPowerISAView::cr_condition_modes_sim()
+            .into_cr_bits_lsb0()
+            .map(|v| v.expect("known to be Some"))
+    }
+}
+
+impl_view_trait! {
    #[hdl(cmp_eq)]
    pub struct PRegFlagsX86 {}

-impl PRegFlagsX86 {
-    pub fn cf(flags: impl ToExpr<Type = PRegFlags>) -> Expr<Bool> {
-        flags.to_expr().pwr_ca_x86_cf
-    }
-    pub fn zf(flags: impl ToExpr<Type = PRegFlags>) -> Expr<Bool> {
-        flags.to_expr().pwr_cr_eq_x86_zf
-    }
-    pub fn sf(flags: impl ToExpr<Type = PRegFlags>) -> Expr<Bool> {
-        flags.to_expr().pwr_cr_lt_x86_sf
-    }
-    pub fn of(flags: impl ToExpr<Type = PRegFlags>) -> Expr<Bool> {
-        flags.to_expr().pwr_ov_x86_of
-    }
-    pub fn af(flags: impl ToExpr<Type = PRegFlags>) -> Expr<Bool> {
-        flags.to_expr().pwr_ca32_x86_af
-    }
-    pub fn pf(flags: impl ToExpr<Type = PRegFlags>) -> Expr<Bool> {
-        flags.to_expr().pwr_cr_gt_x86_pf
-    }
-    pub fn df(flags: impl ToExpr<Type = PRegFlags>) -> Expr<Bool> {
-        flags.to_expr().pwr_ov32_x86_df
-    }
-    #[hdl]
-    pub fn clear_unused(flags: impl ToExpr<Type = PRegFlags>) {
-        // list all flags explicitly so we don't miss handling any new flags
-        #[hdl]
-        let PRegFlags {
-            pwr_ca_x86_cf: _,
-            pwr_ca32_x86_af: _,
-            pwr_ov_x86_of: _,
-            pwr_ov32_x86_df: _,
-            pwr_cr_lt_x86_sf: _,
-            pwr_cr_gt_x86_pf: _,
-            pwr_cr_eq_x86_zf: _,
-            pwr_so: unused1,
-        } = flags;
-        connect(unused1, false);
+    #[derive(Copy, Clone, Debug)]
+    #[non_exhaustive]
+    pub struct PRegFlagsX86View {
+        pub unused: ViewUnused([pwr_so]),
+        pub cf: pwr_ca_x86_cf,
+        pub zf: pwr_cr_eq_x86_zf,
+        pub sf: pwr_cr_lt_x86_sf,
+        pub of: pwr_ov_x86_of,
+        pub af: pwr_ca32_x86_af,
+        pub pf: pwr_cr_gt_x86_pf,
+        pub df: pwr_ov32_x86_df,
    }
 }

+macro_rules! impl_flags {
+    (
+        $(#[$struct_meta:meta])*
+        $struct_vis:vis struct $PRegFlags:ident<$T:ident: Type = Bool> {
+            $($field:ident: T,)*
+        }
+    ) => {
+        $(#[$struct_meta])*
+        $struct_vis struct $PRegFlags<$T: Type = Bool> {
+            $($field: $T,)*
+        }
+
+        struct Fields<$T> {
+            $($field: $T,)*
+        }
+
+        impl<$T> Fields<$T> {
+            fn from_view_unused(unused: ViewUnused<$T, PRegFlagsAllUnused>) -> Self {
+                let ViewUnused([
+                    $($field,)*
+                ]) = unused;
+                Self {
+                    $($field,)*
+                }
+            }
+            fn into_view_unused(self) -> ViewUnused<$T, PRegFlagsAllUnused> {
+                ViewUnused([
+                    $(self.$field,)*
+                ])
+            }
+        }
+
+        impl_view_trait! {
+            #[hdl(cmp_eq)]
+            pub struct PRegFlagsAllUnused {}
+
+            #[derive(Copy, Clone, Debug)]
+            #[non_exhaustive]
+            pub struct PRegFlagsAllUnusedView {
+                pub unused: ViewUnused([
+                    $($field,)*
+                ]),
+            }
+        }
+    };
+}
+
+impl_flags! {
    #[hdl(cmp_eq)]
    /// this is *not* the same as any particular ISA's flags register,
    /// on PowerISA it is a combination of some bits from XER with a single 4-bit CR field.
@ -105,34 +663,103 @@ impl PRegFlagsX86 {
    ///
    /// * PowerISA: [`struct@PRegFlagsPowerISA`]
    /// * x86: [`struct@PRegFlagsX86`]
-pub struct PRegFlags {
-    pwr_ca_x86_cf: Bool,
-    pwr_ca32_x86_af: Bool,
-    pwr_ov_x86_of: Bool,
-    pwr_ov32_x86_df: Bool,
-    pwr_cr_lt_x86_sf: Bool,
-    pwr_cr_gt_x86_pf: Bool,
-    pwr_cr_eq_x86_zf: Bool,
-    pwr_so: Bool,
+    pub struct PRegFlags<T: Type = Bool> {
+        pwr_ca32_x86_af: T,
+        pwr_ca_x86_cf: T,
+        pwr_ov32_x86_df: T,
+        pwr_ov_x86_of: T,
+        pwr_so: T,
+        pwr_cr_eq_x86_zf: T,
+        pwr_cr_gt_x86_pf: T,
+        pwr_cr_lt_x86_sf: T,
+    }
+}
+
+impl<T: Type> PRegFlags<T> {
+    pub const fn field_ty(self) -> T {
+        self.pwr_so
+    }
+    pub fn view<V: PRegFlagsViewTrait>(flags: impl ToExpr<Type = Self>) -> V::View<Expr<T>> {
+        V::view(flags)
+    }
+    pub fn view_sim<V: PRegFlagsViewTrait>(
+        flags: impl ToSimValue<Type = Self>,
+    ) -> V::View<SimValue<T>> {
+        V::view_sim(flags)
+    }
+    pub fn view_sim_ref<V: PRegFlagsViewTrait>(flags: &SimValue<Self>) -> V::View<&SimValue<T>> {
+        V::view_sim_ref(flags)
+    }
+    pub fn view_sim_mut<V: PRegFlagsViewTrait>(
+        flags: &mut SimValue<Self>,
+    ) -> V::View<&mut SimValue<T>> {
+        V::view_sim_mut(flags)
+    }
+    pub fn from_view<V: PRegFlagsViewTrait>(view: V::View<impl ToExpr<Type = T>>) -> Expr<Self> {
+        V::from_view(view)
+    }
+    pub fn from_view_sim<V: PRegFlagsViewTrait>(
+        view: V::View<impl ToSimValue<Type = T>>,
+    ) -> SimValue<Self> {
+        V::from_view_sim(view)
+    }
+    pub fn fields(flags: impl ToExpr<Type = Self>) -> ViewUnused<Expr<T>, PRegFlagsAllUnused> {
+        Self::view::<PRegFlagsAllUnused>(flags).unused
+    }
+    pub fn fields_sim(
+        flags: impl ToSimValue<Type = Self>,
+    ) -> ViewUnused<SimValue<T>, PRegFlagsAllUnused> {
+        Self::view_sim::<PRegFlagsAllUnused>(flags).unused
+    }
+    pub fn fields_sim_ref(flags: &SimValue<Self>) -> ViewUnused<&SimValue<T>, PRegFlagsAllUnused> {
+        Self::view_sim_ref::<PRegFlagsAllUnused>(flags).unused
+    }
+    pub fn fields_sim_mut(
+        flags: &mut SimValue<Self>,
+    ) -> ViewUnused<&mut SimValue<T>, PRegFlagsAllUnused> {
+        Self::view_sim_mut::<PRegFlagsAllUnused>(flags).unused
+    }
+    pub fn from_fields(
+        fields: ViewUnused<impl ToExpr<Type = T>, PRegFlagsAllUnused>,
+    ) -> Expr<Self> {
+        Self::from_view::<PRegFlagsAllUnused>(PRegFlagsAllUnusedView { unused: fields })
+    }
+    pub fn from_fields_sim(
+        fields: ViewUnused<impl ToSimValue<Type = T>, PRegFlagsAllUnused>,
+    ) -> SimValue<Self> {
+        Self::from_view_sim::<PRegFlagsAllUnused>(PRegFlagsAllUnusedView { unused: fields })
+    }
+    /// if trying to set all fields individually, prefer using the individual accessor
+    /// functions and [`PRegFlagsPowerISA::clear_unused()`]/[`PRegFlagsX86::clear_unused()`]/etc.
+    pub fn splat(v: impl ToExpr<Type = T>) -> Expr<Self> {
+        Self::from_fields(ViewUnused::splat(v.to_expr()))
+    }
+    /// if trying to set all fields individually, prefer using the individual accessor
+    /// functions and [`PRegFlagsPowerISA::clear_unused()`]/[`PRegFlagsX86::clear_unused()`]/etc.
+    pub fn splat_sim(v: impl ToSimValue<Type = T>) -> SimValue<Self> {
+        Self::from_fields_sim(ViewUnused::splat(v.into_sim_value()))
+    }
+}
+
+impl PRegFlags<UIntInRange<0, { PRegFlags::FLAG_COUNT }>> {
+    pub fn flag_indexes() -> SimValue<Self> {
+        let ty = <Self as StaticType>::TYPE.field_ty();
+        Self::from_fields_sim(ViewUnused::from_fn(|i| i.to_sim_value_with_type(ty)))
+    }
 }

 impl PRegFlags {
    /// if trying to set all fields individually, prefer using the individual accessor
    /// functions and [`PRegFlagsPowerISA::clear_unused()`]/[`PRegFlagsX86::clear_unused()`]/etc.
-    #[hdl]
    pub fn zeroed() -> Expr<PRegFlags> {
-        #[hdl]
-        PRegFlags {
-            pwr_ca_x86_cf: false,
-            pwr_ca32_x86_af: false,
-            pwr_ov_x86_of: false,
-            pwr_ov32_x86_df: false,
-            pwr_cr_lt_x86_sf: false,
-            pwr_cr_gt_x86_pf: false,
-            pwr_cr_eq_x86_zf: false,
-            pwr_so: false,
+        Self::splat(false)
    }
+    /// if trying to set all fields individually, prefer using the individual accessor
+    /// functions and [`PRegFlagsPowerISA::clear_unused()`]/[`PRegFlagsX86::clear_unused()`]/etc.
+    pub fn zeroed_sim() -> SimValue<PRegFlags> {
+        Self::splat_sim(false)
    }
+    pub const FLAG_COUNT: usize = PRegFlagsAllUnused::UNUSED_INNER_LEN;
 }

 #[hdl(cmp_eq)]
--- a/crates/cpu/src/unit.rs
+++ b/crates/cpu/src/unit.rs
@ -4,8 +4,9 @@
 use crate::{
    config::CpuConfig,
    instruction::{
-        AluBranchMOp, LoadStoreMOp, MOp, MOpDestReg, MOpInto, MOpRegNum, MOpTrait, RenamedMOp,
-        UnitOutRegNum, mop_enum,
+        AluBranchMOp, LoadStoreMOp, MOp, MOpDestReg, MOpInto, MOpRegNum, MOpTrait,
+        MOpVariantVisitOps, MOpVariantVisitor, MOpVisitVariants, RenamedMOp, UnitOutRegNum,
+        mop_enum,
    },
    register::{FlagsMode, PRegValue},
    unit::unit_base::UnitToRegAlloc,
@ -15,6 +16,8 @@ use fayalite::{
    intern::{Intern, Interned},
    prelude::*,
 };
+use serde::{Deserialize, Serialize};
+use std::ops::ControlFlow;

 pub mod alu_branch;
 pub mod unit_base;
@ -36,7 +39,7 @@ macro_rules! all_units {
        }
    ) => {
        $(#[$enum_meta])*
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Hash, Debug)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Hash, Debug, Serialize, Deserialize)]
        $vis enum $UnitKind {
            $(
                $(#[$variant_meta])*
@ -52,9 +55,16 @@ macro_rules! all_units {
            }
        }

-        impl ToExpr for $UnitKind {
+        impl ValueType for $UnitKind {
            type Type = $HdlUnitKind;
+            type ValueCategory = fayalite::expr::value_category::ValueCategoryExpr;

+            fn ty(&self) -> Self::Type {
+                $HdlUnitKind
+            }
+        }
+
+        impl ToExpr for $UnitKind {
            fn to_expr(&self) -> Expr<Self::Type> {
                match self {
                    $($UnitKind::$Unit => $HdlUnitKind.$Unit(),)*
@ -75,7 +85,15 @@ macro_rules! all_units {
            #[impl_mop_into = false]
            #[hdl]
            $(#[$enum_meta])*
-            $vis enum $UnitMOpEnum<$DestReg: Type, $SrcRegWidth: Size, #[MOp(get_ty = $transformed_move_op_get_ty)] $TransformedMoveOp: Type> {
+            $vis enum $UnitMOpEnum<
+                $DestReg: Type,
+                $SrcRegWidth: Size,
+                #[MOp(get_ty = $transformed_move_op_get_ty)] $TransformedMoveOp: Type,
+                #[MOpVisitVariants] [
+                    $TransformedMoveOp: MOpVisitVariants<DestReg = $DestReg, SrcRegWidth = $SrcRegWidth>,
+                    $($Op: MOpVisitVariants<DestReg = $DestReg, SrcRegWidth = $SrcRegWidth>,)*
+                ]
+            > {
                $(
                    $(#[$variant_meta])*
                    $Unit($Op),
@ -98,7 +116,7 @@ macro_rules! all_units {
                #[hdl]
                $vis fn $extract(expr: impl ToExpr<Type = Self>) -> Expr<HdlOption<$Op>> {
                    let expr = expr.to_expr();
-                    let ty = Expr::ty(expr);
+                    let ty = expr.ty();
                    #[hdl]
                    let $extract = wire(HdlOption[ty.$Unit]);
                    connect($extract, HdlOption[ty.$Unit].HdlNone());
@ -164,10 +182,10 @@ macro_rules! all_units {
                $TransformedMoveOp: MOpTrait<DestReg = $DestReg, SrcRegWidth = $SrcRegWidth>,
            {
                let this = this.to_expr();
-                let new_ty = Expr::ty(this).with_transformed_move_op_ty(new_transformed_move_op_ty);
+                let new_ty = this.ty().with_transformed_move_op_ty(new_transformed_move_op_ty);
                #[hdl]
                let with_transformed_move_op = wire(HdlOption[new_ty]);
-                connect(with_transformed_move_op, Expr::ty(with_transformed_move_op).HdlNone());
+                connect(with_transformed_move_op, with_transformed_move_op.ty().HdlNone());
                // workaround #[hdl] match expanding to a loop, so you can't move variables in it
                let mut connect_transformed_move_op = Some(connect_transformed_move_op);
                #[hdl]
@ -209,7 +227,7 @@ macro_rules! all_units {
                RenamedMOp[MOpTrait::dest_reg_ty(self)][MOpTrait::src_reg_width(self)]
            }
            fn mop_into(this: Expr<Self>) -> Expr<RenamedMOp<$DestReg, $SrcRegWidth>> {
-                MOpInto::<RenamedMOp<$DestReg, $SrcRegWidth>>::mop_into_ty(Expr::ty(this)).$BeforeUnit(this)
+                MOpInto::<RenamedMOp<$DestReg, $SrcRegWidth>>::mop_into_ty(this.ty()).$BeforeUnit(this)
            }
        })*

@ -218,7 +236,7 @@ macro_rules! all_units {
                RenamedMOp[MOpTrait::dest_reg_ty(self)][MOpTrait::src_reg_width(self)]
            }
            fn mop_into(this: Expr<Self>) -> Expr<RenamedMOp<$DestReg, $SrcRegWidth>> {
-                MOpInto::<RenamedMOp<$DestReg, $SrcRegWidth>>::mop_into_ty(Expr::ty(this)).$AfterUnit(this)
+                MOpInto::<RenamedMOp<$DestReg, $SrcRegWidth>>::mop_into_ty(this.ty()).$AfterUnit(this)
            }
        })*
    };
--- a/crates/cpu/src/unit/alu_branch.rs
+++ b/crates/cpu/src/unit/alu_branch.rs
@ -4,10 +4,14 @@
 use crate::{
    config::CpuConfig,
    instruction::{
-        AddSubMOp, AluBranchMOp, AluCommonMOp, COMMON_MOP_SRC_LEN, CommonMOp, LogicalMOp, MOpTrait,
-        OutputIntegerMode, RenamedMOp, UnitOutRegNum,
+        AddSubMOp, AluBranchMOp, AluCommonMOp, BranchMOp, COMMON_MOP_SRC_LEN, CommonMOpDefaultImm,
+        CompareMOp, LogicalFlagsMOp, LogicalMOp, MOpTrait, OutputIntegerMode, ReadSpecialMOp,
+        RenamedMOp, ShiftRotateMOp, UnitOutRegNum,
+    },
+    register::{
+        FlagsMode, PRegFlagsPowerISA, PRegFlagsPowerISAView, PRegFlagsViewTrait, PRegFlagsX86,
+        PRegFlagsX86View, PRegValue, ViewUnused,
    },
-    register::{FlagsMode, PRegFlagsPowerISA, PRegFlagsX86, PRegValue},
    unit::{
        DynUnit, DynUnitWrapper, GlobalState, UnitKind, UnitMOp, UnitOutput, UnitResult,
        UnitResultCompleted, UnitTrait,
@ -38,11 +42,11 @@ fn add_sub<SrcCount: KnownSize>(
        add_pc,
    } = mop;
    #[hdl]
-    let AluCommonMOp::<_, _, _> {
+    let AluCommonMOp::<_, _, _, _> {
        common,
        output_integer_mode,
    } = alu_common;
-    let imm: Expr<UInt<64>> = CommonMOp::imm(common).cast_to_static();
+    let imm = CommonMOpDefaultImm::as_sint_dyn(common.imm).cast_to_static::<UInt<64>>();
    #[hdl]
    let carry_in_before_inversion = wire();
    connect(carry_in_before_inversion, false);
@ -56,13 +60,13 @@ fn add_sub<SrcCount: KnownSize>(
            FlagsMode::PowerISA(_) => {
                connect(
                    carry_in_before_inversion,
-                    PRegFlagsPowerISA::xer_ca(src_values[1].flags),
+                    PRegFlagsPowerISA::view(src_values[1].flags).xer_ca,
                );
            }
            FlagsMode::X86(_) => {
                connect(
                    carry_in_before_inversion,
-                    PRegFlagsX86::cf(src_values[1].flags),
+                    PRegFlagsX86::view(src_values[1].flags).cf,
                );
            }
        }
@ -199,27 +203,36 @@ fn add_sub<SrcCount: KnownSize>(
    #[hdl]
    match flags_mode {
        FlagsMode::PowerISA(_) => {
-            PRegFlagsPowerISA::clear_unused(flags);
-            connect(PRegFlagsPowerISA::xer_ca(flags), pwr_ca);
-            connect(PRegFlagsPowerISA::xer_ca32(flags), pwr_ca32);
-            connect(PRegFlagsPowerISA::xer_ov(flags), pwr_ov);
-            connect(PRegFlagsPowerISA::xer_ov32(flags), pwr_ov32);
-            connect(PRegFlagsPowerISA::cr_lt(flags), pwr_cr_lt);
-            connect(PRegFlagsPowerISA::cr_gt(flags), pwr_cr_gt);
-            connect(PRegFlagsPowerISA::cr_eq(flags), pwr_cr_eq);
-            connect(PRegFlagsPowerISA::so(flags), pwr_so);
+            connect(
+                flags,
+                PRegFlagsPowerISA::from_view(PRegFlagsPowerISAView {
+                    unused: ViewUnused::splat(false.to_expr()),
+                    xer_ca: pwr_ca,
+                    xer_ca32: pwr_ca32,
+                    xer_ov: pwr_ov,
+                    xer_ov32: pwr_ov32,
+                    so: pwr_so,
+                    cr_lt: pwr_cr_lt,
+                    cr_gt: pwr_cr_gt,
+                    cr_eq: pwr_cr_eq,
+                }),
+            );
        }
        FlagsMode::X86(_) => {
-            PRegFlagsX86::clear_unused(flags);
-            connect(PRegFlagsX86::cf(flags), x86_cf);
-            connect(PRegFlagsX86::af(flags), x86_af);
-            connect(PRegFlagsX86::of(flags), x86_of);
-            connect(PRegFlagsX86::sf(flags), x86_sf);
-            connect(PRegFlagsX86::pf(flags), x86_pf);
-            connect(PRegFlagsX86::zf(flags), x86_zf);
-
+            connect(
+                flags,
+                PRegFlagsX86::from_view(PRegFlagsX86View {
+                    unused: ViewUnused::splat(false.to_expr()),
+                    cf: x86_cf,
+                    zf: x86_zf,
+                    sf: x86_sf,
+                    of: x86_of,
+                    af: x86_af,
+                    pf: x86_pf,
                    // this insn doesn't write DF, so it's output isn't used for reading DF
-            connect(PRegFlagsX86::df(flags), false);
+                    df: false.to_expr(),
+                }),
+            );
        }
    }
    #[hdl]
@ -230,9 +243,95 @@ fn add_sub<SrcCount: KnownSize>(
    }
 }

+#[hdl]
+fn logical_flags(
+    mop: Expr<LogicalFlagsMOp<UnitOutRegNum<DynSize>, DynSize>>,
+    flags_mode: Expr<FlagsMode>,
+    src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>,
+) -> Expr<UnitResultCompleted<()>> {
+    // TODO: finish
+    #[hdl]
+    UnitResultCompleted::<_> {
+        value: PRegValue::zeroed(),
+        extra_out: (),
+    }
+}
+
 #[hdl]
 fn logical(
-    mop: Expr<LogicalMOp<UnitOutRegNum<DynSize>, DynSize>>,
+    mop: Expr<LogicalMOp<UnitOutRegNum<DynSize>, DynSize, ConstUsize<2>>>,
+    flags_mode: Expr<FlagsMode>,
+    src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>,
+) -> Expr<UnitResultCompleted<()>> {
+    // TODO: finish
+    #[hdl]
+    UnitResultCompleted::<_> {
+        value: PRegValue::zeroed(),
+        extra_out: (),
+    }
+}
+
+#[hdl]
+fn logical_i(
+    mop: Expr<LogicalMOp<UnitOutRegNum<DynSize>, DynSize, ConstUsize<1>>>,
+    flags_mode: Expr<FlagsMode>,
+    src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>,
+) -> Expr<UnitResultCompleted<()>> {
+    // TODO: finish
+    #[hdl]
+    UnitResultCompleted::<_> {
+        value: PRegValue::zeroed(),
+        extra_out: (),
+    }
+}
+
+#[hdl]
+fn shift_rotate(
+    mop: Expr<ShiftRotateMOp<UnitOutRegNum<DynSize>, DynSize>>,
+    flags_mode: Expr<FlagsMode>,
+    src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>,
+) -> Expr<UnitResultCompleted<()>> {
+    // TODO: finish
+    #[hdl]
+    UnitResultCompleted::<_> {
+        value: PRegValue::zeroed(),
+        extra_out: (),
+    }
+}
+
+#[hdl]
+fn compare<SrcCount: KnownSize>(
+    mop: Expr<CompareMOp<UnitOutRegNum<DynSize>, DynSize, SrcCount>>,
+    flags_mode: Expr<FlagsMode>,
+    src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>,
+) -> Expr<UnitResultCompleted<()>> {
+    // TODO: finish
+    #[hdl]
+    UnitResultCompleted::<_> {
+        value: PRegValue::zeroed(),
+        extra_out: (),
+    }
+}
+
+#[hdl]
+fn branch<SrcCount: KnownSize>(
+    mop: Expr<BranchMOp<UnitOutRegNum<DynSize>, DynSize, SrcCount>>,
+    pc: Expr<UInt<64>>,
+    flags_mode: Expr<FlagsMode>,
+    src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>,
+) -> Expr<UnitResultCompleted<()>> {
+    // TODO: finish
+    #[hdl]
+    UnitResultCompleted::<_> {
+        value: PRegValue::zeroed(),
+        extra_out: (),
+    }
+}
+
+#[hdl]
+fn read_special(
+    mop: Expr<ReadSpecialMOp<UnitOutRegNum<DynSize>, DynSize>>,
+    pc: Expr<UInt<64>>,
    flags_mode: Expr<FlagsMode>,
    src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>,
 ) -> Expr<UnitResultCompleted<()>> {
@ -266,16 +365,13 @@ pub fn alu_branch(config: &CpuConfig, unit_index: usize) {
    let unit_base = instance(unit_base(
        config,
        unit_index,
-        Expr::ty(unit_to_reg_alloc).input.data.HdlSome.mop,
+        unit_to_reg_alloc.ty().input.data.HdlSome.mop,
        (),
    ));
    connect(unit_to_reg_alloc, unit_base.unit_to_reg_alloc);
    connect(unit_base.cd, cd);
    connect(unit_base.execute_start.ready, true);
-    connect(
-        unit_base.execute_end,
-        Expr::ty(unit_base.execute_end).HdlNone(),
-    );
+    connect(unit_base.execute_end, unit_base.execute_end.ty().HdlNone());
    #[hdl]
    if let HdlSome(execute_start) = ReadyValid::firing_data(unit_base.execute_start) {
        #[hdl]
@ -322,6 +418,23 @@ pub fn alu_branch(config: &CpuConfig, unit_index: usize) {
                    },
                ),
            ),
+            AluBranchMOp::<_, _>::LogicalFlags(mop) => connect(
+                unit_base.execute_end,
+                HdlSome(
+                    #[hdl]
+                    ExecuteEnd::<_, _> {
+                        unit_output: #[hdl]
+                        UnitOutput::<_, _> {
+                            which: MOpTrait::dest_reg(mop),
+                            result: UnitResult[()].Completed(logical_flags(
+                                mop,
+                                global_state.flags_mode,
+                                src_values,
+                            )),
+                        },
+                    },
+                ),
+            ),
            AluBranchMOp::<_, _>::Logical(mop) => connect(
                unit_base.execute_end,
                HdlSome(
@ -339,6 +452,128 @@ pub fn alu_branch(config: &CpuConfig, unit_index: usize) {
                    },
                ),
            ),
+            AluBranchMOp::<_, _>::LogicalI(mop) => connect(
+                unit_base.execute_end,
+                HdlSome(
+                    #[hdl]
+                    ExecuteEnd::<_, _> {
+                        unit_output: #[hdl]
+                        UnitOutput::<_, _> {
+                            which: MOpTrait::dest_reg(mop),
+                            result: UnitResult[()].Completed(logical_i(
+                                mop,
+                                global_state.flags_mode,
+                                src_values,
+                            )),
+                        },
+                    },
+                ),
+            ),
+            AluBranchMOp::<_, _>::ShiftRotate(mop) => connect(
+                unit_base.execute_end,
+                HdlSome(
+                    #[hdl]
+                    ExecuteEnd::<_, _> {
+                        unit_output: #[hdl]
+                        UnitOutput::<_, _> {
+                            which: MOpTrait::dest_reg(mop),
+                            result: UnitResult[()].Completed(shift_rotate(
+                                mop,
+                                global_state.flags_mode,
+                                src_values,
+                            )),
+                        },
+                    },
+                ),
+            ),
+            AluBranchMOp::<_, _>::Compare(mop) => connect(
+                unit_base.execute_end,
+                HdlSome(
+                    #[hdl]
+                    ExecuteEnd::<_, _> {
+                        unit_output: #[hdl]
+                        UnitOutput::<_, _> {
+                            which: MOpTrait::dest_reg(mop),
+                            result: UnitResult[()].Completed(compare(
+                                mop,
+                                global_state.flags_mode,
+                                src_values,
+                            )),
+                        },
+                    },
+                ),
+            ),
+            AluBranchMOp::<_, _>::CompareI(mop) => connect(
+                unit_base.execute_end,
+                HdlSome(
+                    #[hdl]
+                    ExecuteEnd::<_, _> {
+                        unit_output: #[hdl]
+                        UnitOutput::<_, _> {
+                            which: MOpTrait::dest_reg(mop),
+                            result: UnitResult[()].Completed(compare(
+                                mop,
+                                global_state.flags_mode,
+                                src_values,
+                            )),
+                        },
+                    },
+                ),
+            ),
+            AluBranchMOp::<_, _>::Branch(mop) => connect(
+                unit_base.execute_end,
+                HdlSome(
+                    #[hdl]
+                    ExecuteEnd::<_, _> {
+                        unit_output: #[hdl]
+                        UnitOutput::<_, _> {
+                            which: MOpTrait::dest_reg(mop),
+                            result: UnitResult[()].Completed(branch(
+                                mop,
+                                pc,
+                                global_state.flags_mode,
+                                src_values,
+                            )),
+                        },
+                    },
+                ),
+            ),
+            AluBranchMOp::<_, _>::BranchI(mop) => connect(
+                unit_base.execute_end,
+                HdlSome(
+                    #[hdl]
+                    ExecuteEnd::<_, _> {
+                        unit_output: #[hdl]
+                        UnitOutput::<_, _> {
+                            which: MOpTrait::dest_reg(mop),
+                            result: UnitResult[()].Completed(branch(
+                                mop,
+                                pc,
+                                global_state.flags_mode,
+                                src_values,
+                            )),
+                        },
+                    },
+                ),
+            ),
+            AluBranchMOp::<_, _>::ReadSpecial(mop) => connect(
+                unit_base.execute_end,
+                HdlSome(
+                    #[hdl]
+                    ExecuteEnd::<_, _> {
+                        unit_output: #[hdl]
+                        UnitOutput::<_, _> {
+                            which: MOpTrait::dest_reg(mop),
+                            result: UnitResult[()].Completed(read_special(
+                                mop,
+                                pc,
+                                global_state.flags_mode,
+                                src_values,
+                            )),
+                        },
+                    },
+                ),
+            ),
        }
    }
 }
--- a/crates/cpu/src/unit/unit_base.rs
+++ b/crates/cpu/src/unit/unit_base.rs
@ -227,7 +227,7 @@ impl InFlightOpsSummary<DynSize> {
        in_flight_ops: impl ToExpr<Type = ArrayType<HdlOption<InFlightOp<MOp>>, MaxInFlight>>,
    ) -> Expr<Self> {
        let in_flight_ops = in_flight_ops.to_expr();
-        let max_in_flight = Expr::ty(in_flight_ops).len();
+        let max_in_flight = in_flight_ops.ty().len();
        let index_range = 0..max_in_flight;
        let index_ty = UInt::range(index_range.clone());
        tree_reduce(
@ -259,7 +259,7 @@ pub fn unit_base<
    let execute_end: HdlOption<ExecuteEnd<DynSize, ExtraOut>> =
        m.input(HdlOption[ExecuteEnd[config.out_reg_num_width][extra_out_ty]]);

-    connect(execute_start.data, Expr::ty(execute_start).data.HdlNone());
+    connect(execute_start.data, execute_start.ty().data.HdlNone());

    let max_in_flight = config.unit_max_in_flight(unit_index).get();
    let in_flight_op_ty = InFlightOp[mop_ty];
@ -270,7 +270,7 @@ pub fn unit_base<

    let in_flight_ops_summary_value = InFlightOpsSummary::summarize(in_flight_ops);
    #[hdl]
-    let in_flight_ops_summary = wire(Expr::ty(in_flight_ops_summary_value));
+    let in_flight_ops_summary = wire(in_flight_ops_summary_value.ty());
    connect(in_flight_ops_summary, in_flight_ops_summary_value);

    connect(
@ -302,7 +302,7 @@ pub fn unit_base<
    #[hdl]
    let input_src_regs_valid = wire();
    connect(input_src_regs_valid, [true; COMMON_MOP_SRC_LEN]);
-    let mut unit_output_regs_valid: Vec<MemBuilder<Bool>> = (0..Expr::ty(unit_output_writes).len())
+    let mut unit_output_regs_valid: Vec<MemBuilder<Bool>> = (0..unit_output_writes.ty().len())
        .map(|unit_index| {
            let mut mem = memory_with_loc(
                &format!("unit_{unit_index}_output_regs_valid"),
@ -313,7 +313,7 @@ pub fn unit_base<
            mem
        })
        .collect();
-    for unit_index in 0..Expr::ty(unit_output_writes).len() {
+    for unit_index in 0..unit_output_writes.ty().len() {
        let mut unit_output_regs = memory_with_loc(
            &format!("unit_{unit_index}_output_regs"),
            PRegValue,
@ -411,7 +411,7 @@ pub fn unit_base<

    connect(
        unit_to_reg_alloc.output,
-        Expr::ty(unit_to_reg_alloc.output).HdlNone(),
+        unit_to_reg_alloc.output.ty().HdlNone(),
    );

    #[hdl]
@ -503,7 +503,7 @@ pub fn unit_base<

            #[hdl]
            if in_flight_ops_summary.ready_op_index.cmp_eq(HdlSome(
-                in_flight_op_index.cast_to(Expr::ty(in_flight_ops_summary).ready_op_index.HdlSome),
+                in_flight_op_index.cast_to(in_flight_ops_summary.ty().ready_op_index.HdlSome),
            )) {
                connect(read_src_regs, src_regs);
            }
@ -512,7 +512,7 @@ pub fn unit_base<
                in_flight_op_next_src_ready_flags[in_flight_op_index],
                src_ready_flags,
            );
-            for unit_index in 0..Expr::ty(unit_output_writes).len() {
+            for unit_index in 0..unit_output_writes.ty().len() {
                #[hdl]
                if let HdlSome(unit_output_write) = unit_output_writes[unit_index] {
                    #[hdl]
--- a/crates/cpu/src/util.rs
+++ b/crates/cpu/src/util.rs
@ -1,6 +1,9 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information

+use fayalite::{expr::ops::ArrayLiteral, module::wire_with_loc, prelude::*};
+use std::num::NonZero;
+
 pub mod array_vec;
 pub mod tree_reduce;

@ -25,3 +28,255 @@ pub(crate) const fn range_u32_nth_or_panic(range: &std::ops::Range<u32>, index:
        panic!("index out of range")
    }
 }
+
+// TODO: move to fayalite
+pub trait Rotate<Amount> {
+    type Output;
+    /// like [`usize::rotate_left`] or [`<[T]>::rotate_left`](slice::rotate_left) depending on `Self` -- note that in lsb0 those rotate in opposite directions
+    fn rotate_left(&self, amount: Amount) -> Self::Output;
+    /// like [`usize::rotate_right`] or [`<[T]>::rotate_right`](slice::rotate_right) depending on `Self` -- note that in lsb0 those rotate in opposite directions
+    fn rotate_right(&self, amount: Amount) -> Self::Output;
+}
+
+impl<VSz: Size> Rotate<usize> for Expr<UIntType<VSz>> {
+    type Output = Self;
+    /// like [`usize::rotate_left`]
+    fn rotate_left(&self, amount: usize) -> Self::Output {
+        if self.ty().width() == 0 {
+            return *self;
+        }
+        let amount = amount % self.ty().width();
+        let l = *self << amount;
+        let r = *self >> (self.ty().width() - amount);
+        (l | r).cast_to(self.ty())
+    }
+    /// like [`usize::rotate_right`]
+    fn rotate_right(&self, amount: usize) -> Self::Output {
+        if self.ty().width() == 0 {
+            return *self;
+        }
+        let amount = amount % self.ty().width();
+        let l = *self << (self.ty().width() - amount);
+        let r = *self >> amount;
+        (l | r).cast_to(self.ty())
+    }
+}
+
+impl<VSz: Size> Rotate<usize> for SimValue<UIntType<VSz>> {
+    type Output = Self;
+    /// like [`usize::rotate_left`]
+    fn rotate_left(&self, amount: usize) -> Self::Output {
+        if self.ty().width() == 0 {
+            return self.clone();
+        }
+        let amount = amount % self.ty().width();
+        let l = self << amount;
+        let r = self >> (self.ty().width() - amount);
+        (l | r).cast_to(self.ty())
+    }
+    /// like [`usize::rotate_right`]
+    fn rotate_right(&self, amount: usize) -> Self::Output {
+        if self.ty().width() == 0 {
+            return self.clone();
+        }
+        let amount = amount % self.ty().width();
+        let l = self << (self.ty().width() - amount);
+        let r = self >> amount;
+        (l | r).cast_to(self.ty())
+    }
+}
+
+impl<VSz: Size, ASz: Size> Rotate<Expr<UIntType<ASz>>> for Expr<UIntType<VSz>> {
+    type Output = Self;
+    /// like [`usize::rotate_left`]
+    fn rotate_left(&self, amount: Expr<UIntType<ASz>>) -> Self::Output {
+        if self.ty().width() == 0 {
+            return *self;
+        }
+        let amount = amount % self.ty().width();
+        let l = *self << amount;
+        let r = *self >> (self.ty().width() - amount);
+        (l | r).cast_to(self.ty())
+    }
+    /// like [`usize::rotate_right`]
+    fn rotate_right(&self, amount: Expr<UIntType<ASz>>) -> Self::Output {
+        if self.ty().width() == 0 {
+            return *self;
+        }
+        let amount = amount % self.ty().width();
+        let l = *self << (self.ty().width() - amount).cast_to(amount.ty());
+        let r = *self >> amount;
+        (l | r).cast_to(self.ty())
+    }
+}
+
+impl<VSz: Size, ASz: Size> Rotate<SimValue<UIntType<ASz>>> for SimValue<UIntType<VSz>> {
+    type Output = Self;
+    /// like [`usize::rotate_left`]
+    fn rotate_left(&self, amount: SimValue<UIntType<ASz>>) -> Self::Output {
+        if self.ty().width() == 0 {
+            return self.clone();
+        }
+        let amount = amount % self.ty().width();
+        let l = self << &amount;
+        let r = self >> (self.ty().width() - amount);
+        (l | r).cast_to(self.ty())
+    }
+    /// like [`usize::rotate_right`]
+    fn rotate_right(&self, amount: SimValue<UIntType<ASz>>) -> Self::Output {
+        if self.ty().width() == 0 {
+            return self.clone();
+        }
+        let amount = amount % self.ty().width();
+        let l = self << (self.ty().width() - &amount).cast_to(amount.ty());
+        let r = self >> amount;
+        (l | r).cast_to(self.ty())
+    }
+}
+
+fn array_rotate_helper<T: Type, N: Size, AmountSize: Size>(
+    mut array: Expr<ArrayType<T, N>>,
+    amount: Expr<UIntType<AmountSize>>,
+    rotate_fn: impl Fn(&mut [Expr<T>], usize),
+    rotate_fn_name: &str,
+) -> Expr<ArrayType<T, N>> {
+    let Some(mut prev_step_size) = NonZero::new(array.ty().len()) else {
+        return array;
+    };
+    fn named<T: Type>(v: Expr<T>, name: impl AsRef<str>) -> Expr<T> {
+        let w = wire_with_loc(name.as_ref(), SourceLocation::caller(), v.ty());
+        connect(w, v);
+        w
+    }
+    fn non_empty_array_to_expr<T: Type, Len: Size>(
+        v: impl AsRef<[Expr<T>]>,
+    ) -> Expr<ArrayType<T, Len>> {
+        let v = v.as_ref();
+        ArrayLiteral::new(v[0].ty(), v.iter().map(|v| Expr::canonical(*v)).collect()).to_expr()
+    }
+    fn mux<T: Type>(b: Expr<Bool>, true_v: Expr<T>, false_v: Expr<T>) -> Expr<T> {
+        let a: Expr<Array<T, 2>> = non_empty_array_to_expr([false_v, true_v]);
+        a[b.cast_to_static::<UInt<1>>()]
+    }
+    let amount_ty = amount.ty();
+    let mut amount = (amount % prev_step_size).cast_to(amount_ty);
+    loop {
+        (prev_step_size, amount, array) =
+            if let Some(step_size) = NonZero::new(prev_step_size.get() / 2) {
+                let amount = named(amount, format!("{rotate_fn_name}_amount_{prev_step_size}"));
+                let do_rotate = amount.cmp_ge(step_size);
+                let mut rotated_array = (*array).clone();
+                rotate_fn(rotated_array.as_mut(), step_size.get());
+                let rotated_array = named(
+                    non_empty_array_to_expr(rotated_array),
+                    format!("{rotate_fn_name}_rotated_array_{step_size}"),
+                );
+                let array = mux(do_rotate, rotated_array, array);
+                let array = named(array, format!("{rotate_fn_name}_array_{step_size}"));
+                let amount = mux(do_rotate, (amount - step_size).cast_to(amount_ty), amount);
+                (step_size, amount, array)
+            } else {
+                return array;
+            };
+    }
+}
+
+impl<T: Type, N: Size, AmountSize: Size> Rotate<Expr<UIntType<AmountSize>>>
+    for Expr<ArrayType<T, N>>
+{
+    type Output = Self;
+    /// like [`<[T]>::rotate_left`](slice::rotate_left)
+    fn rotate_left(&self, amount: Expr<UIntType<AmountSize>>) -> Self::Output {
+        array_rotate_helper(*self, amount, <[Expr<T>]>::rotate_left, "rotate_left")
+    }
+    /// like [`<[T]>::rotate_right`](slice::rotate_right)
+    fn rotate_right(&self, amount: Expr<UIntType<AmountSize>>) -> Self::Output {
+        array_rotate_helper(*self, amount, <[Expr<T>]>::rotate_right, "rotate_right")
+    }
+}
+
+impl<T: Type, N: Size, AmountSize: Size> Rotate<SimValue<UIntType<AmountSize>>>
+    for SimValue<ArrayType<T, N>>
+{
+    type Output = Self;
+    /// like [`<[T]>::rotate_left`](slice::rotate_left)
+    fn rotate_left(&self, amount: SimValue<UIntType<AmountSize>>) -> Self::Output {
+        if self.ty().len() == 0 {
+            return self.clone();
+        }
+        let Ok(amount) = usize::try_from(amount.to_bigint() % self.ty().len()) else {
+            unreachable!();
+        };
+        let mut retval = self.clone();
+        AsMut::<[SimValue<T>]>::as_mut(&mut SimValue::value_mut(&mut retval)).rotate_left(amount);
+        retval
+    }
+    /// like [`<[T]>::rotate_right`](slice::rotate_right)
+    fn rotate_right(&self, amount: SimValue<UIntType<AmountSize>>) -> Self::Output {
+        if self.ty().len() == 0 {
+            return self.clone();
+        }
+        let Ok(amount) = usize::try_from(amount.to_bigint() % self.ty().len()) else {
+            unreachable!();
+        };
+        let mut retval = self.clone();
+        AsMut::<[SimValue<T>]>::as_mut(&mut SimValue::value_mut(&mut retval)).rotate_right(amount);
+        retval
+    }
+}
+
+impl<T: Type, N: Size> Rotate<usize> for Expr<ArrayType<T, N>> {
+    type Output = Self;
+    /// like [`<[T]>::rotate_left`](slice::rotate_left)
+    fn rotate_left(&self, amount: usize) -> Self::Output {
+        if self.ty().len() == 0 {
+            return self.clone();
+        }
+        let amount = amount % self.ty().len();
+        let mut retval = Vec::from_iter(*self);
+        retval.rotate_left(amount);
+        ArrayLiteral::new(
+            self.ty().element(),
+            retval.into_iter().map(Expr::canonical).collect(),
+        )
+        .to_expr()
+    }
+    /// like [`<[T]>::rotate_right`](slice::rotate_right)
+    fn rotate_right(&self, amount: usize) -> Self::Output {
+        if self.ty().len() == 0 {
+            return self.clone();
+        }
+        let amount = amount % self.ty().len();
+        let mut retval = Vec::from_iter(*self);
+        retval.rotate_right(amount);
+        ArrayLiteral::new(
+            self.ty().element(),
+            retval.into_iter().map(Expr::canonical).collect(),
+        )
+        .to_expr()
+    }
+}
+
+impl<T: Type, N: Size> Rotate<usize> for SimValue<ArrayType<T, N>> {
+    type Output = Self;
+    /// like [`<[T]>::rotate_left`](slice::rotate_left)
+    fn rotate_left(&self, amount: usize) -> Self::Output {
+        if self.ty().len() == 0 {
+            return self.clone();
+        }
+        let amount = amount % self.ty().len();
+        let mut retval = self.clone();
+        AsMut::<[SimValue<T>]>::as_mut(&mut SimValue::value_mut(&mut retval)).rotate_left(amount);
+        retval
+    }
+    /// like [`<[T]>::rotate_right`](slice::rotate_right)
+    fn rotate_right(&self, amount: usize) -> Self::Output {
+        if self.ty().len() == 0 {
+            return self.clone();
+        }
+        let amount = amount % self.ty().len();
+        let mut retval = self.clone();
+        AsMut::<[SimValue<T>]>::as_mut(&mut SimValue::value_mut(&mut retval)).rotate_right(amount);
+        retval
+    }
+}
--- a/crates/cpu/src/util/array_vec.rs
+++ b/crates/cpu/src/util/array_vec.rs
@ -1,147 +1,28 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information

-use fayalite::{
-    expr::ops::{ExprCastTo, ExprIndex, ExprPartialEq, ExprPartialOrd},
-    int::SizeType,
-    intern::{Intern, Interned},
-    prelude::*,
-    ty::{MatchVariantWithoutScope, StaticType, TypeProperties},
-};
-use std::{marker::PhantomData, ops::Index};
+use fayalite::{expr::ops::ExprIndex, int::UIntInRangeInclusiveType, prelude::*};
+use std::fmt;

-#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
-pub struct Length<Max: Size> {
-    ty: UInt,
-    _phantom: PhantomData<Max>,
+#[derive(Clone, Debug)]
+pub struct ArrayVecFullError<V, I: Iterator> {
+    pub value: V,
+    pub rest: std::iter::Chain<std::iter::Once<I::Item>, I>,
 }

-impl<Max: Size> Length<Max> {
-    pub fn new(max: Max::SizeType) -> Self {
-        Self {
-            ty: UInt::range_inclusive(0..=Max::as_usize(max)),
-            _phantom: PhantomData,
-        }
-    }
-    pub fn ty(self) -> UInt {
-        self.ty
-    }
-    pub fn zero(self) -> Expr<Self> {
-        Self::from_uint_unchecked(self.ty.zero())
-    }
-    pub fn from_uint_unchecked(v: impl ToExpr<Type = UInt>) -> Expr<Self> {
-        Expr::from_canonical(Expr::canonical(v.to_expr()))
-    }
-    pub fn cast_from_uint_unchecked<SrcWidth: Size>(
-        self,
-        v: impl ToExpr<Type = UIntType<SrcWidth>>,
-    ) -> Expr<Self> {
-        Self::from_uint_unchecked(v.to_expr().cast_to(self.ty))
-    }
-    pub fn as_uint(this: impl ToExpr<Type = Self>) -> Expr<UInt> {
-        let this = this.to_expr();
-        this.cast_to(Expr::ty(this).ty)
+impl<V, I: Iterator> fmt::Display for ArrayVecFullError<V, I> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        write!(f, "ArrayVec is full")
    }
 }

-impl<Max: Size, DestWidth: Size> ExprCastTo<UIntType<DestWidth>> for Length<Max> {
-    fn cast_to(src: Expr<Self>, to_type: UIntType<DestWidth>) -> Expr<UIntType<DestWidth>> {
-        Expr::<UInt>::from_canonical(Expr::canonical(src)).cast_to(to_type)
-    }
+impl<V: fmt::Debug, I: Iterator<Item: fmt::Debug> + fmt::Debug> std::error::Error
+    for ArrayVecFullError<V, I>
+{
 }

-#[allow(non_upper_case_globals)]
-pub const Length: __LengthWithoutGenerics = __LengthWithoutGenerics {};
-
-#[non_exhaustive]
-pub struct __LengthWithoutGenerics {}
-
-impl<M: SizeType> Index<M> for __LengthWithoutGenerics {
-    type Output = Length<M::Size>;
-
-    fn index(&self, max: M) -> &Self::Output {
-        Interned::into_inner(Length::new(max).intern_sized())
-    }
-}
-
-impl<Max: Size> Type for Length<Max> {
-    type BaseType = UInt;
-    type MaskType = Bool;
-    type MatchVariant = Expr<Self>;
-    type MatchActiveScope = ();
-    type MatchVariantAndInactiveScope = MatchVariantWithoutScope<Self::MatchVariant>;
-    type MatchVariantsIter = std::iter::Once<Self::MatchVariantAndInactiveScope>;
-    fn match_variants(
-        this: Expr<Self>,
-        source_location: SourceLocation,
-    ) -> Self::MatchVariantsIter {
-        let _ = source_location;
-        std::iter::once(MatchVariantWithoutScope(this))
-    }
-
-    fn mask_type(&self) -> Self::MaskType {
-        Bool
-    }
-
-    fn canonical(&self) -> CanonicalType {
-        self.ty.canonical()
-    }
-
-    fn from_canonical(canonical_type: CanonicalType) -> Self {
-        let ty = <UInt>::from_canonical(canonical_type);
-        if let Some(known_max) = Max::KNOWN_VALUE {
-            assert_eq!(ty, UInt::range_inclusive(0..=known_max));
-        }
-        Self {
-            ty,
-            _phantom: PhantomData,
-        }
-    }
-
-    fn source_location() -> SourceLocation {
-        SourceLocation::caller()
-    }
-}
-
-impl<Max: KnownSize> StaticType for Length<Max> {
-    const TYPE: Self = Self {
-        ty: UInt {
-            width: Max::VALUE.next_power_of_two().ilog2() as usize,
-        },
-        _phantom: PhantomData,
-    };
-    const MASK_TYPE: Self::MaskType = Bool;
-    const TYPE_PROPERTIES: TypeProperties = {
-        let mut p = <UInt<1>>::TYPE_PROPERTIES;
-        p.bit_width = Self::TYPE.ty.width;
-        p
-    };
-    const MASK_TYPE_PROPERTIES: TypeProperties = Bool::TYPE_PROPERTIES;
-}
-
-impl<Max: Size> ExprPartialEq<Self> for Length<Max> {
-    fn cmp_eq(lhs: Expr<Self>, rhs: Expr<Self>) -> Expr<Bool> {
-        Self::as_uint(lhs).cmp_eq(Self::as_uint(rhs))
-    }
-    fn cmp_ne(lhs: Expr<Self>, rhs: Expr<Self>) -> Expr<Bool> {
-        Self::as_uint(lhs).cmp_ne(Self::as_uint(rhs))
-    }
-}
-
-impl<Max: Size> ExprPartialOrd<Self> for Length<Max> {
-    fn cmp_lt(lhs: Expr<Self>, rhs: Expr<Self>) -> Expr<Bool> {
-        Self::as_uint(lhs).cmp_lt(Self::as_uint(rhs))
-    }
-    fn cmp_le(lhs: Expr<Self>, rhs: Expr<Self>) -> Expr<Bool> {
-        Self::as_uint(lhs).cmp_le(Self::as_uint(rhs))
-    }
-    fn cmp_gt(lhs: Expr<Self>, rhs: Expr<Self>) -> Expr<Bool> {
-        Self::as_uint(lhs).cmp_gt(Self::as_uint(rhs))
-    }
-    fn cmp_ge(lhs: Expr<Self>, rhs: Expr<Self>) -> Expr<Bool> {
-        Self::as_uint(lhs).cmp_ge(Self::as_uint(rhs))
-    }
-}
+#[hdl]
+pub type Length<Max: Size> = UIntInRangeInclusiveType<ConstUsize<0>, Max>;

 /// like [`std::vec::Vec`], except with a [`Expr`] for [`len()`][`Self::len()`] and a fixed capacity
 #[hdl]
@ -156,7 +37,55 @@ impl<T: Type, N: Size> ArrayVec<T, N> {
        #[hdl]
        ArrayVec {
            elements: self.elements.uninit(),
-            len: self.len.zero(),
+            len: 0u8.cast_to(self.len),
+        }
+    }
+    #[hdl]
+    pub fn new_sim(self, uninit_element: impl ToSimValueWithType<T>) -> SimValue<Self> {
+        let uninit_element = uninit_element.into_sim_value_with_type(self.element());
+        #[hdl(sim)]
+        ArrayVec::<_, _> {
+            elements: SimValue::from_array_elements(
+                self.elements,
+                (0..self.elements.len()).map(|_| uninit_element.clone()),
+            ),
+            len: 0u8.cast_to(self.len),
+        }
+    }
+    #[hdl]
+    pub fn new_full_sim(
+        self,
+        elements: impl ToSimValueWithType<ArrayType<T, N>>,
+    ) -> SimValue<Self> {
+        let elements = elements.to_sim_value_with_type(self.elements);
+        #[hdl(sim)]
+        Self {
+            elements,
+            len: self.elements.len().to_sim_value_with_type(self.len),
+        }
+    }
+    pub fn from_iter_sim<I: IntoIterator<Item: ToSimValueWithType<T>>>(
+        self,
+        uninit_element: impl ToSimValueWithType<T>,
+        iter: I,
+    ) -> Result<SimValue<Self>, ArrayVecFullError<SimValue<Self>, I::IntoIter>> {
+        let mut value = Self::new_sim(self, uninit_element);
+        let element = self.element();
+        let mut iter = iter.into_iter();
+        for i in 0..self.capacity() {
+            let Some(v) = iter.next() else {
+                break;
+            };
+            value.elements[i] = v.into_sim_value_with_type(element);
+            *value.len = i + 1;
+        }
+        if let Some(extra) = iter.next() {
+            Err(ArrayVecFullError {
+                value,
+                rest: std::iter::once(extra).chain(iter),
+            })
+        } else {
+            Ok(value)
        }
    }
    pub fn element(self) -> T {
@ -176,8 +105,8 @@ impl<T: Type, N: Size> ArrayVec<T, N> {
        let elements = elements.to_expr();
        let len = len.to_expr();
        assert_eq!(
-            Length::new(N::from_usize(Expr::ty(elements).len())),
-            Expr::ty(len),
+            Length[N::from_usize(elements.ty().len())],
+            len.ty(),
            "len type mismatch",
        );
        #[hdl]
@ -189,9 +118,12 @@ impl<T: Type, N: Size> ArrayVec<T, N> {
    pub fn len(this: impl ToExpr<Type = Self>) -> Expr<Length<N>> {
        this.to_expr().len
    }
+    pub fn len_sim(this: &SimValue<Self>) -> &SimValue<Length<N>> {
+        &this.len
+    }
    pub fn is_empty(this: impl ToExpr<Type = Self>) -> Expr<Bool> {
        let len = Self::len(this);
-        len.cmp_eq(Expr::ty(len).zero())
+        len.cmp_eq(0u8)
    }
    pub fn capacity(self) -> usize {
        self.elements.len()
@ -207,11 +139,77 @@ impl<T: Type, N: Size> ArrayVec<T, N> {
        let this = this.to_expr();
        for (index, element) in this.elements.into_iter().enumerate() {
            #[hdl]
-            if index.cmp_lt(Length::as_uint(this.len)) {
+            if index.cmp_lt(this.len) {
                f(index, element);
            }
        }
    }
+    pub fn elements_sim_ref(this: &SimValue<Self>) -> &[SimValue<T>] {
+        &this.elements[..*this.len]
+    }
+    pub fn elements_sim_mut(this: &mut SimValue<Self>) -> &mut [SimValue<T>] {
+        let len = *this.len;
+        &mut this.elements[..len]
+    }
+    #[hdl]
+    pub async fn async_for_each_sim(
+        this: impl ToSimValue<Type = Self>,
+        mut f: impl AsyncFnMut(usize, SimValue<T>),
+    ) {
+        #[hdl(sim)]
+        let ArrayVec::<_, _> { elements, len } = this.into_sim_value();
+        for (index, element) in elements.into_iter().enumerate() {
+            if index.cmp_lt(*len) {
+                f(index, element).await;
+            }
+        }
+    }
+    #[hdl]
+    pub async fn async_for_each_sim_ref<'a>(
+        this: &'a SimValue<Self>,
+        mut f: impl AsyncFnMut(usize, &'a SimValue<T>),
+    ) {
+        #[hdl(sim)]
+        let ArrayVec::<_, _> { elements, len } = this;
+        for (index, element) in elements.iter().enumerate() {
+            if index.cmp_lt(**len) {
+                f(index, element).await;
+            }
+        }
+    }
+    #[hdl]
+    pub async fn async_for_each_sim_mut<'a>(
+        this: &'a mut SimValue<Self>,
+        mut f: impl AsyncFnMut(usize, &'a mut SimValue<T>),
+    ) {
+        #[hdl(sim)]
+        let ArrayVec::<_, _> { elements, len } = this;
+        for (index, element) in elements.iter_mut().enumerate() {
+            if index.cmp_lt(**len) {
+                f(index, element).await;
+            }
+        }
+    }
+    #[hdl]
+    pub fn try_push_sim(
+        this: &mut SimValue<Self>,
+        value: impl ToSimValueWithType<T>,
+    ) -> Result<(), SimValue<T>> {
+        let value = value.into_sim_value_with_type(this.ty().element());
+        let capacity = this.ty().capacity();
+        #[hdl(sim)]
+        let ArrayVec::<_, _> { elements, len } = this;
+        if **len < capacity {
+            elements[**len] = value;
+            **len += 1;
+            Ok(())
+        } else {
+            Err(value)
+        }
+    }
+    pub fn truncate_sim(this: &mut SimValue<Self>, len: usize) {
+        *this.len = len.min(*this.len);
+    }
    pub fn mapped_ty<U: Type>(self, new_element_ty: U) -> ArrayVec<U, N> {
        ArrayVec {
            elements: ArrayType[new_element_ty][N::from_usize(self.elements.len())],
@ -226,7 +224,7 @@ impl<T: Type, N: Size> ArrayVec<T, N> {
    ) -> Expr<ArrayVec<U, N>> {
        let this = this.to_expr();
        #[hdl]
-        let mapped_array_vec = wire(Expr::ty(this).mapped_ty(new_element_ty));
+        let mapped_array_vec = wire(this.ty().mapped_ty(new_element_ty));
        connect(mapped_array_vec.len, this.len);
        Self::for_each(this, |index, element| {
            connect(mapped_array_vec[index], f(index, element));
@ -234,15 +232,42 @@ impl<T: Type, N: Size> ArrayVec<T, N> {
        mapped_array_vec
    }
    #[hdl]
+    pub fn map_sim<U: Type>(
+        this: impl ToSimValue<Type = Self>,
+        uninit_element: impl ToSimValue<Type = U>,
+        mut f: impl FnMut(usize, SimValue<T>) -> SimValue<U>,
+    ) -> SimValue<ArrayVec<U, N>> {
+        let this = this.into_sim_value();
+        let uninit_element = uninit_element.into_sim_value();
+        let ty = this.ty().mapped_ty(uninit_element.ty());
+        #[hdl(sim)]
+        let Self { elements, len } = this;
+        #[hdl(sim)]
+        ArrayVec::<_, _> {
+            elements: SimValue::from_array_elements(
+                ty.elements,
+                SimValue::into_value(elements)
+                    .into_iter()
+                    .enumerate()
+                    .map(|(index, element)| {
+                        if index < *len {
+                            f(index, element)
+                        } else {
+                            uninit_element.clone()
+                        }
+                    }),
+            ),
+            len,
+        }
+    }
+    #[hdl]
    pub fn as_array_of_options(this: impl ToExpr<Type = Self>) -> Expr<ArrayType<HdlOption<T>, N>> {
        let this = this.to_expr();
        #[hdl]
-        let array_vec_as_array_of_options = wire(
-            ArrayType[HdlOption[Expr::ty(this).element()]]
-                [N::from_usize(Expr::ty(this).capacity())],
-        );
+        let array_vec_as_array_of_options =
+            wire(ArrayType[HdlOption[this.ty().element()]][N::from_usize(this.ty().capacity())]);
        for element in array_vec_as_array_of_options {
-            connect(element, Expr::ty(element).HdlNone());
+            connect(element, element.ty().HdlNone());
        }
        Self::for_each(this, |index, element| {
            connect(array_vec_as_array_of_options[index], HdlSome(element))
@ -263,3 +288,34 @@ where
        <ArrayType<T, N> as ExprIndex<Idx>>::expr_index(&this.elements, index)
    }
 }
+
+impl<T: Type> ArrayVec<T, ConstUsize<1>> {
+    #[hdl]
+    pub fn from_opt_sim(
+        opt: impl ToSimValue<Type = HdlOption<T>>,
+        uninit_element: impl ToSimValueWithType<T>,
+    ) -> SimValue<Self> {
+        let opt = opt.into_sim_value();
+        let ty = ArrayVec[opt.ty().HdlSome][ConstUsize];
+        #[hdl(sim)]
+        match opt {
+            HdlSome(v) => ty.new_full_sim([v]),
+            HdlNone => ty.new_sim(uninit_element),
+        }
+    }
+    #[hdl]
+    pub fn into_opt_sim(this: impl ToSimValue<Type = Self>) -> SimValue<HdlOption<T>> {
+        let this = this.into_sim_value();
+        #[hdl(sim)]
+        let Self { elements, len } = this;
+        let [element] = SimValue::into_value(elements);
+        let ty = HdlOption[element.ty()];
+        if *len == 0 {
+            #[hdl(sim)]
+            ty.HdlNone()
+        } else {
+            #[hdl(sim)]
+            ty.HdlSome(element)
+        }
+    }
+}
--- a/crates/cpu/tests/expected/fetch.vcd
+++ b/crates/cpu/tests/expected/fetch.vcd
--- a/crates/cpu/tests/expected/next_pc.vcd
+++ b/crates/cpu/tests/expected/next_pc.vcd
--- a/crates/cpu/tests/expected/receiver_and_uart_clock_gen.vcd
+++ b/crates/cpu/tests/expected/receiver_and_uart_clock_gen.vcd
--- a/crates/cpu/tests/expected/receiver_no_queue_and_uart_clock_gen.vcd
+++ b/crates/cpu/tests/expected/receiver_no_queue_and_uart_clock_gen.vcd
--- a/crates/cpu/tests/expected/reg_alloc.vcd
+++ b/crates/cpu/tests/expected/reg_alloc.vcd
--- a/crates/cpu/tests/expected/simple_uart.vcd
+++ b/crates/cpu/tests/expected/simple_uart.vcd
--- a/crates/cpu/tests/expected/transmitter_and_uart_clock_gen.vcd
+++ b/crates/cpu/tests/expected/transmitter_and_uart_clock_gen.vcd
--- a/crates/cpu/tests/fetch.rs
+++ b/crates/cpu/tests/fetch.rs
@ -0,0 +1,702 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+
+use cpu::{
+    config::{CpuConfig, UnitConfig},
+    fetch::{FetchToDecodeInterface, FetchToDecodeInterfaceInner, fetch},
+    main_memory_and_io::{
+        MemoryInterface, MemoryOperationErrorKind, MemoryOperationFinish,
+        MemoryOperationFinishKind, MemoryOperationKind, MemoryOperationStart,
+    },
+    next_pc::{FETCH_BLOCK_ID_WIDTH, NextPcToFetchInterface, NextPcToFetchInterfaceInner},
+    unit::UnitKind,
+    util::array_vec::ArrayVec,
+};
+use fayalite::{
+    prelude::*,
+    sim::vcd::VcdWriterDecls,
+    util::{DebugAsDisplay, RcWriter},
+};
+use std::{cell::RefCell, collections::VecDeque, fmt, num::NonZeroUsize};
+
+struct Random {
+    index: u64,
+}
+
+impl Random {
+    fn next(&mut self) -> u64 {
+        let index = self.index;
+        self.index = self.index.wrapping_add(1);
+        // make a pseudo-random number deterministically based on index
+        index
+            .wrapping_add(1)
+            .wrapping_mul(0x18C49126EABE7A0D) // random prime
+            .rotate_left(32)
+            .wrapping_mul(0x92B38C197608A6B) // random prime
+            .rotate_right(60)
+    }
+}
+
+const MEMORY_QUEUE_SIZE: usize = 16;
+
+#[hdl]
+struct MemoryQueueEntry {
+    addr: UInt<64>,
+    fetch_block_id: UInt<{ FETCH_BLOCK_ID_WIDTH }>,
+    cycles_left: UInt<8>,
+}
+
+impl MemoryQueueEntry {
+    #[hdl]
+    fn default_sim(self) -> SimValue<Self> {
+        #[hdl(sim)]
+        Self {
+            addr: 0u64,
+            fetch_block_id: self.fetch_block_id.zero(),
+            cycles_left: 0u8,
+        }
+    }
+    fn get_next_delay(random: &mut Random) -> u8 {
+        if random.next() % 32 == 0 { 30 } else { 5 }
+    }
+}
+
+const MEMORY_DATA: &str = "Test data, testing...\nTest Test!\nSecond Cache Line\nTesting.....\n";
+const MEMORY_START: u64 = 0x1000;
+const MEMORY_RANGE2: std::ops::Range<u64> = 0x2000..0x3000;
+const MEMORY_ERROR_RANGE: std::ops::Range<u64> = 0x10F00..0x20F00;
+const MEMORY_ERROR_STEP: u64 = 0x1000;
+
+fn read_memory(start: u64, len: usize) -> Option<&'static [u8]> {
+    if MEMORY_ERROR_RANGE.contains(&start) {
+        let start = start - MEMORY_ERROR_RANGE.start;
+        let fail_at = start / MEMORY_ERROR_STEP;
+        let offset = start % MEMORY_ERROR_STEP;
+        return if offset < fail_at {
+            [0xFFu8; MEMORY_DATA.len()].get(..len)
+        } else {
+            None
+        };
+    }
+    if MEMORY_RANGE2.contains(&start) {
+        return [0xF2u8; MEMORY_DATA.len()].get(..len);
+    }
+    MEMORY_DATA
+        .as_bytes()
+        .get(start.checked_sub(MEMORY_START)?.try_into().ok()?..)?
+        .get(..len)
+}
+
+#[hdl_module(extern)]
+fn mock_memory(config: PhantomConst<CpuConfig>) {
+    #[hdl]
+    let cd: ClockDomain = m.input();
+    #[hdl]
+    let memory_interface: MemoryInterface<PhantomConst<CpuConfig>> =
+        m.input(MemoryInterface[config]);
+    #[hdl]
+    let queue_debug: ArrayVec<MemoryQueueEntry, ConstUsize<{ MEMORY_QUEUE_SIZE }>> = m.output();
+    m.register_clock_for_past(cd.clk);
+    m.extern_module_simulation_fn(
+        (cd, memory_interface, queue_debug),
+        |(cd, memory_interface, queue_debug), mut sim| async move {
+            // intentionally have a different sequence each time we're reset
+            let random = RefCell::new(Random { index: 0 });
+            sim.resettable(
+                cd,
+                async |mut sim| {
+                    #[hdl]
+                    let MemoryInterface::<_> {
+                        start,
+                        finish,
+                        next_fetch_block_ids,
+                        config: _,
+                    } = memory_interface;
+                    sim.write(start.ready, false).await;
+                    sim.write(finish.data, finish.ty().data.HdlNone()).await;
+                    sim.write(next_fetch_block_ids, next_fetch_block_ids.ty().HdlNone())
+                        .await;
+                    sim.write(
+                        queue_debug,
+                        queue_debug.ty().new_sim(MemoryQueueEntry.default_sim()),
+                    )
+                    .await;
+                },
+                |sim, ()| run_fn(cd, memory_interface, queue_debug, &random, sim),
+            )
+            .await;
+        },
+    );
+    #[hdl]
+    async fn run_fn(
+        cd: Expr<ClockDomain>,
+        memory_interface: Expr<MemoryInterface<PhantomConst<CpuConfig>>>,
+        queue_debug: Expr<ArrayVec<MemoryQueueEntry, ConstUsize<{ MEMORY_QUEUE_SIZE }>>>,
+        random: &RefCell<Random>,
+        mut sim: ExternModuleSimulationState,
+    ) {
+        let mut random = random.borrow_mut();
+        let config = memory_interface.config.ty();
+        let finish_data_ty = memory_interface.finish.data.ty();
+        let next_fetch_block_ids_ty = memory_interface.next_fetch_block_ids.ty();
+        let mut queue: VecDeque<SimValue<MemoryQueueEntry>> = VecDeque::new();
+        loop {
+            for entry in &mut queue {
+                entry.cycles_left = entry.cycles_left.as_int().saturating_sub(1).to_sim_value();
+            }
+            let sim_queue = queue_debug
+                .ty()
+                .from_iter_sim(MemoryQueueEntry.default_sim(), &queue)
+                .ok()
+                .expect("queue is known to be small enough");
+            sim.write(queue_debug, sim_queue).await;
+            sim.write_bool(
+                memory_interface.start.ready,
+                queue.len() < MEMORY_QUEUE_SIZE && random.next() % 32 != 0,
+            )
+            .await;
+            sim.write(
+                memory_interface.next_fetch_block_ids,
+                #[hdl(sim)]
+                next_fetch_block_ids_ty.HdlSome(
+                    next_fetch_block_ids_ty
+                        .HdlSome
+                        .from_iter_sim(0u8, queue.iter().map(|entry| &entry.fetch_block_id))
+                        .ok()
+                        .expect("queue is known to be small enough"),
+                ),
+            )
+            .await;
+            let finish_data = if let Some(entry) = queue
+                .front()
+                .filter(|entry| entry.cycles_left.as_int() == 0)
+            {
+                #[hdl(sim)]
+                let MemoryQueueEntry {
+                    addr,
+                    fetch_block_id: _,
+                    cycles_left: _,
+                } = entry;
+                let addr = addr.as_int();
+                let mut read_data =
+                    repeat(0u8, finish_data_ty.HdlSome.read_data.len()).to_sim_value();
+                let kind = if let Some(data) = read_memory(addr, read_data.len()) {
+                    for (l, r) in read_data.iter_mut().zip(data) {
+                        *l = r.to_sim_value();
+                    }
+                    #[hdl(sim)]
+                    MemoryOperationFinishKind.Success(
+                        #[hdl(sim)]
+                        MemoryOperationKind.Read(),
+                    )
+                } else {
+                    #[hdl(sim)]
+                    MemoryOperationFinishKind.Error(
+                        #[hdl(sim)]
+                        MemoryOperationErrorKind.Generic(),
+                    )
+                };
+                #[hdl(sim)]
+                finish_data_ty.HdlSome(
+                    #[hdl(sim)]
+                    MemoryOperationFinish::<_> {
+                        kind,
+                        read_data,
+                        config,
+                    },
+                )
+            } else {
+                #[hdl(sim)]
+                finish_data_ty.HdlNone()
+            };
+            sim.write(memory_interface.finish.data, &finish_data).await;
+            sim.wait_for_clock_edge(cd.clk).await;
+            println!(
+                "Dump mock memory queue: {:#?}",
+                Vec::from_iter(queue.iter().map(|v| {
+                    DebugAsDisplay(format!(
+                        "fid={:#x} addr={:#x}",
+                        v.fetch_block_id.as_int(),
+                        v.addr.as_int(),
+                    ))
+                }))
+            );
+            if sim
+                .read_past_bool(memory_interface.start.ready, cd.clk)
+                .await
+            {
+                #[hdl(sim)]
+                if let HdlSome(memory_operation_start) =
+                    sim.read_past(memory_interface.start.data, cd.clk).await
+                {
+                    #[hdl(sim)]
+                    let MemoryOperationStart::<_> {
+                        kind,
+                        addr,
+                        write_data: _,
+                        rw_mask,
+                        fetch_block_id,
+                        config: _,
+                    } = memory_operation_start;
+                    #[hdl(sim)]
+                    match kind {
+                        MemoryOperationKind::Read => {}
+                        MemoryOperationKind::Write => unreachable!(),
+                    }
+                    assert!(
+                        rw_mask.iter().all(|v| **v),
+                        "rw_mask should be all true: {rw_mask:?}"
+                    );
+                    let entry = #[hdl(sim)]
+                    MemoryQueueEntry {
+                        addr,
+                        fetch_block_id,
+                        cycles_left: MemoryQueueEntry::get_next_delay(&mut random),
+                    };
+                    println!("mock memory start: {entry:#?}");
+                    queue.push_back(entry);
+                }
+            }
+            if sim
+                .read_past_bool(memory_interface.finish.ready, cd.clk)
+                .await
+            {
+                #[hdl(sim)]
+                if let HdlSome(finish_data) = finish_data {
+                    let Some(entry) = queue.pop_front() else {
+                        unreachable!();
+                    };
+                    #[hdl(sim)]
+                    let MemoryOperationFinish::<_> {
+                        kind,
+                        read_data,
+                        config: _,
+                    } = finish_data;
+                    let kind = #[hdl(sim)]
+                    match kind {
+                        MemoryOperationFinishKind::Error(_) => Err(()),
+                        MemoryOperationFinishKind::Success(_) => Ok(()),
+                    };
+                    println!(
+                        "mock memory finish: kind={kind:?} read_data={read_data:?} {entry:#?}"
+                    );
+                }
+            }
+        }
+    }
+}
+
+#[hdl_module]
+fn dut(config: PhantomConst<CpuConfig>) {
+    #[hdl]
+    let cd: ClockDomain = m.input();
+    #[hdl]
+    let from_next_pc: NextPcToFetchInterface<PhantomConst<CpuConfig>> =
+        m.input(NextPcToFetchInterface[config]);
+    #[hdl]
+    let to_decode: FetchToDecodeInterface<PhantomConst<CpuConfig>> =
+        m.output(FetchToDecodeInterface[config]);
+    #[hdl]
+    let fetch = instance(fetch(config));
+    #[hdl]
+    let fetch {
+        cd: fetch_cd,
+        memory_interface: fetch_memory_interface,
+        from_next_pc: fetch_from_next_pc,
+        to_decode: fetch_to_decode,
+    } = fetch;
+    connect(fetch_cd, cd);
+    connect(fetch_from_next_pc, from_next_pc);
+    connect(to_decode, fetch_to_decode);
+    #[hdl]
+    let mock_memory = instance(mock_memory(config));
+    #[hdl]
+    let mock_memory {
+        cd: mock_memory_cd,
+        memory_interface: mock_memory_interface,
+        queue_debug: _,
+    } = mock_memory;
+    connect(mock_memory_cd, cd);
+    connect(mock_memory_interface, fetch_memory_interface);
+}
+
+#[derive(Clone)]
+struct FetchTestOperation {
+    start_pc: u64,
+    fetch_block_id: u8,
+    fetch_block_data: [u8; FETCH_WIDTH_IN_BYTES],
+    error: Option<SimValue<MemoryOperationErrorKind>>,
+}
+
+impl PartialEq for FetchTestOperation {
+    #[hdl]
+    fn eq(&self, other: &Self) -> bool {
+        let Self {
+            start_pc,
+            fetch_block_id,
+            fetch_block_data,
+            ref error,
+        } = *self;
+        if let Some(error) = error {
+            #[hdl(sim)]
+            match error {
+                MemoryOperationErrorKind::Generic => {}
+            }
+        }
+        start_pc == other.start_pc
+            && fetch_block_id == other.fetch_block_id
+            && fetch_block_data == other.fetch_block_data
+            && error.is_some() == other.error.is_some()
+    }
+}
+
+impl fmt::Debug for FetchTestOperation {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        let Self {
+            start_pc,
+            fetch_block_id,
+            fetch_block_data,
+            error,
+        } = self;
+        let mut debug_struct = f.debug_struct("FetchTestOperation");
+        debug_struct.field("start_pc", &format_args!("{start_pc:#x}"));
+        debug_struct.field("fetch_block_id", &format_args!("{fetch_block_id:#x}"));
+        if fetch_block_data.iter().all(|v| *v == fetch_block_data[0]) {
+            debug_struct.field(
+                "fetch_block_data",
+                &format_args!(
+                    "[b'{}'; {FETCH_WIDTH_IN_BYTES}]",
+                    fetch_block_data[0].escape_ascii(),
+                ),
+            );
+        } else {
+            debug_struct.field(
+                "fetch_block_data",
+                &format_args!("b\"{}\"", fetch_block_data.escape_ascii()),
+            );
+        }
+        debug_struct.field("error", error).finish()
+    }
+}
+
+const LOG2_FETCH_WIDTH_IN_BYTES: u8 = 3;
+const FETCH_WIDTH_IN_BYTES: usize = 1 << LOG2_FETCH_WIDTH_IN_BYTES;
+const LOG2_CACHE_LINE_SIZE_IN_BYTES: u8 = 5;
+const CACHE_LINE_SIZE_IN_BYTES: usize = 1 << LOG2_CACHE_LINE_SIZE_IN_BYTES;
+
+// needs to be a multiple of the cache line size
+const _: [(); CACHE_LINE_SIZE_IN_BYTES * 2] = [(); MEMORY_DATA.len()];
+
+fn fetch_test_operations() -> Vec<FetchTestOperation> {
+    #[track_caller]
+    fn mem_data(r: std::ops::RangeFrom<usize>) -> [u8; FETCH_WIDTH_IN_BYTES] {
+        *MEMORY_DATA[r]
+            .as_bytes()
+            .first_chunk()
+            .expect("start should be in-range")
+    }
+    #[hdl]
+    fn generic_error() -> SimValue<MemoryOperationErrorKind> {
+        #[hdl(sim)]
+        MemoryOperationErrorKind.Generic()
+    }
+    let mut last_fetch_block_id = 0u8.wrapping_sub(1);
+    macro_rules! op {
+        {
+            $($field:ident: $value:expr,)*
+        } => {
+            FetchTestOperation {
+                fetch_block_id: {
+                    last_fetch_block_id = last_fetch_block_id.wrapping_add(1);
+                    last_fetch_block_id
+                },
+                $($field: $value,)*
+            }
+        };
+    }
+    vec![
+        op! {
+            start_pc: 0x1000,
+            fetch_block_data: mem_data(0..),
+            error: None,
+        },
+        op! {
+            start_pc: 0x1010,
+            fetch_block_data: mem_data(0x10..),
+            error: None,
+        },
+        op! {
+            start_pc: 0x1020,
+            fetch_block_data: mem_data(0x20..),
+            error: None,
+        },
+        op! {
+            start_pc: 0x100,
+            fetch_block_data: [0; _],
+            error: Some(generic_error()),
+        },
+        op! {
+            start_pc: MEMORY_ERROR_RANGE.start,
+            fetch_block_data: [0; _],
+            error: Some(generic_error()),
+        },
+        op! {
+            start_pc: MEMORY_ERROR_RANGE.start + MEMORY_ERROR_STEP,
+            fetch_block_data: [0; _],
+            error: Some(generic_error()),
+        },
+        op! {
+            start_pc: MEMORY_ERROR_RANGE.start + MEMORY_ERROR_STEP * 2,
+            fetch_block_data: [0; _],
+            error: Some(generic_error()),
+        },
+        op! {
+            start_pc: MEMORY_ERROR_RANGE.start + MEMORY_ERROR_STEP * 3,
+            fetch_block_data: [0; _],
+            error: Some(generic_error()),
+        },
+        op! {
+            start_pc: 0x1000,
+            fetch_block_data: mem_data(0..),
+            error: None,
+        },
+        op! {
+            start_pc: 0x1010,
+            fetch_block_data: mem_data(0x10..),
+            error: None,
+        },
+        op! {
+            start_pc: 0x1020,
+            fetch_block_data: mem_data(0x20..),
+            error: None,
+        },
+        op! {
+            start_pc: 0x1000,
+            fetch_block_data: mem_data(0..),
+            error: None,
+        },
+        op! {
+            start_pc: 0x1010,
+            fetch_block_data: mem_data(0x10..),
+            error: None,
+        },
+        op! {
+            start_pc: 0x1020,
+            fetch_block_data: mem_data(0x20..),
+            error: None,
+        },
+        op! {
+            start_pc: MEMORY_RANGE2.start,
+            fetch_block_data: [0xF2; _],
+            error: None,
+        },
+        op! {
+            start_pc: MEMORY_RANGE2.start,
+            fetch_block_data: [0xF2; _],
+            error: None,
+        },
+        op! {
+            start_pc: MEMORY_RANGE2.start,
+            fetch_block_data: [0xF2; _],
+            error: None,
+        },
+        op! {
+            start_pc: MEMORY_RANGE2.start,
+            fetch_block_data: [0xF2; _],
+            error: None,
+        },
+        op! {
+            start_pc: MEMORY_RANGE2.start,
+            fetch_block_data: [0xF2; _],
+            error: None,
+        },
+        op! {
+            start_pc: MEMORY_RANGE2.start,
+            fetch_block_data: [0xF2; _],
+            error: None,
+        },
+        op! {
+            start_pc: MEMORY_RANGE2.start,
+            fetch_block_data: [0xF2; _],
+            error: None,
+        },
+        op! {
+            start_pc: 0x1000,
+            fetch_block_data: mem_data(0..),
+            error: None,
+        },
+        op! {
+            start_pc: 0x1000,
+            fetch_block_data: mem_data(0..),
+            error: None,
+        },
+        op! {
+            start_pc: 0x1000,
+            fetch_block_data: mem_data(0..),
+            error: None,
+        },
+        op! {
+            start_pc: 0x1000,
+            fetch_block_data: mem_data(0..),
+            error: None,
+        },
+        op! {
+            start_pc: 0x1000,
+            fetch_block_data: mem_data(0..),
+            error: None,
+        },
+        op! {
+            start_pc: 0x1000,
+            fetch_block_data: mem_data(0..),
+            error: None,
+        },
+    ]
+}
+
+#[test]
+#[hdl]
+fn test_fetch() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let mut config = CpuConfig::new(
+        vec![
+            UnitConfig::new(UnitKind::AluBranch),
+            UnitConfig::new(UnitKind::AluBranch),
+        ],
+        NonZeroUsize::new(20).unwrap(),
+    );
+    config.fetch_width = NonZeroUsize::new(2).unwrap();
+    config.log2_fetch_width_in_bytes = LOG2_FETCH_WIDTH_IN_BYTES;
+    config.log2_cache_line_size_in_bytes = LOG2_CACHE_LINE_SIZE_IN_BYTES;
+    config.log2_l1_i_cache_line_count = 4;
+    let m = dut(PhantomConst::new_sized(config));
+    let mut sim = Simulation::new(m);
+    let writer = RcWriter::default();
+    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
+    struct DumpVcdOnDrop {
+        writer: Option<RcWriter>,
+    }
+    impl Drop for DumpVcdOnDrop {
+        fn drop(&mut self) {
+            if let Some(mut writer) = self.writer.take() {
+                let vcd = String::from_utf8(writer.take()).unwrap();
+                println!("####### VCD:\n{vcd}\n#######");
+            }
+        }
+    }
+    let mut writer = DumpVcdOnDrop {
+        writer: Some(writer),
+    };
+    let from_next_pc_ty = sim.io().from_next_pc.ty();
+    sim.write_clock(sim.io().cd.clk, false);
+    sim.write_reset(sim.io().cd.rst, true);
+    sim.write(
+        sim.io().from_next_pc.cancel.data,
+        from_next_pc_ty.cancel.data.HdlNone(),
+    );
+    sim.write(
+        sim.io().from_next_pc.fetch.data,
+        from_next_pc_ty.fetch.data.HdlNone(),
+    );
+    sim.write(sim.io().to_decode.fetched.ready, true);
+    sim.write(
+        sim.io().to_decode.next_fetch_block_ids,
+        HdlSome(
+            sim.io()
+                .ty()
+                .to_decode
+                .next_fetch_block_ids
+                .HdlSome
+                .new_sim(0u8),
+        ),
+    );
+    let operations = fetch_test_operations();
+    let mut started_operations = 0;
+    let mut finished_operations = 0;
+    for cycle in 0..150 {
+        sim.write(
+            sim.io().from_next_pc.fetch.data,
+            if let Some(op) = operations.get(started_operations) {
+                #[hdl(sim)]
+                HdlSome(
+                    #[hdl(sim)]
+                    NextPcToFetchInterfaceInner {
+                        start_pc: op.start_pc,
+                        fetch_block_id: op.fetch_block_id,
+                    },
+                )
+            } else {
+                #[hdl(sim)]
+                HdlNone()
+            },
+        );
+        sim.advance_time(SimDuration::from_nanos(500));
+        #[hdl(sim)]
+        if let HdlSome(next_fetch_block_ids) = sim.read(sim.io().from_next_pc.next_fetch_block_ids)
+        {
+            let next_fetch_block_ids = ArrayVec::elements_sim_ref(&next_fetch_block_ids);
+            let expected_next_fetch_block_ids = Vec::from_iter(
+                operations
+                    .get(finished_operations..started_operations)
+                    .unwrap_or(&[])
+                    .iter()
+                    .map(|op| op.fetch_block_id.to_sim_value()),
+            );
+            println!("expected_next_fetch_block_ids={expected_next_fetch_block_ids:?}");
+            assert_eq!(next_fetch_block_ids, expected_next_fetch_block_ids);
+        }
+        if sim.read_bool(sim.io().from_next_pc.fetch.ready) {
+            #[hdl(sim)]
+            if let HdlSome(_) = sim.read(sim.io().from_next_pc.fetch.data) {
+                println!("started fetch: {:#?}", operations[started_operations]);
+                started_operations += 1;
+            }
+        } else {
+            println!("not ready to start fetch");
+        }
+        if sim.read_bool(sim.io().to_decode.fetched.ready) {
+            #[hdl(sim)]
+            if let HdlSome(fetched) = sim.read(sim.io().to_decode.fetched.data) {
+                #[hdl(sim)]
+                let FetchToDecodeInterfaceInner::<_> {
+                    start_pc,
+                    fetch_block_id,
+                    fetch_block_data,
+                    error,
+                    config: _,
+                } = &fetched;
+                let Some(expected_op) = operations.get(finished_operations) else {
+                    panic!("too many finished operations: {fetched:#?}");
+                };
+                let op = FetchTestOperation {
+                    start_pc: start_pc.as_int(),
+                    fetch_block_id: fetch_block_id.as_int(),
+                    error: #[hdl(sim)]
+                    match error {
+                        HdlSome(e) => Some(e.clone()),
+                        HdlNone => None,
+                    },
+                    fetch_block_data: std::array::from_fn(|i| fetch_block_data[i].as_int()),
+                };
+                println!("finished fetch: op={op:#?}");
+                assert_eq!(
+                    op, *expected_op,
+                    "cycle={cycle} finished_operations={finished_operations}",
+                );
+                finished_operations += 1;
+            } else {
+                println!("not ready to finish fetch");
+            }
+        }
+        println!("clock tick: {cycle}");
+        sim.write_clock(sim.io().cd.clk, true);
+        sim.advance_time(SimDuration::from_nanos(500));
+        sim.write_clock(sim.io().cd.clk, false);
+        sim.write_reset(sim.io().cd.rst, false);
+    }
+    assert_eq!(finished_operations, operations.len());
+    let vcd = String::from_utf8(writer.writer.take().unwrap().take()).unwrap();
+    println!("####### VCD:\n{vcd}\n#######");
+    if vcd != include_str!("expected/fetch.vcd") {
+        panic!();
+    }
+}
--- a/crates/cpu/tests/next_pc.rs
+++ b/crates/cpu/tests/next_pc.rs
--- a/crates/cpu/tests/reg_alloc.rs
+++ b/crates/cpu/tests/reg_alloc.rs
@ -3,14 +3,12 @@

 use cpu::{
    config::{CpuConfig, UnitConfig},
-    instruction::{AddSubMOp, LogicalMOp, MOp, MOpDestReg, MOpRegNum, OutputIntegerMode},
+    instruction::{AddSubMOp, LogicalMOp, Lut4, MOp, MOpDestReg, MOpRegNum, OutputIntegerMode},
    reg_alloc::{FetchedDecodedMOp, reg_alloc},
    register::{FlagsMode, PRegFlagsPowerISA},
    unit::{GlobalState, UnitKind},
 };
 use fayalite::{
-    assert_export_firrtl,
-    firrtl::ExportOptions,
    prelude::*,
    sim::{Simulation, time::SimDuration, vcd::VcdWriterDecls},
    util::RcWriter,
@ -61,7 +59,7 @@ fn test_reg_alloc() {
                [HdlSome(()), HdlNone()],
            },
            [0u8; 2],
-            0x12345678u32.cast_to_static(),
+            0x12345678u32.cast_to_static::<SInt<_>>(),
            OutputIntegerMode.DupLow32(),
            false,
            false,
@ -83,7 +81,7 @@ fn test_reg_alloc() {
                [HdlSome(()), HdlNone()],
            },
            [1u8, 0, 0],
-            1.cast_to_static(),
+            1.cast_to_static::<SInt<_>>(),
            OutputIntegerMode.Full64(),
            false,
            false,
@ -101,9 +99,9 @@ fn test_reg_alloc() {
                flag_regs: [HdlNone(), HdlSome(())],
            },
            [2u8, 4u8],
-            0.cast_to_static(),
+            0.cast_to_static::<SInt<_>>(),
            OutputIntegerMode.Full64(),
-            0b0110_hdl_u4,
+            Lut4::from_fn(|a, b| a ^ b),
        ),
    ];
    let insns = insns_init.into_iter().chain(insns_loop.into_iter().cycle());
--- a/crates/cpu/tests/simple_power_isa_decoder/expected/decode_one_insn.vcd
+++ b/crates/cpu/tests/simple_power_isa_decoder/expected/decode_one_insn.vcd
--- a/crates/cpu/tests/simple_power_isa_decoder/main.rs
+++ b/crates/cpu/tests/simple_power_isa_decoder/main.rs
@ -0,0 +1,208 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+
+use crate::test_cases::TestCase;
+use cpu::{
+    decoder::simple_power_isa::decode_one_insn, instruction::MOp, util::array_vec::ArrayVec,
+};
+use fayalite::{prelude::*, sim::vcd::VcdWriterDecls, util::RcWriter};
+use std::{fmt::Write as _, io::Write, process::Command};
+
+mod test_cases;
+
+#[test]
+fn test_test_cases_assembly() -> std::io::Result<()> {
+    let llvm_mc_regex = regex::Regex::new(r"llvm-mc(-\d+)?$").expect("known to be a valid regex");
+    let llvm_mc = which::which_re(llvm_mc_regex)
+        .expect("can't find llvm-mc or llvm-mc-<num> in path")
+        .next()
+        .expect("can't find llvm-mc or llvm-mc-<num> in path");
+    let test_cases = test_cases::test_cases();
+    let mut assembly = String::new();
+    for TestCase {
+        mnemonic,
+        first_input: _,
+        second_input: _,
+        output: _,
+        loc: _,
+    } in &test_cases
+    {
+        writeln!(assembly, "{mnemonic}").unwrap();
+    }
+    let (reader, mut writer) = std::io::pipe()?;
+    let thread = std::thread::spawn(move || writer.write_all(assembly.as_bytes()));
+    let std::process::Output {
+        status,
+        stdout,
+        stderr,
+    } = Command::new(&llvm_mc)
+        .arg("--triple=powerpc64le-linux-gnu")
+        .arg("--assemble")
+        .arg("--filetype=asm")
+        .arg("--show-encoding")
+        .arg("-")
+        .stdin(reader)
+        .output()?;
+    let _ = thread.join();
+    let stderr = String::from_utf8_lossy(&stderr);
+    eprint!("{stderr}");
+    if !status.success() {
+        panic!("{} failed: {status}", llvm_mc.display());
+    }
+    let stdout = String::from_utf8_lossy(&stdout);
+    print!("{stdout}");
+    let mut lines = stdout.lines();
+    let text_line = lines.next();
+    assert_eq!(text_line, Some("\t.text"));
+    let mut any_error = false;
+    macro_rules! assert_eq_cont {
+        ($l:expr, $r:expr, $($msg:tt)+) => {
+            match (&$l, &$r) {
+                (l, r) => if l != r {
+                    eprintln!("assertion failed: {}\nl={l:#?}\nr={r:#?}", format_args!($($msg)+));
+                    any_error = true;
+                }
+            }
+        };
+    }
+    for test_case @ TestCase {
+        mnemonic: _,
+        first_input,
+        second_input,
+        output: _,
+        loc: _,
+    } in test_cases
+    {
+        let Some(line) = lines.next() else {
+            panic!("output missing line for: {test_case:?}");
+        };
+        if line.starts_with("\t.long") {
+            assert_eq!(
+                line,
+                format!("\t.long\t{first_input}"),
+                "test_case={test_case:?}\nline:\n{line}"
+            );
+            if let Some(second_input) = second_input {
+                let Some(line) = lines.next() else {
+                    panic!("output missing line for: {test_case:?}");
+                };
+                assert_eq!(
+                    line,
+                    format!("\t.long\t{second_input}"),
+                    "test_case={test_case:?}\nline:\n{line}"
+                );
+            }
+            continue;
+        }
+        let Some((_, comment)) = line.split_once('#') else {
+            panic!("output line missing comment. test_case={test_case:?}\nline:\n{line}");
+        };
+        let [b0, b1, b2, b3] = first_input.to_le_bytes();
+        let expected_comment = if let Some(second_input) = second_input {
+            let [b4, b5, b6, b7] = second_input.to_le_bytes();
+            format!(
+                " encoding: [0x{b0:02x},0x{b1:02x},0x{b2:02x},0x{b3:02x},0x{b4:02x},0x{b5:02x},0x{b6:02x},0x{b7:02x}]"
+            )
+        } else {
+            format!(" encoding: [0x{b0:02x},0x{b1:02x},0x{b2:02x},0x{b3:02x}]")
+        };
+        assert_eq_cont!(
+            comment,
+            expected_comment,
+            "test_case={test_case:?}\nline:\n{line}"
+        );
+    }
+    for line in lines {
+        assert!(line.trim().is_empty(), "bad trailing output line: {line:?}");
+    }
+    if any_error {
+        panic!();
+    }
+    Ok(())
+}
+
+#[hdl]
+#[test]
+fn test_decode_insn() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let m = decode_one_insn();
+    let mut sim = Simulation::new(m);
+    let writer = RcWriter::default();
+    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
+    struct DumpVcdOnDrop {
+        writer: Option<RcWriter>,
+    }
+    impl Drop for DumpVcdOnDrop {
+        fn drop(&mut self) {
+            if let Some(mut writer) = self.writer.take() {
+                let vcd = String::from_utf8(writer.take()).unwrap();
+                println!("####### VCD:\n{vcd}\n#######");
+            }
+        }
+    }
+    let mut writer = DumpVcdOnDrop {
+        writer: Some(writer),
+    };
+    for test_case @ TestCase {
+        mnemonic: _,
+        first_input,
+        second_input,
+        output: _,
+        loc: _,
+    } in test_cases::test_cases()
+    {
+        sim.write(sim.io().first_input, first_input);
+        sim.write(
+            sim.io().second_input,
+            if let Some(v) = second_input {
+                #[hdl(sim)]
+                HdlSome(v)
+            } else {
+                #[hdl(sim)]
+                HdlNone()
+            },
+        );
+        sim.advance_time(SimDuration::from_micros(1));
+        let second_input_used = sim.read_bool(sim.io().second_input_used);
+        let is_illegal = sim.read_bool(sim.io().is_illegal);
+        let output = sim.read(sim.io().output);
+        #[derive(Debug)]
+        #[expect(dead_code, reason = "used only for Debug formatting")]
+        struct FormattedOutput<'a> {
+            insns: &'a [SimValue<MOp>],
+            second_input_used: bool,
+            is_illegal: bool,
+        }
+        let expected = format!(
+            "{:#?}",
+            FormattedOutput {
+                insns: ArrayVec::elements_sim_ref(&test_case.output),
+                second_input_used: second_input.is_some(),
+                is_illegal: false,
+            },
+        );
+        let output = format!(
+            "{:#?}",
+            FormattedOutput {
+                insns: ArrayVec::elements_sim_ref(&output),
+                second_input_used,
+                is_illegal,
+            },
+        );
+        assert!(
+            expected == output,
+            "test_case={test_case:#?}\noutput={output}\nexpected={expected}"
+        );
+    }
+    let vcd = String::from_utf8(writer.writer.take().unwrap().take()).unwrap();
+    println!("####### VCD:\n{vcd}\n#######");
+    if vcd != include_str!("expected/decode_one_insn.vcd") {
+        panic!();
+    }
+}
+
+#[hdl]
+#[test]
+fn test_simple_power_isa_decoder() {
+    // TODO
+}
--- a/crates/cpu/tests/simple_power_isa_decoder/test_cases.rs
+++ b/crates/cpu/tests/simple_power_isa_decoder/test_cases.rs
@ -0,0 +1,158 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+
+use cpu::{instruction::MOp, util::array_vec::ArrayVec};
+use fayalite::prelude::*;
+use std::fmt;
+
+mod branch;
+mod condition_register;
+mod fixed_point_arithmetic;
+mod fixed_point_compare;
+mod fixed_point_load;
+mod fixed_point_logical;
+mod fixed_point_rotate_and_shift;
+mod fixed_point_store;
+mod move_to_from_system_register;
+mod prefixed_no_operation;
+
+pub struct TestCase {
+    pub mnemonic: &'static str,
+    pub first_input: u32,
+    pub second_input: Option<u32>,
+    pub output: SimValue<ArrayVec<MOp, ConstUsize<3>>>,
+    pub loc: &'static std::panic::Location<'static>,
+}
+
+impl fmt::Debug for TestCase {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        let Self {
+            mnemonic,
+            first_input,
+            second_input,
+            output,
+            loc,
+        } = self;
+        let mut debug_struct = f.debug_struct("TestCase");
+        debug_struct
+            .field("mnemonic", mnemonic)
+            .field("first_input", &format_args!("0x{first_input:08x}"));
+        if let Some(second_input) = second_input {
+            debug_struct.field("second_input", &format_args!("0x{second_input:08x}"));
+        } else {
+            debug_struct.field("second_input", &format_args!("None"));
+        }
+        debug_struct
+            .field("output", &ArrayVec::elements_sim_ref(output))
+            .field("loc", &format_args!("{loc}"))
+            .finish()
+    }
+}
+
+#[track_caller]
+fn insn_empty(mnemonic: &'static str, first_input: u32, second_input: Option<u32>) -> TestCase {
+    let zero_mop = UInt::new_dyn(MOp.canonical().bit_width())
+        .zero()
+        .cast_bits_to(MOp);
+    TestCase {
+        mnemonic,
+        first_input,
+        second_input,
+        output: ArrayVec::new_sim(ArrayVec[MOp][ConstUsize], &zero_mop),
+        loc: std::panic::Location::caller(),
+    }
+}
+
+#[track_caller]
+fn insn_single(
+    mnemonic: &'static str,
+    first_input: u32,
+    second_input: Option<u32>,
+    output: impl ToSimValue<Type = MOp>,
+) -> TestCase {
+    let zero_mop = UInt::new_dyn(MOp.canonical().bit_width())
+        .zero()
+        .cast_bits_to(MOp);
+    let mut single_storage = ArrayVec::new_sim(ArrayVec[MOp][ConstUsize], &zero_mop);
+    ArrayVec::try_push_sim(&mut single_storage, zero_mop).expect("known to have space");
+    ArrayVec::elements_sim_mut(&mut single_storage)[0] = output.to_sim_value();
+    TestCase {
+        mnemonic,
+        first_input,
+        second_input,
+        output: single_storage,
+        loc: std::panic::Location::caller(),
+    }
+}
+
+#[track_caller]
+fn insn_double(
+    mnemonic: &'static str,
+    first_input: u32,
+    second_input: Option<u32>,
+    insns: [impl ToSimValue<Type = MOp>; 2],
+) -> TestCase {
+    let zero_mop = UInt::new_dyn(MOp.canonical().bit_width())
+        .zero()
+        .cast_bits_to(MOp);
+    let mut single_storage = ArrayVec::new_sim(ArrayVec[MOp][ConstUsize], &zero_mop);
+    ArrayVec::try_push_sim(&mut single_storage, &zero_mop).expect("known to have space");
+    ArrayVec::try_push_sim(&mut single_storage, zero_mop).expect("known to have space");
+    ArrayVec::elements_sim_mut(&mut single_storage)[0] = insns[0].to_sim_value();
+    ArrayVec::elements_sim_mut(&mut single_storage)[1] = insns[1].to_sim_value();
+    TestCase {
+        mnemonic,
+        first_input,
+        second_input,
+        output: single_storage,
+        loc: std::panic::Location::caller(),
+    }
+}
+
+#[track_caller]
+fn insn_triple(
+    mnemonic: &'static str,
+    first_input: u32,
+    second_input: Option<u32>,
+    insns: [impl ToSimValue<Type = MOp>; 3],
+) -> TestCase {
+    let zero_mop = UInt::new_dyn(MOp.canonical().bit_width())
+        .zero()
+        .cast_bits_to(MOp);
+    let mut single_storage = ArrayVec::new_sim(ArrayVec[MOp][ConstUsize], &zero_mop);
+    ArrayVec::try_push_sim(&mut single_storage, &zero_mop).expect("known to have space");
+    ArrayVec::try_push_sim(&mut single_storage, &zero_mop).expect("known to have space");
+    ArrayVec::try_push_sim(&mut single_storage, zero_mop).expect("known to have space");
+    ArrayVec::elements_sim_mut(&mut single_storage)[0] = insns[0].to_sim_value();
+    ArrayVec::elements_sim_mut(&mut single_storage)[1] = insns[1].to_sim_value();
+    ArrayVec::elements_sim_mut(&mut single_storage)[2] = insns[2].to_sim_value();
+    TestCase {
+        mnemonic,
+        first_input,
+        second_input,
+        output: single_storage,
+        loc: std::panic::Location::caller(),
+    }
+}
+
+pub fn test_cases() -> Vec<TestCase> {
+    let mut retval = Vec::new();
+    branch::test_cases_book_i_2_4_branch(&mut retval);
+    condition_register::test_cases_book_i_2_5_condition_register(&mut retval);
+    fixed_point_load::test_cases_book_i_3_3_2_fixed_point_load(&mut retval);
+    fixed_point_store::test_cases_book_i_3_3_3_fixed_point_store(&mut retval);
+    fixed_point_arithmetic::test_cases_book_i_3_3_9_fixed_point_arithmetic(&mut retval);
+    fixed_point_compare::test_cases_book_i_3_3_10_fixed_point_compare(&mut retval);
+    fixed_point_logical::test_cases_book_i_3_3_13_fixed_point_logical(&mut retval);
+    fixed_point_rotate_and_shift::test_cases_book_i_3_3_14_fixed_point_rotate_and_shift(
+        &mut retval,
+    );
+    move_to_from_system_register::test_cases_book_i_3_3_19_move_to_from_system_register(
+        &mut retval,
+    );
+    prefixed_no_operation::test_cases_book_i_3_3_20_prefixed_no_operation(&mut retval);
+    move_to_from_system_register::test_cases_book_iii_5_4_4_move_to_from_system_register(
+        &mut retval,
+    );
+    retval
+}
--- a/crates/cpu/tests/simple_power_isa_decoder/test_cases/branch.rs
+++ b/crates/cpu/tests/simple_power_isa_decoder/test_cases/branch.rs
@ -0,0 +1,446 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+
+use crate::test_cases::{TestCase, insn_double, insn_single};
+use cpu::instruction::{
+    AddSubMOp, BranchMOp, ConditionMode, MOp, MOpDestReg, MOpRegNum, OutputIntegerMode,
+};
+use fayalite::prelude::*;
+
+/// covers instructions in PowerISA v3.1C Book I 2.4 Branch Instructions
+pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
+    retval.push(insn_single(
+        "b 0x345678",
+        0x48345678,
+        None,
+        BranchMOp::branch_i(
+            MOpDestReg::new_sim(&[], &[]),
+            MOpRegNum::const_zero().value,
+            0x345678.cast_to_static::<SInt<_>>(),
+            true,
+            false,
+            false,
+        ),
+    ));
+    retval.push(insn_single(
+        "ba 0x345678",
+        0x4834567a,
+        None,
+        BranchMOp::branch_i(
+            MOpDestReg::new_sim(&[], &[]),
+            MOpRegNum::const_zero().value,
+            0x345678.cast_to_static::<SInt<_>>(),
+            false,
+            false,
+            false,
+        ),
+    ));
+    retval.push(insn_single(
+        "bl 0x345678",
+        0x48345679,
+        None,
+        BranchMOp::branch_i(
+            MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_LR_REG_NUM], &[]),
+            MOpRegNum::const_zero().value,
+            0x345678.cast_to_static::<SInt<_>>(),
+            true,
+            true,
+            false,
+        ),
+    ));
+    retval.push(insn_single(
+        "bla 0x345678",
+        0x4834567b,
+        None,
+        BranchMOp::branch_i(
+            MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_LR_REG_NUM], &[]),
+            MOpRegNum::const_zero().value,
+            0x345678.cast_to_static::<SInt<_>>(),
+            false,
+            true,
+            false,
+        ),
+    ));
+    fn insn_dec_ctr_and(
+        mnemonic: &'static str,
+        first_input: u32,
+        second_input: Option<u32>,
+        second_insn: impl ToSimValue<Type = MOp>,
+    ) -> TestCase {
+        insn_double(
+            mnemonic,
+            first_input,
+            second_input,
+            [
+                AddSubMOp::add_sub_i::<MOp>(
+                    MOpDestReg::new([MOpRegNum::power_isa_ctr_reg()], []),
+                    [
+                        MOpRegNum::power_isa_ctr_reg().value,
+                        MOpRegNum::const_zero().value,
+                    ],
+                    (-1).cast_to_static::<SInt<_>>(),
+                    OutputIntegerMode.Full64(),
+                    false,
+                    false,
+                    false,
+                    false,
+                )
+                .into_sim_value(),
+                second_insn.into_sim_value(),
+            ],
+        )
+    }
+    macro_rules! insn_branch_conds {
+        (
+            mnemonic = $mnemonic:literal;
+            mnemonic_l = $mnemonic_l:literal;
+            asm_last_arg = $asm_last_arg:literal;
+            imm = $imm:literal;
+            encoding = $encoding:literal;
+            src1 = $src1:expr;
+            pc_relative = $pc_relative:expr;
+            is_ret = $is_ret:expr;
+        ) => {
+            insn_branch_conds! {
+                mnemonic = $mnemonic;
+                asm_last_arg = $asm_last_arg;
+                imm = $imm;
+                encoding = $encoding;
+                dest = MOpDestReg::new_sim(&[], &[]);
+                src1 = $src1;
+                pc_relative = $pc_relative;
+                lk = false;
+                is_ret = $is_ret;
+            }
+            insn_branch_conds! {
+                mnemonic = $mnemonic_l;
+                asm_last_arg = $asm_last_arg;
+                imm = $imm;
+                encoding = $encoding | 1;
+                dest = MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_LR_REG_NUM], &[]);
+                src1 = $src1;
+                pc_relative = $pc_relative;
+                lk = true;
+                is_ret = $is_ret;
+            }
+        };
+        (
+            mnemonic = $mnemonic:literal;
+            asm_last_arg = $asm_last_arg:literal;
+            imm = $imm:literal;
+            encoding = $encoding:expr;
+            dest = $dest:expr;
+            src1 = $src1:expr;
+            pc_relative = $pc_relative:expr;
+            lk = $lk:expr;
+            is_ret = $is_ret:expr;
+        ) => {
+            if !$mnemonic.starts_with("bcctr") {
+                retval.push(insn_dec_ctr_and(
+                    concat!($mnemonic, " 0, 0, ", $asm_last_arg),
+                    $encoding,
+                    None,
+                    BranchMOp::branch_cond_ctr(
+                        $dest,
+                        [
+                            MOpRegNum::power_isa_cr_reg_imm(0).value,
+                            $src1,
+                            MOpRegNum::power_isa_ctr_reg().value,
+                        ],
+                        $imm.cast_to_static::<SInt<_>>(),
+                        true,
+                        ConditionMode.SLt(),
+                        true,
+                        $pc_relative,
+                        $lk,
+                        $is_ret,
+                    ),
+                ));
+                retval.push(insn_dec_ctr_and(
+                    concat!($mnemonic, " 0, 1, ", $asm_last_arg),
+                    $encoding | 0x010000,
+                    None,
+                    BranchMOp::branch_cond_ctr(
+                        $dest,
+                        [
+                            MOpRegNum::power_isa_cr_reg_imm(0).value,
+                            $src1,
+                            MOpRegNum::power_isa_ctr_reg().value,
+                        ],
+                        $imm.cast_to_static::<SInt<_>>(),
+                        true,
+                        ConditionMode.SGt(),
+                        true,
+                        $pc_relative,
+                        $lk,
+                        $is_ret,
+                    ),
+                ));
+                retval.push(insn_dec_ctr_and(
+                    concat!($mnemonic, " 0, 2, ", $asm_last_arg),
+                    $encoding | 0x020000,
+                    None,
+                    BranchMOp::branch_cond_ctr(
+                        $dest,
+                        [
+                            MOpRegNum::power_isa_cr_reg_imm(0).value,
+                            $src1,
+                            MOpRegNum::power_isa_ctr_reg().value,
+                        ],
+                        $imm.cast_to_static::<SInt<_>>(),
+                        true,
+                        ConditionMode.Eq(),
+                        true,
+                        $pc_relative,
+                        $lk,
+                        $is_ret,
+                    ),
+                ));
+                retval.push(insn_dec_ctr_and(
+                    concat!($mnemonic, " 0, 3, ", $asm_last_arg),
+                    $encoding | 0x030000,
+                    None,
+                    BranchMOp::branch_cond_ctr(
+                        $dest,
+                        [
+                            MOpRegNum::power_isa_cr_reg_imm(0).value,
+                            $src1,
+                            MOpRegNum::power_isa_ctr_reg().value,
+                        ],
+                        $imm.cast_to_static::<SInt<_>>(),
+                        true,
+                        ConditionMode.Overflow(),
+                        true,
+                        $pc_relative,
+                        $lk,
+                        $is_ret,
+                    ),
+                ));
+                retval.push(insn_dec_ctr_and(
+                    concat!($mnemonic, " 0, 9, ", $asm_last_arg),
+                    $encoding | 0x090000,
+                    None,
+                    BranchMOp::branch_cond_ctr(
+                        $dest,
+                        [
+                            MOpRegNum::power_isa_cr_reg_imm(2).value,
+                            $src1,
+                            MOpRegNum::power_isa_ctr_reg().value,
+                        ],
+                        $imm.cast_to_static::<SInt<_>>(),
+                        true,
+                        ConditionMode.SGt(),
+                        true,
+                        $pc_relative,
+                        $lk,
+                        $is_ret,
+                    ),
+                ));
+                retval.push(insn_dec_ctr_and(
+                    concat!($mnemonic, " 2, 0, ", $asm_last_arg),
+                    $encoding | (2 << 21),
+                    None,
+                    BranchMOp::branch_cond_ctr(
+                        $dest,
+                        [
+                            MOpRegNum::power_isa_cr_reg_imm(0).value,
+                            $src1,
+                            MOpRegNum::power_isa_ctr_reg().value,
+                        ],
+                        $imm.cast_to_static::<SInt<_>>(),
+                        true,
+                        ConditionMode.SLt(),
+                        false,
+                        $pc_relative,
+                        $lk,
+                        $is_ret,
+                    ),
+                ));
+            }
+            retval.push(insn_single(
+                concat!($mnemonic, " 4, 0, ", $asm_last_arg),
+                $encoding | (4 << 21),
+                None,
+                BranchMOp::branch_cond_ctr(
+                    $dest,
+                    [
+                        MOpRegNum::power_isa_cr_reg_imm(0).value,
+                        $src1,
+                        MOpRegNum::const_zero().value,
+                    ],
+                    $imm.cast_to_static::<SInt<_>>(),
+                    true,
+                    ConditionMode.SLt(),
+                    true,
+                    $pc_relative,
+                    $lk,
+                    $is_ret,
+                ),
+            ));
+            if !$mnemonic.starts_with("bcctr") {
+                retval.push(insn_dec_ctr_and(
+                    concat!($mnemonic, " 8, 0, ", $asm_last_arg),
+                    $encoding | (8 << 21),
+                    None,
+                    BranchMOp::branch_cond_ctr(
+                        $dest,
+                        [
+                            MOpRegNum::power_isa_cr_reg_imm(0).value,
+                            $src1,
+                            MOpRegNum::power_isa_ctr_reg().value,
+                        ],
+                        $imm.cast_to_static::<SInt<_>>(),
+                        false,
+                        ConditionMode.SLt(),
+                        true,
+                        $pc_relative,
+                        $lk,
+                        $is_ret,
+                    ),
+                ));
+                retval.push(insn_dec_ctr_and(
+                    concat!($mnemonic, " 10, 0, ", $asm_last_arg),
+                    $encoding | (10 << 21),
+                    None,
+                    BranchMOp::branch_cond_ctr(
+                        $dest,
+                        [
+                            MOpRegNum::power_isa_cr_reg_imm(0).value,
+                            $src1,
+                            MOpRegNum::power_isa_ctr_reg().value,
+                        ],
+                        $imm.cast_to_static::<SInt<_>>(),
+                        false,
+                        ConditionMode.SLt(),
+                        false,
+                        $pc_relative,
+                        $lk,
+                        $is_ret,
+                    ),
+                ));
+            }
+            retval.push(insn_single(
+                concat!($mnemonic, " 12, 0, ", $asm_last_arg),
+                $encoding | (12 << 21),
+                None,
+                BranchMOp::branch_cond_ctr(
+                    $dest,
+                    [
+                        MOpRegNum::power_isa_cr_reg_imm(0).value,
+                        $src1,
+                        MOpRegNum::const_zero().value,
+                    ],
+                    $imm.cast_to_static::<SInt<_>>(),
+                    false,
+                    ConditionMode.SLt(),
+                    true,
+                    $pc_relative,
+                    $lk,
+                    $is_ret,
+                ),
+            ));
+            if !$mnemonic.starts_with("bcctr") {
+                retval.push(insn_dec_ctr_and(
+                    concat!($mnemonic, " 16, 0, ", $asm_last_arg),
+                    $encoding | (16 << 21),
+                    None,
+                    BranchMOp::branch_ctr(
+                        $dest,
+                        $src1,
+                        MOpRegNum::power_isa_ctr_reg().value,
+                        $imm.cast_to_static::<SInt<_>>(),
+                        true,
+                        $pc_relative,
+                        $lk,
+                        $is_ret,
+                    ),
+                ));
+                retval.push(insn_dec_ctr_and(
+                    concat!($mnemonic, " 18, 0, ", $asm_last_arg),
+                    $encoding | (18 << 21),
+                    None,
+                    BranchMOp::branch_ctr(
+                        $dest,
+                        $src1,
+                        MOpRegNum::power_isa_ctr_reg().value,
+                        $imm.cast_to_static::<SInt<_>>(),
+                        false,
+                        $pc_relative,
+                        $lk,
+                        $is_ret,
+                    ),
+                ));
+            }
+            retval.push(insn_single(
+                concat!($mnemonic, " 20, 0, ", $asm_last_arg),
+                $encoding | (20 << 21),
+                None,
+                BranchMOp::branch_i(
+                    $dest,
+                    $src1,
+                    $imm.cast_to_static::<SInt<_>>(),
+                    $pc_relative,
+                    $lk,
+                    $is_ret,
+                ),
+            ));
+        };
+    }
+    insn_branch_conds! {
+        mnemonic = "bc";
+        mnemonic_l = "bcl";
+        asm_last_arg = "0x1234";
+        imm = 0x1234;
+        encoding = 0x40001234;
+        src1 = MOpRegNum::const_zero().value;
+        pc_relative = true;
+        is_ret = false;
+    }
+    insn_branch_conds! {
+        mnemonic = "bca";
+        mnemonic_l = "bcla";
+        asm_last_arg = "0x1234";
+        imm = 0x1234;
+        encoding = 0x40001236;
+        src1 = MOpRegNum::const_zero().value;
+        pc_relative = false;
+        is_ret = false;
+    }
+    insn_branch_conds! {
+        mnemonic = "bclr";
+        mnemonic_l = "bclrl";
+        asm_last_arg = "0";
+        imm = 0;
+        encoding = 0x4c000020;
+        src1 = MOpRegNum::power_isa_lr_reg().value;
+        pc_relative = false;
+        is_ret = true;
+    }
+    insn_branch_conds! {
+        mnemonic = "bcctr";
+        mnemonic_l = "bcctrl";
+        asm_last_arg = "0";
+        imm = 0;
+        encoding = 0x4c000420;
+        src1 = MOpRegNum::power_isa_ctr_reg().value;
+        pc_relative = false;
+        is_ret = false;
+    }
+    retval.push(insn_dec_ctr_and(
+        // LLVM doesn't support the bctar[l] instructions:
+        // https://github.com/llvm/llvm-project/issues/176864
+        ".long 0x4e400461 # bctarl 18, 0, 0",
+        0x4e400461,
+        None,
+        BranchMOp::branch_ctr(
+            MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_LR_REG_NUM], &[]),
+            MOpRegNum::power_isa_tar_reg().value,
+            MOpRegNum::power_isa_ctr_reg().value,
+            0.cast_to_static::<SInt<_>>(),
+            false,
+            false,
+            true,
+            false,
+        ),
+    ));
+}
--- a/crates/cpu/tests/simple_power_isa_decoder/test_cases/condition_register.rs
+++ b/crates/cpu/tests/simple_power_isa_decoder/test_cases/condition_register.rs
@ -0,0 +1,103 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+
+use crate::test_cases::{TestCase, insn_single};
+use cpu::{
+    instruction::{LogicalFlagsMOp, LogicalFlagsMOpImm, Lut4, MOpDestReg, MOpRegNum, MoveRegMOp},
+    register::PRegFlagsPowerISA,
+};
+use fayalite::prelude::*;
+
+/// covers instructions in PowerISA v3.1C Book I 2.5 Condition Register Instructions
+pub fn test_cases_book_i_2_5_condition_register(retval: &mut Vec<TestCase>) {
+    macro_rules! cr_bit_logical_op {
+        (
+            $mnemonic:literal,
+            $encoding:literal,
+            $lut:expr
+        ) => {{
+            retval.push(insn_single(
+                concat!($mnemonic, " 4*cr3+so, 4*cr1+gt, 4*cr5+lt"),
+                $encoding | 0x01e5a000,
+                None,
+                LogicalFlagsMOp::logical_flags(
+                    MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
+                    [
+                        MOpRegNum::power_isa_cr_reg_imm(1).value,
+                        MOpRegNum::power_isa_cr_reg_imm(5).value,
+                        MOpRegNum::power_isa_cr_reg_imm(3).value,
+                    ],
+                    LogicalFlagsMOpImm::from_swizzle_fn::<PRegFlagsPowerISA>(|src0, src1, src2| {
+                        let mut dest = src2.map(|v| Some(v.into()));
+                        dest.so = Some((src0.cr_gt, src1.cr_lt).into());
+                        dest
+                    }),
+                    $lut,
+                ),
+            ));
+            retval.push(insn_single(
+                concat!($mnemonic, " lt, gt, eq"),
+                $encoding | 0x00011000,
+                None,
+                LogicalFlagsMOp::logical_flags(
+                    MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(0)], &[]),
+                    [
+                        MOpRegNum::power_isa_cr_reg_imm(0).value,
+                        MOpRegNum::power_isa_cr_reg_imm(0).value,
+                        MOpRegNum::power_isa_cr_reg_imm(0).value,
+                    ],
+                    LogicalFlagsMOpImm::from_swizzle_fn::<PRegFlagsPowerISA>(|src0, src1, src2| {
+                        let mut dest = src2.map(|v| Some(v.into()));
+                        dest.cr_lt = Some((src0.cr_gt, src1.cr_eq).into());
+                        dest
+                    }),
+                    $lut,
+                ),
+            ));
+            retval.push(insn_single(
+                concat!($mnemonic, " gt, gt, eq"),
+                $encoding | 0x00211000,
+                None,
+                LogicalFlagsMOp::logical_flags(
+                    MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(0)], &[]),
+                    [
+                        MOpRegNum::power_isa_cr_reg_imm(0).value,
+                        MOpRegNum::power_isa_cr_reg_imm(0).value,
+                        MOpRegNum::power_isa_cr_reg_imm(0).value,
+                    ],
+                    LogicalFlagsMOpImm::from_swizzle_fn::<PRegFlagsPowerISA>(|src0, src1, src2| {
+                        let mut dest = src2.map(|v| Some(v.into()));
+                        dest.cr_gt = Some((src0.cr_gt, src1.cr_eq).into());
+                        dest
+                    }),
+                    $lut,
+                ),
+            ));
+        }};
+    }
+    cr_bit_logical_op!("crand", 0x4c000202, Lut4::from_fn(|a, b| a & b));
+    cr_bit_logical_op!("crnand", 0x4c0001c2, Lut4::from_fn(|a, b| !(a & b)));
+    cr_bit_logical_op!("cror", 0x4c000382, Lut4::from_fn(|a, b| a | b));
+    cr_bit_logical_op!("crxor", 0x4c000182, Lut4::from_fn(|a, b| a ^ b));
+    cr_bit_logical_op!("crnor", 0x4c000042, Lut4::from_fn(|a, b| !(a | b)));
+    cr_bit_logical_op!("creqv", 0x4c000242, Lut4::from_fn(|a, b| a == b));
+    cr_bit_logical_op!("crandc", 0x4c000102, Lut4::from_fn(|a, b| a & !b));
+    cr_bit_logical_op!("crorc", 0x4c000342, Lut4::from_fn(|a, b| a | !b));
+    macro_rules! mcrf {
+        ($dest:literal, $src:literal; $encoding:literal) => {
+            retval.push(insn_single(
+                concat!("mcrf ", $dest, ", ", $src),
+                $encoding,
+                None,
+                MoveRegMOp::move_reg(
+                    MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num($dest)], &[]),
+                    [MOpRegNum::power_isa_cr_reg_imm($src).value],
+                    0i8.cast_to_static::<SInt<_>>(),
+                ),
+            ));
+        };
+    }
+    mcrf!(0, 0; 0x4c000000);
+    mcrf!(5, 7; 0x4e9c0000);
+    mcrf!(5, 0; 0x4e800000);
+}
--- a/crates/cpu/tests/simple_power_isa_decoder/test_cases/fixed_point_arithmetic.rs
+++ b/crates/cpu/tests/simple_power_isa_decoder/test_cases/fixed_point_arithmetic.rs
@ -0,0 +1,408 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+
+use crate::test_cases::{TestCase, insn_single};
+use cpu::instruction::{AddSubMOp, MOpDestReg, MOpRegNum, OutputIntegerMode};
+use fayalite::prelude::*;
+
+/// covers instructions in PowerISA v3.1C Book I 3.3.9 Fixed-Point Arithmetic Instructions
+pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>) {
+    retval.push(insn_single(
+        "addi 3, 4, 0x1234",
+        0x38641234,
+        None,
+        AddSubMOp::add_sub_i(
+            MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
+            [
+                MOpRegNum::power_isa_gpr_reg_imm(4).value,
+                MOpRegNum::const_zero().value,
+            ],
+            0x1234.cast_to_static::<SInt<_>>(),
+            OutputIntegerMode.Full64(),
+            false,
+            false,
+            false,
+            false,
+        ),
+    ));
+    retval.push(insn_single(
+        "paddi 3, 4, 0x123456789, 0",
+        0x06012345,
+        Some(0x38646789),
+        AddSubMOp::add_sub_i(
+            MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
+            [
+                MOpRegNum::power_isa_gpr_reg_imm(4).value,
+                MOpRegNum::const_zero().value,
+            ],
+            0x123456789i64.cast_to_static::<SInt<_>>(),
+            OutputIntegerMode.Full64(),
+            false,
+            false,
+            false,
+            false,
+        ),
+    ));
+    retval.push(insn_single(
+        "paddi 3, 0, 0x123456789, 1",
+        0x06112345,
+        Some(0x38606789),
+        AddSubMOp::add_sub_i(
+            MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
+            [MOpRegNum::const_zero().value, MOpRegNum::const_zero().value],
+            0x123456789i64.cast_to_static::<SInt<_>>(),
+            OutputIntegerMode.Full64(),
+            false,
+            false,
+            false,
+            true,
+        ),
+    ));
+    retval.push(insn_single(
+        "addis 3, 4, 0x1234",
+        0x3C641234,
+        None,
+        AddSubMOp::add_sub_i(
+            MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
+            [
+                MOpRegNum::power_isa_gpr_reg_imm(4).value,
+                MOpRegNum::const_zero().value,
+            ],
+            0x12340000.cast_to_static::<SInt<_>>(),
+            OutputIntegerMode.Full64(),
+            false,
+            false,
+            false,
+            false,
+        ),
+    ));
+    retval.push(insn_single(
+        "addpcis 3, 0x1234",
+        0x4c7a1204,
+        None,
+        AddSubMOp::add_sub_i(
+            MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
+            [MOpRegNum::const_zero().value; _],
+            0x12340004.cast_to_static::<SInt<_>>(),
+            OutputIntegerMode.Full64(),
+            false,
+            false,
+            false,
+            true,
+        ),
+    ));
+    retval.push(insn_single(
+        "add. 3, 4, 5",
+        0x7c642a15,
+        None,
+        AddSubMOp::add_sub(
+            MOpDestReg::new_sim(
+                &[MOpRegNum::power_isa_gpr_reg_num(3)],
+                &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
+            ),
+            [
+                MOpRegNum::power_isa_gpr_reg_imm(4).value,
+                MOpRegNum::power_isa_gpr_reg_imm(5).value,
+                MOpRegNum::const_zero().value,
+            ],
+            0.cast_to_static::<SInt<_>>(),
+            OutputIntegerMode.Full64(),
+            false,
+            false,
+            false,
+            false,
+        ),
+    ));
+    retval.push(insn_single(
+        "addic. 3, 4, 0x1234",
+        0x34641234,
+        None,
+        AddSubMOp::add_sub_i(
+            MOpDestReg::new_sim(
+                &[
+                    MOpRegNum::power_isa_gpr_reg_num(3),
+                    MOpRegNum::POWER_ISA_XER_CA_CA32_REG_NUM,
+                ],
+                &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
+            ),
+            [
+                MOpRegNum::power_isa_gpr_reg_imm(4).value,
+                MOpRegNum::const_zero().value,
+            ],
+            0x1234.cast_to_static::<SInt<_>>(),
+            OutputIntegerMode.Full64(),
+            false,
+            false,
+            false,
+            false,
+        ),
+    ));
+    retval.push(insn_single(
+        "subf. 3, 4, 5",
+        0x7c642851,
+        None,
+        AddSubMOp::add_sub(
+            MOpDestReg::new_sim(
+                &[MOpRegNum::power_isa_gpr_reg_num(3)],
+                &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
+            ),
+            [
+                MOpRegNum::power_isa_gpr_reg_imm(4).value,
+                MOpRegNum::power_isa_gpr_reg_imm(5).value,
+                MOpRegNum::const_zero().value,
+            ],
+            0.cast_to_static::<SInt<_>>(),
+            OutputIntegerMode.Full64(),
+            true,
+            false,
+            true,
+            false,
+        ),
+    ));
+    retval.push(insn_single(
+        "subfic 3, 4, 0x1234",
+        0x20641234,
+        None,
+        AddSubMOp::add_sub_i(
+            MOpDestReg::new_sim(
+                &[
+                    MOpRegNum::power_isa_gpr_reg_num(3),
+                    MOpRegNum::POWER_ISA_XER_CA_CA32_REG_NUM,
+                ],
+                &[],
+            ),
+            [
+                MOpRegNum::power_isa_gpr_reg_imm(4).value,
+                MOpRegNum::const_zero().value,
+            ],
+            0x1234.cast_to_static::<SInt<_>>(),
+            OutputIntegerMode.Full64(),
+            true,
+            false,
+            true,
+            false,
+        ),
+    ));
+    retval.push(insn_single(
+        "addc. 3, 4, 5",
+        0x7c642815,
+        None,
+        AddSubMOp::add_sub(
+            MOpDestReg::new_sim(
+                &[
+                    MOpRegNum::power_isa_gpr_reg_num(3),
+                    MOpRegNum::POWER_ISA_XER_CA_CA32_REG_NUM,
+                ],
+                &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
+            ),
+            [
+                MOpRegNum::power_isa_gpr_reg_imm(4).value,
+                MOpRegNum::power_isa_gpr_reg_imm(5).value,
+                MOpRegNum::const_zero().value,
+            ],
+            0.cast_to_static::<SInt<_>>(),
+            OutputIntegerMode.Full64(),
+            false,
+            false,
+            false,
+            false,
+        ),
+    ));
+    retval.push(insn_single(
+        "subfc. 3, 4, 5",
+        0x7c642811,
+        None,
+        AddSubMOp::add_sub(
+            MOpDestReg::new_sim(
+                &[
+                    MOpRegNum::power_isa_gpr_reg_num(3),
+                    MOpRegNum::POWER_ISA_XER_CA_CA32_REG_NUM,
+                ],
+                &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
+            ),
+            [
+                MOpRegNum::power_isa_gpr_reg_imm(4).value,
+                MOpRegNum::power_isa_gpr_reg_imm(5).value,
+                MOpRegNum::const_zero().value,
+            ],
+            0.cast_to_static::<SInt<_>>(),
+            OutputIntegerMode.Full64(),
+            true,
+            false,
+            true,
+            false,
+        ),
+    ));
+    retval.push(insn_single(
+        "adde. 3, 4, 5",
+        0x7c642915,
+        None,
+        AddSubMOp::add_sub(
+            MOpDestReg::new_sim(
+                &[
+                    MOpRegNum::power_isa_gpr_reg_num(3),
+                    MOpRegNum::POWER_ISA_XER_CA_CA32_REG_NUM,
+                ],
+                &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
+            ),
+            [
+                MOpRegNum::power_isa_gpr_reg_imm(4).value,
+                MOpRegNum::power_isa_xer_ca_ca32_reg().value,
+                MOpRegNum::power_isa_gpr_reg_imm(5).value,
+            ],
+            0.cast_to_static::<SInt<_>>(),
+            OutputIntegerMode.Full64(),
+            false,
+            true,
+            false,
+            false,
+        ),
+    ));
+    retval.push(insn_single(
+        "subfe. 3, 4, 5",
+        0x7c642911,
+        None,
+        AddSubMOp::add_sub(
+            MOpDestReg::new_sim(
+                &[
+                    MOpRegNum::power_isa_gpr_reg_num(3),
+                    MOpRegNum::POWER_ISA_XER_CA_CA32_REG_NUM,
+                ],
+                &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
+            ),
+            [
+                MOpRegNum::power_isa_gpr_reg_imm(4).value,
+                MOpRegNum::power_isa_xer_ca_ca32_reg().value,
+                MOpRegNum::power_isa_gpr_reg_imm(5).value,
+            ],
+            0.cast_to_static::<SInt<_>>(),
+            OutputIntegerMode.Full64(),
+            true,
+            true,
+            false,
+            false,
+        ),
+    ));
+    retval.push(insn_single(
+        "addme. 3, 4",
+        0x7c6401d5,
+        None,
+        AddSubMOp::add_sub(
+            MOpDestReg::new_sim(
+                &[
+                    MOpRegNum::power_isa_gpr_reg_num(3),
+                    MOpRegNum::POWER_ISA_XER_CA_CA32_REG_NUM,
+                ],
+                &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
+            ),
+            [
+                MOpRegNum::power_isa_gpr_reg_imm(4).value,
+                MOpRegNum::power_isa_xer_ca_ca32_reg().value,
+                MOpRegNum::const_zero().value,
+            ],
+            (-1i8).cast_to_static::<SInt<_>>(),
+            OutputIntegerMode.Full64(),
+            false,
+            true,
+            false,
+            false,
+        ),
+    ));
+    retval.push(insn_single(
+        "subfme. 3, 4",
+        0x7c6401d1,
+        None,
+        AddSubMOp::add_sub(
+            MOpDestReg::new_sim(
+                &[
+                    MOpRegNum::power_isa_gpr_reg_num(3),
+                    MOpRegNum::POWER_ISA_XER_CA_CA32_REG_NUM,
+                ],
+                &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
+            ),
+            [
+                MOpRegNum::power_isa_gpr_reg_imm(4).value,
+                MOpRegNum::power_isa_xer_ca_ca32_reg().value,
+                MOpRegNum::const_zero().value,
+            ],
+            (-1i8).cast_to_static::<SInt<_>>(),
+            OutputIntegerMode.Full64(),
+            true,
+            true,
+            false,
+            false,
+        ),
+    ));
+    retval.push(insn_single(
+        "addze. 3, 4",
+        0x7c640195,
+        None,
+        AddSubMOp::add_sub(
+            MOpDestReg::new_sim(
+                &[
+                    MOpRegNum::power_isa_gpr_reg_num(3),
+                    MOpRegNum::POWER_ISA_XER_CA_CA32_REG_NUM,
+                ],
+                &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
+            ),
+            [
+                MOpRegNum::power_isa_gpr_reg_imm(4).value,
+                MOpRegNum::power_isa_xer_ca_ca32_reg().value,
+                MOpRegNum::const_zero().value,
+            ],
+            0.cast_to_static::<SInt<_>>(),
+            OutputIntegerMode.Full64(),
+            false,
+            true,
+            false,
+            false,
+        ),
+    ));
+    retval.push(insn_single(
+        "subfze. 3, 4",
+        0x7c640191,
+        None,
+        AddSubMOp::add_sub(
+            MOpDestReg::new_sim(
+                &[
+                    MOpRegNum::power_isa_gpr_reg_num(3),
+                    MOpRegNum::POWER_ISA_XER_CA_CA32_REG_NUM,
+                ],
+                &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
+            ),
+            [
+                MOpRegNum::power_isa_gpr_reg_imm(4).value,
+                MOpRegNum::power_isa_xer_ca_ca32_reg().value,
+                MOpRegNum::const_zero().value,
+            ],
+            0.cast_to_static::<SInt<_>>(),
+            OutputIntegerMode.Full64(),
+            true,
+            true,
+            false,
+            false,
+        ),
+    ));
+    retval.push(insn_single(
+        "neg. 3, 4",
+        0x7c6400d1,
+        None,
+        AddSubMOp::add_sub(
+            MOpDestReg::new_sim(
+                &[MOpRegNum::power_isa_gpr_reg_num(3)],
+                &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
+            ),
+            [
+                MOpRegNum::power_isa_gpr_reg_imm(4).value,
+                MOpRegNum::const_zero().value,
+                MOpRegNum::const_zero().value,
+            ],
+            0.cast_to_static::<SInt<_>>(),
+            OutputIntegerMode.Full64(),
+            true,
+            false,
+            true,
+            false,
+        ),
+    ));
+}
--- a/crates/cpu/tests/simple_power_isa_decoder/test_cases/fixed_point_compare.rs
+++ b/crates/cpu/tests/simple_power_isa_decoder/test_cases/fixed_point_compare.rs
@ -0,0 +1,163 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+
+use crate::test_cases::{TestCase, insn_single};
+use cpu::instruction::{CompareMOp, CompareMode, MOpDestReg, MOpRegNum, OutputIntegerMode};
+use fayalite::prelude::*;
+
+/// covers instructions in PowerISA v3.1C Book I 3.3.10 Fixed-Point Compare Instructions
+pub fn test_cases_book_i_3_3_10_fixed_point_compare(retval: &mut Vec<TestCase>) {
+    retval.push(insn_single(
+        "cmpi 3, 0, 4, 0x1234",
+        0x2d841234,
+        None,
+        CompareMOp::compare_i(
+            MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
+            [MOpRegNum::power_isa_gpr_reg_imm(4).value],
+            0x1234.cast_to_static::<SInt<_>>(),
+            OutputIntegerMode.Full64(),
+            CompareMode.S32(),
+        ),
+    ));
+    retval.push(insn_single(
+        "cmpi 3, 1, 4, -0x7655",
+        0x2da489ab,
+        None,
+        CompareMOp::compare_i(
+            MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
+            [MOpRegNum::power_isa_gpr_reg_imm(4).value],
+            (0x89abu16 as i16).cast_to_static::<SInt<_>>(),
+            OutputIntegerMode.Full64(),
+            CompareMode.S64(),
+        ),
+    ));
+    retval.push(insn_single(
+        "cmp 3, 0, 4, 5",
+        0x7d842800,
+        None,
+        CompareMOp::compare(
+            MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
+            [
+                MOpRegNum::power_isa_gpr_reg_imm(4).value,
+                MOpRegNum::power_isa_gpr_reg_imm(5).value,
+            ],
+            0.cast_to_static::<SInt<_>>(),
+            OutputIntegerMode.Full64(),
+            CompareMode.S32(),
+        ),
+    ));
+    retval.push(insn_single(
+        "cmp 3, 1, 4, 5",
+        0x7da42800,
+        None,
+        CompareMOp::compare(
+            MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
+            [
+                MOpRegNum::power_isa_gpr_reg_imm(4).value,
+                MOpRegNum::power_isa_gpr_reg_imm(5).value,
+            ],
+            0.cast_to_static::<SInt<_>>(),
+            OutputIntegerMode.Full64(),
+            CompareMode.S64(),
+        ),
+    ));
+    retval.push(insn_single(
+        "cmpli 3, 0, 4, 0x1234",
+        0x29841234,
+        None,
+        CompareMOp::compare_i(
+            MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
+            [MOpRegNum::power_isa_gpr_reg_imm(4).value],
+            0x1234.cast_to_static::<SInt<_>>(),
+            OutputIntegerMode.Full64(),
+            CompareMode.U32(),
+        ),
+    ));
+    retval.push(insn_single(
+        "cmpli 3, 1, 4, 0x89ab",
+        0x29a489ab,
+        None,
+        CompareMOp::compare_i(
+            MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
+            [MOpRegNum::power_isa_gpr_reg_imm(4).value],
+            0x89ab.cast_to_static::<SInt<_>>(),
+            OutputIntegerMode.Full64(),
+            CompareMode.U64(),
+        ),
+    ));
+    retval.push(insn_single(
+        "cmpl 3, 0, 4, 5",
+        0x7d842840,
+        None,
+        CompareMOp::compare(
+            MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
+            [
+                MOpRegNum::power_isa_gpr_reg_imm(4).value,
+                MOpRegNum::power_isa_gpr_reg_imm(5).value,
+            ],
+            0.cast_to_static::<SInt<_>>(),
+            OutputIntegerMode.Full64(),
+            CompareMode.U32(),
+        ),
+    ));
+    retval.push(insn_single(
+        "cmpl 3, 1, 4, 5",
+        0x7da42840,
+        None,
+        CompareMOp::compare(
+            MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
+            [
+                MOpRegNum::power_isa_gpr_reg_imm(4).value,
+                MOpRegNum::power_isa_gpr_reg_imm(5).value,
+            ],
+            0.cast_to_static::<SInt<_>>(),
+            OutputIntegerMode.Full64(),
+            CompareMode.U64(),
+        ),
+    ));
+    retval.push(insn_single(
+        "cmprb 3, 0, 4, 5",
+        0x7d842980,
+        None,
+        CompareMOp::compare(
+            MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
+            [
+                MOpRegNum::power_isa_gpr_reg_imm(4).value,
+                MOpRegNum::power_isa_gpr_reg_imm(5).value,
+            ],
+            0.cast_to_static::<SInt<_>>(),
+            OutputIntegerMode.Full64(),
+            CompareMode.CmpRBOne(),
+        ),
+    ));
+    retval.push(insn_single(
+        "cmprb 3, 1, 4, 5",
+        0x7da42980,
+        None,
+        CompareMOp::compare(
+            MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
+            [
+                MOpRegNum::power_isa_gpr_reg_imm(4).value,
+                MOpRegNum::power_isa_gpr_reg_imm(5).value,
+            ],
+            0.cast_to_static::<SInt<_>>(),
+            OutputIntegerMode.Full64(),
+            CompareMode.CmpRBTwo(),
+        ),
+    ));
+    retval.push(insn_single(
+        "cmpeqb 3, 4, 5",
+        0x7d8429c0,
+        None,
+        CompareMOp::compare(
+            MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
+            [
+                MOpRegNum::power_isa_gpr_reg_imm(4).value,
+                MOpRegNum::power_isa_gpr_reg_imm(5).value,
+            ],
+            0.cast_to_static::<SInt<_>>(),
+            OutputIntegerMode.Full64(),
+            CompareMode.CmpEqB(),
+        ),
+    ));
+}
--- a/crates/cpu/tests/simple_power_isa_decoder/test_cases/fixed_point_load.rs
+++ b/crates/cpu/tests/simple_power_isa_decoder/test_cases/fixed_point_load.rs
@ -0,0 +1,525 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+
+use crate::test_cases::{TestCase, insn_double};
+use cpu::instruction::{
+    AddSubMOp, LoadMOp, LoadStoreConversion, LoadStoreWidth, MOpDestReg, MOpRegNum,
+    OutputIntegerMode,
+};
+use fayalite::prelude::*;
+
+/// covers instructions in PowerISA v3.1C Book I 3.3.2 Fixed-Point Load Instructions
+pub fn test_cases_book_i_3_3_2_fixed_point_load(retval: &mut Vec<TestCase>) {
+    macro_rules! load_prefixed {
+        (
+            $mnemonic:literal $dest:literal, $disp:literal($ra:literal), $r:literal;
+            $prefix:literal, $suffix:literal;
+            $width:ident;
+            $conversion:ident;
+        ) => {
+            retval.push(insn_double(
+                concat!($mnemonic, " ", $dest, ", ", $disp, "(", $ra, "), ", $r),
+                $prefix,
+                Some($suffix),
+                [
+                    AddSubMOp::add_sub_i(
+                        MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]),
+                        [
+                            if $r != 0 || $ra == 0 {
+                                MOpRegNum::const_zero().value
+                            } else {
+                                MOpRegNum::power_isa_gpr_reg_imm($ra).value
+                            },
+                            MOpRegNum::const_zero().value,
+                        ],
+                        ($disp as i64).cast_to_static::<SInt<_>>(),
+                        OutputIntegerMode.Full64(),
+                        false,
+                        false,
+                        false,
+                        $r != 0,
+                    ),
+                    LoadMOp::load(
+                        MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]),
+                        [MOpRegNum::power_isa_temp_reg().value],
+                        LoadStoreWidth.$width(),
+                        LoadStoreConversion.$conversion(),
+                    ),
+                ],
+            ));
+        };
+    }
+    macro_rules! load {
+        (
+            $mnemonic:literal $dest:literal, $disp:literal($ra:literal);
+            $encoding:literal;
+            $width:ident;
+            $conversion:ident;
+        ) => {
+            retval.push(insn_double(
+                concat!($mnemonic, " ", $dest, ", ", $disp, "(", $ra, ")"),
+                $encoding,
+                None,
+                [
+                    AddSubMOp::add_sub_i(
+                        MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]),
+                        [
+                            if $ra == 0 {
+                                MOpRegNum::const_zero().value
+                            } else {
+                                MOpRegNum::power_isa_gpr_reg_imm($ra).value
+                            },
+                            MOpRegNum::const_zero().value,
+                        ],
+                        ($disp as i64).cast_to_static::<SInt<_>>(),
+                        OutputIntegerMode.Full64(),
+                        false,
+                        false,
+                        false,
+                        false,
+                    ),
+                    LoadMOp::load(
+                        MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]),
+                        [MOpRegNum::power_isa_temp_reg().value],
+                        LoadStoreWidth.$width(),
+                        LoadStoreConversion.$conversion(),
+                    ),
+                ],
+            ));
+        };
+    }
+    macro_rules! load_update {
+        (
+            $mnemonic:literal $dest:literal, $disp:literal($ra:literal);
+            $encoding:literal;
+            $width:ident;
+            $conversion:ident;
+        ) => {
+            retval.push(insn_double(
+                concat!($mnemonic, " ", $dest, ", ", $disp, "(", $ra, ")"),
+                $encoding,
+                None,
+                [
+                    AddSubMOp::add_sub_i(
+                        MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($ra)], &[]),
+                        [
+                            MOpRegNum::power_isa_gpr_reg_imm($ra).value,
+                            MOpRegNum::const_zero().value,
+                        ],
+                        ($disp as i64).cast_to_static::<SInt<_>>(),
+                        OutputIntegerMode.Full64(),
+                        false,
+                        false,
+                        false,
+                        false,
+                    ),
+                    LoadMOp::load(
+                        MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]),
+                        [MOpRegNum::power_isa_gpr_reg_imm($ra).value],
+                        LoadStoreWidth.$width(),
+                        LoadStoreConversion.$conversion(),
+                    ),
+                ],
+            ));
+        };
+    }
+    macro_rules! load_indexed {
+        (
+            $mnemonic:literal $dest:literal, $ra:literal, $rb:literal;
+            $encoding:literal;
+            $width:ident;
+            $conversion:ident;
+        ) => {
+            retval.push(insn_double(
+                concat!($mnemonic, " ", $dest, ", ", $ra, ", ", $rb),
+                $encoding,
+                None,
+                [
+                    AddSubMOp::add_sub_i(
+                        MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]),
+                        [
+                            if $ra == 0 {
+                                MOpRegNum::const_zero().value
+                            } else {
+                                MOpRegNum::power_isa_gpr_reg_imm($ra).value
+                            },
+                            MOpRegNum::power_isa_gpr_reg_imm($rb).value,
+                        ],
+                        0.cast_to_static::<SInt<_>>(),
+                        OutputIntegerMode.Full64(),
+                        false,
+                        false,
+                        false,
+                        false,
+                    ),
+                    LoadMOp::load(
+                        MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]),
+                        [MOpRegNum::power_isa_temp_reg().value],
+                        LoadStoreWidth.$width(),
+                        LoadStoreConversion.$conversion(),
+                    ),
+                ],
+            ));
+        };
+    }
+    macro_rules! load_update_indexed {
+        (
+            $mnemonic:literal $dest:literal, $ra:literal, $rb:literal;
+            $encoding:literal;
+            $width:ident;
+            $conversion:ident;
+        ) => {
+            retval.push(insn_double(
+                concat!($mnemonic, " ", $dest, ", ", $ra, ", ", $rb),
+                $encoding,
+                None,
+                [
+                    AddSubMOp::add_sub_i(
+                        MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($ra)], &[]),
+                        [
+                            MOpRegNum::power_isa_gpr_reg_imm($ra).value,
+                            MOpRegNum::power_isa_gpr_reg_imm($rb).value,
+                        ],
+                        0.cast_to_static::<SInt<_>>(),
+                        OutputIntegerMode.Full64(),
+                        false,
+                        false,
+                        false,
+                        false,
+                    ),
+                    LoadMOp::load(
+                        MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]),
+                        [MOpRegNum::power_isa_gpr_reg_imm($ra).value],
+                        LoadStoreWidth.$width(),
+                        LoadStoreConversion.$conversion(),
+                    ),
+                ],
+            ));
+        };
+    }
+
+    load! {
+        "lbz" 3, 0x1234(4);
+        0x88641234;
+        Width8Bit;
+        ZeroExt;
+    }
+    load! {
+        "lbz" 3, 0x1234(0);
+        0x88601234;
+        Width8Bit;
+        ZeroExt;
+    }
+    load_prefixed! {
+        "plbz" 3, 0x123456789(4), 0;
+        0x06012345, 0x88646789;
+        Width8Bit;
+        ZeroExt;
+    }
+    load_prefixed! {
+        "plbz" 3, 0x123456789(0), 0;
+        0x06012345, 0x88606789;
+        Width8Bit;
+        ZeroExt;
+    }
+    load_prefixed! {
+        "plbz" 3, 0x123456789(0), 1;
+        0x06112345, 0x88606789;
+        Width8Bit;
+        ZeroExt;
+    }
+    load_indexed! {
+        "lbzx" 3, 4, 5;
+        0x7c6428ae;
+        Width8Bit;
+        ZeroExt;
+    }
+    load_indexed! {
+        "lbzx" 3, 0, 5;
+        0x7c6028ae;
+        Width8Bit;
+        ZeroExt;
+    }
+    load_update! {
+        "lbzu" 3, 0x1234(4);
+        0x8c641234;
+        Width8Bit;
+        ZeroExt;
+    }
+    load_update_indexed! {
+        "lbzux" 3, 4, 5;
+        0x7c6428ee;
+        Width8Bit;
+        ZeroExt;
+    }
+
+    load! {
+        "lhz" 3, 0x1234(4);
+        0xa0641234;
+        Width16Bit;
+        ZeroExt;
+    }
+    load! {
+        "lhz" 3, 0x1234(0);
+        0xa0601234;
+        Width16Bit;
+        ZeroExt;
+    }
+    load_prefixed! {
+        "plhz" 3, 0x123456789(4), 0;
+        0x06012345, 0xa0646789;
+        Width16Bit;
+        ZeroExt;
+    }
+    load_prefixed! {
+        "plhz" 3, 0x123456789(0), 0;
+        0x06012345, 0xa0606789;
+        Width16Bit;
+        ZeroExt;
+    }
+    load_prefixed! {
+        "plhz" 3, 0x123456789(0), 1;
+        0x06112345, 0xa0606789;
+        Width16Bit;
+        ZeroExt;
+    }
+    load_indexed! {
+        "lhzx" 3, 4, 5;
+        0x7c642a2e;
+        Width16Bit;
+        ZeroExt;
+    }
+    load_indexed! {
+        "lhzx" 3, 0, 5;
+        0x7c602a2e;
+        Width16Bit;
+        ZeroExt;
+    }
+    load_update! {
+        "lhzu" 3, 0x1234(4);
+        0xa4641234;
+        Width16Bit;
+        ZeroExt;
+    }
+    load_update_indexed! {
+        "lhzux" 3, 4, 5;
+        0x7c642a6e;
+        Width16Bit;
+        ZeroExt;
+    }
+
+    load! {
+        "lha" 3, 0x1234(4);
+        0xa8641234;
+        Width16Bit;
+        SignExt;
+    }
+    load! {
+        "lha" 3, 0x1234(0);
+        0xa8601234;
+        Width16Bit;
+        SignExt;
+    }
+    load_prefixed! {
+        "plha" 3, 0x123456789(4), 0;
+        0x06012345, 0xa8646789;
+        Width16Bit;
+        SignExt;
+    }
+    load_prefixed! {
+        "plha" 3, 0x123456789(0), 0;
+        0x06012345, 0xa8606789;
+        Width16Bit;
+        SignExt;
+    }
+    load_prefixed! {
+        "plha" 3, 0x123456789(0), 1;
+        0x06112345, 0xa8606789;
+        Width16Bit;
+        SignExt;
+    }
+    load_indexed! {
+        "lhax" 3, 4, 5;
+        0x7c642aae;
+        Width16Bit;
+        SignExt;
+    }
+    load_indexed! {
+        "lhax" 3, 0, 5;
+        0x7c602aae;
+        Width16Bit;
+        SignExt;
+    }
+    load_update! {
+        "lhau" 3, 0x1234(4);
+        0xac641234;
+        Width16Bit;
+        SignExt;
+    }
+    load_update_indexed! {
+        "lhaux" 3, 4, 5;
+        0x7c642aee;
+        Width16Bit;
+        SignExt;
+    }
+
+    load! {
+        "lwz" 3, 0x1234(4);
+        0x80641234;
+        Width32Bit;
+        ZeroExt;
+    }
+    load! {
+        "lwz" 3, 0x1234(0);
+        0x80601234;
+        Width32Bit;
+        ZeroExt;
+    }
+    load_prefixed! {
+        "plwz" 3, 0x123456789(4), 0;
+        0x06012345, 0x80646789;
+        Width32Bit;
+        ZeroExt;
+    }
+    load_prefixed! {
+        "plwz" 3, 0x123456789(0), 0;
+        0x06012345, 0x80606789;
+        Width32Bit;
+        ZeroExt;
+    }
+    load_prefixed! {
+        "plwz" 3, 0x123456789(0), 1;
+        0x06112345, 0x80606789;
+        Width32Bit;
+        ZeroExt;
+    }
+    load_indexed! {
+        "lwzx" 3, 4, 5;
+        0x7c64282e;
+        Width32Bit;
+        ZeroExt;
+    }
+    load_indexed! {
+        "lwzx" 3, 0, 5;
+        0x7c60282e;
+        Width32Bit;
+        ZeroExt;
+    }
+    load_update! {
+        "lwzu" 3, 0x1234(4);
+        0x84641234;
+        Width32Bit;
+        ZeroExt;
+    }
+    load_update_indexed! {
+        "lwzux" 3, 4, 5;
+        0x7c64286e;
+        Width32Bit;
+        ZeroExt;
+    }
+
+    load! {
+        "lwa" 3, 0x1234(4);
+        0xe8641236;
+        Width32Bit;
+        SignExt;
+    }
+    load! {
+        "lwa" 3, 0x1234(0);
+        0xe8601236;
+        Width32Bit;
+        SignExt;
+    }
+    load_prefixed! {
+        "plwa" 3, 0x123456789(4), 0;
+        0x04012345, 0xa4646789;
+        Width32Bit;
+        SignExt;
+    }
+    load_prefixed! {
+        "plwa" 3, 0x123456789(0), 0;
+        0x04012345, 0xa4606789;
+        Width32Bit;
+        SignExt;
+    }
+    load_prefixed! {
+        "plwa" 3, 0x123456789(0), 1;
+        0x04112345, 0xa4606789;
+        Width32Bit;
+        SignExt;
+    }
+    load_indexed! {
+        "lwax" 3, 4, 5;
+        0x7c642aaa;
+        Width32Bit;
+        SignExt;
+    }
+    load_indexed! {
+        "lwax" 3, 0, 5;
+        0x7c602aaa;
+        Width32Bit;
+        SignExt;
+    }
+    // there is no `lwau`
+    load_update_indexed! {
+        "lwaux" 3, 4, 5;
+        0x7c642aea;
+        Width32Bit;
+        SignExt;
+    }
+
+    load! {
+        "ld" 3, 0x1234(4);
+        0xe8641234;
+        Width64Bit;
+        ZeroExt;
+    }
+    load! {
+        "ld" 3, 0x1234(0);
+        0xe8601234;
+        Width64Bit;
+        ZeroExt;
+    }
+    load_prefixed! {
+        "pld" 3, 0x123456789(4), 0;
+        0x04012345, 0xe4646789;
+        Width64Bit;
+        ZeroExt;
+    }
+    load_prefixed! {
+        "pld" 3, 0x123456789(0), 0;
+        0x04012345, 0xe4606789;
+        Width64Bit;
+        ZeroExt;
+    }
+    load_prefixed! {
+        "pld" 3, 0x123456789(0), 1;
+        0x04112345, 0xe4606789;
+        Width64Bit;
+        ZeroExt;
+    }
+    load_indexed! {
+        "ldx" 3, 4, 5;
+        0x7c64282a;
+        Width64Bit;
+        ZeroExt;
+    }
+    load_indexed! {
+        "ldx" 3, 0, 5;
+        0x7c60282a;
+        Width64Bit;
+        ZeroExt;
+    }
+    load_update! {
+        "ldu" 3, 0x1234(4);
+        0xe8641235;
+        Width64Bit;
+        ZeroExt;
+    }
+    load_update_indexed! {
+        "ldux" 3, 4, 5;
+        0x7c64286a;
+        Width64Bit;
+        ZeroExt;
+    }
+}
--- a/crates/cpu/tests/simple_power_isa_decoder/test_cases/fixed_point_logical.rs
+++ b/crates/cpu/tests/simple_power_isa_decoder/test_cases/fixed_point_logical.rs
@ -0,0 +1,273 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+
+use crate::test_cases::{TestCase, insn_empty, insn_single};
+use cpu::instruction::{LogicalMOp, Lut4, MOpDestReg, MOpRegNum, MoveRegMOp, OutputIntegerMode};
+use fayalite::prelude::*;
+
+/// covers instructions in PowerISA v3.1C Book I 3.3.13 Fixed-Point Logical Instructions
+pub fn test_cases_book_i_3_3_13_fixed_point_logical(retval: &mut Vec<TestCase>) {
+    macro_rules! insn_logic_i {
+        (
+            $mnemonic:literal $dest:literal, $src:literal, $imm:literal;
+            $encoding:literal;
+            |$a:ident, $b:ident| $lut_fn:expr;
+        ) => {
+            retval.push(insn_single(
+                concat!(
+                    $mnemonic,
+                    " ",
+                    stringify!($dest),
+                    ", ",
+                    stringify!($src),
+                    ", ",
+                    stringify!($imm)
+                ),
+                $encoding,
+                None,
+                LogicalMOp::logical_i(
+                    MOpDestReg::new_sim(
+                        &[MOpRegNum::power_isa_gpr_reg_num($dest)],
+                        if $mnemonic.contains('.') {
+                            &[MOpRegNum::POWER_ISA_CR_0_REG_NUM]
+                        } else {
+                            &[]
+                        },
+                    ),
+                    [MOpRegNum::power_isa_gpr_reg_imm($src).value],
+                    (($imm as u32) << if $mnemonic.contains('s') { 16 } else { 0 })
+                        .cast_to_static::<SInt<_>>(),
+                    OutputIntegerMode.Full64(),
+                    Lut4::from_fn(|$a, $b| $lut_fn),
+                ),
+            ));
+        };
+    }
+    insn_logic_i! {
+        "andi." 3, 4, 0x89ab;
+        0x708389ab;
+        |a, b| a & b;
+    }
+    insn_logic_i! {
+        "andis." 3, 4, 0x89ab;
+        0x748389ab;
+        |a, b| a & b;
+    }
+    insn_logic_i! {
+        "ori" 3, 4, 0x89ab;
+        0x608389ab;
+        |a, b| a | b;
+    }
+    // ensure nop decodes to zero instructions
+    retval.push(insn_empty("ori 0, 0, 0", 0x60000000, None));
+    insn_logic_i! {
+        "oris" 3, 4, 0x89ab;
+        0x648389ab;
+        |a, b| a | b;
+    }
+    insn_logic_i! {
+        "xori" 3, 4, 0x89ab;
+        0x688389ab;
+        |a, b| a ^ b;
+    }
+    insn_logic_i! {
+        "xori" 0, 0, 0; // ensure xnop actually decodes to a normal ALU instruction
+        0x68000000;
+        |a, b| a ^ b;
+    }
+    insn_logic_i! {
+        "xoris" 3, 4, 0x89ab;
+        0x6c8389ab;
+        |a, b| a ^ b;
+    }
+    macro_rules! insn_logic {
+        (
+            $mnemonic:literal $dest:literal, $src0:literal, $src1:literal;
+            $encoding:literal;
+            |$a:ident, $b:ident| $lut_fn:expr;
+        ) => {
+            retval.push(insn_single(
+                concat!(
+                    $mnemonic,
+                    " ",
+                    stringify!($dest),
+                    ", ",
+                    stringify!($src0),
+                    ", ",
+                    stringify!($src1)
+                ),
+                $encoding,
+                None,
+                LogicalMOp::logical(
+                    MOpDestReg::new_sim(
+                        &[MOpRegNum::power_isa_gpr_reg_num($dest)],
+                        if $mnemonic.contains('.') {
+                            &[MOpRegNum::POWER_ISA_CR_0_REG_NUM]
+                        } else {
+                            &[]
+                        },
+                    ),
+                    [
+                        MOpRegNum::power_isa_gpr_reg_imm($src0).value,
+                        MOpRegNum::power_isa_gpr_reg_imm($src1).value,
+                    ],
+                    0.cast_to_static::<SInt<_>>(),
+                    OutputIntegerMode.Full64(),
+                    Lut4::from_fn(|$a, $b| $lut_fn),
+                ),
+            ));
+        };
+    }
+    insn_logic! {
+        "and" 3, 4, 5;
+        0x7c832838;
+        |a, b| a & b;
+    }
+    insn_logic! {
+        "and." 3, 4, 5;
+        0x7c832839;
+        |a, b| a & b;
+    }
+    insn_logic! {
+        "xor" 3, 4, 5;
+        0x7c832a78;
+        |a, b| a ^ b;
+    }
+    insn_logic! {
+        "xor." 3, 4, 5;
+        0x7c832a79;
+        |a, b| a ^ b;
+    }
+    insn_logic! {
+        "nand" 3, 4, 5;
+        0x7c832bb8;
+        |a, b| !(a & b);
+    }
+    insn_logic! {
+        "nand." 3, 4, 5;
+        0x7c832bb9;
+        |a, b| !(a & b);
+    }
+    insn_logic! {
+        "or" 3, 4, 5;
+        0x7c832b78;
+        |a, b| a | b;
+    }
+    retval.push(insn_single(
+        "or 3, 4, 4", // mr 3, 4
+        0x7c832378,
+        None,
+        MoveRegMOp::move_reg(
+            MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
+            [MOpRegNum::power_isa_gpr_reg_imm(4).value],
+            0.cast_to_static::<SInt<_>>(),
+        ),
+    ));
+    insn_logic! {
+        "or." 3, 4, 5;
+        0x7c832b79;
+        |a, b| a | b;
+    }
+    insn_logic! {
+        "or." 3, 4, 4; // mr. 3, 4
+        0x7c832379;
+        |a, b| a | b;
+    }
+    insn_logic! {
+        "orc" 3, 4, 5;
+        0x7c832b38;
+        |a, b| a | !b;
+    }
+    insn_logic! {
+        "orc." 3, 4, 5;
+        0x7c832b39;
+        |a, b| a | !b;
+    }
+    insn_logic! {
+        "nor" 3, 4, 5;
+        0x7c8328f8;
+        |a, b| !(a | b);
+    }
+    insn_logic! {
+        "nor." 3, 4, 5;
+        0x7c8328f9;
+        |a, b| !(a | b);
+    }
+    insn_logic! {
+        "eqv" 3, 4, 5;
+        0x7c832a38;
+        |a, b| a == b;
+    }
+    insn_logic! {
+        "eqv." 3, 4, 5;
+        0x7c832a39;
+        |a, b| a == b;
+    }
+    insn_logic! {
+        "andc" 3, 4, 5;
+        0x7c832878;
+        |a, b| a & !b;
+    }
+    insn_logic! {
+        "andc." 3, 4, 5;
+        0x7c832879;
+        |a, b| a & !b;
+    }
+    macro_rules! insn_exts {
+        (
+            $mnemonic:literal $dest:literal, $src:literal;
+            $encoding:literal;
+            $OutputIntegerMode:ident;
+        ) => {
+            retval.push(insn_single(
+                concat!($mnemonic, " ", stringify!($dest), ", ", stringify!($src)),
+                $encoding,
+                None,
+                LogicalMOp::logical_i(
+                    MOpDestReg::new_sim(
+                        &[MOpRegNum::power_isa_gpr_reg_num($dest)],
+                        if $mnemonic.contains('.') {
+                            &[MOpRegNum::POWER_ISA_CR_0_REG_NUM]
+                        } else {
+                            &[]
+                        },
+                    ),
+                    [MOpRegNum::power_isa_gpr_reg_imm($src).value],
+                    0.cast_to_static::<SInt<_>>(),
+                    OutputIntegerMode.$OutputIntegerMode(),
+                    Lut4::from_fn(|a, b| a | b),
+                ),
+            ));
+        };
+    }
+    insn_exts! {
+        "extsb" 3, 4;
+        0x7c830774;
+        SignExt8;
+    }
+    insn_exts! {
+        "extsb." 3, 4;
+        0x7c830775;
+        SignExt8;
+    }
+    insn_exts! {
+        "extsh" 3, 4;
+        0x7c830734;
+        SignExt16;
+    }
+    insn_exts! {
+        "extsh." 3, 4;
+        0x7c830735;
+        SignExt16;
+    }
+    insn_exts! {
+        "extsw" 3, 4;
+        0x7c8307b4;
+        SignExt32;
+    }
+    insn_exts! {
+        "extsw." 3, 4;
+        0x7c8307b5;
+        SignExt32;
+    }
+}
--- a/crates/cpu/tests/simple_power_isa_decoder/test_cases/fixed_point_rotate_and_shift.rs
+++ b/crates/cpu/tests/simple_power_isa_decoder/test_cases/fixed_point_rotate_and_shift.rs
--- a/crates/cpu/tests/simple_power_isa_decoder/test_cases/fixed_point_store.rs
+++ b/crates/cpu/tests/simple_power_isa_decoder/test_cases/fixed_point_store.rs
@ -0,0 +1,512 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+
+use crate::test_cases::{TestCase, insn_double, insn_triple};
+use cpu::instruction::{
+    AddSubMOp, LoadStoreConversion, LoadStoreWidth, MOpDestReg, MOpRegNum, MoveRegMOp,
+    OutputIntegerMode, StoreMOp,
+};
+use fayalite::prelude::*;
+
+/// covers instructions in PowerISA v3.1C Book I 3.3.3 Fixed-Point Store Instructions
+pub fn test_cases_book_i_3_3_3_fixed_point_store(retval: &mut Vec<TestCase>) {
+    macro_rules! store_prefixed {
+        (
+            $mnemonic:literal $rs:literal, $disp:literal($ra:literal), $r:literal;
+            $prefix:literal, $suffix:literal;
+            $width:ident;
+        ) => {
+            retval.push(insn_double(
+                concat!($mnemonic, " ", $rs, ", ", $disp, "(", $ra, "), ", $r),
+                $prefix,
+                Some($suffix),
+                [
+                    AddSubMOp::add_sub_i(
+                        MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]),
+                        [
+                            if $r != 0 || $ra == 0 {
+                                MOpRegNum::const_zero().value
+                            } else {
+                                MOpRegNum::power_isa_gpr_reg_imm($ra).value
+                            },
+                            MOpRegNum::const_zero().value,
+                        ],
+                        ($disp as i64).cast_to_static::<SInt<_>>(),
+                        OutputIntegerMode.Full64(),
+                        false,
+                        false,
+                        false,
+                        $r != 0,
+                    ),
+                    StoreMOp::store(
+                        MOpDestReg::new_sim(&[], &[]),
+                        [
+                            MOpRegNum::power_isa_temp_reg().value,
+                            MOpRegNum::power_isa_gpr_reg_imm($rs).value,
+                        ],
+                        LoadStoreWidth.$width(),
+                        LoadStoreConversion.ZeroExt(),
+                    ),
+                ],
+            ));
+        };
+    }
+    macro_rules! store {
+        (
+            $mnemonic:literal $rs:literal, $disp:literal($ra:literal);
+            $encoding:literal;
+            $width:ident;
+        ) => {
+            retval.push(insn_double(
+                concat!($mnemonic, " ", $rs, ", ", $disp, "(", $ra, ")"),
+                $encoding,
+                None,
+                [
+                    AddSubMOp::add_sub_i(
+                        MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]),
+                        [
+                            if $ra == 0 {
+                                MOpRegNum::const_zero().value
+                            } else {
+                                MOpRegNum::power_isa_gpr_reg_imm($ra).value
+                            },
+                            MOpRegNum::const_zero().value,
+                        ],
+                        ($disp as i64).cast_to_static::<SInt<_>>(),
+                        OutputIntegerMode.Full64(),
+                        false,
+                        false,
+                        false,
+                        false,
+                    ),
+                    StoreMOp::store(
+                        MOpDestReg::new_sim(&[], &[]),
+                        [
+                            MOpRegNum::power_isa_temp_reg().value,
+                            MOpRegNum::power_isa_gpr_reg_imm($rs).value,
+                        ],
+                        LoadStoreWidth.$width(),
+                        LoadStoreConversion.ZeroExt(),
+                    ),
+                ],
+            ));
+        };
+    }
+    macro_rules! store_update {
+        (
+            $mnemonic:literal $rs:literal, $disp:literal($ra:literal);
+            $encoding:literal;
+            $width:ident;
+        ) => {
+            if $ra == $rs {
+                retval.push(insn_triple(
+                    concat!($mnemonic, " ", $rs, ", ", $disp, "(", $ra, ")"),
+                    $encoding,
+                    None,
+                    [
+                        AddSubMOp::add_sub_i(
+                            MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]),
+                            [
+                                MOpRegNum::power_isa_gpr_reg_imm($ra).value,
+                                MOpRegNum::const_zero().value,
+                            ],
+                            ($disp as i64).cast_to_static::<SInt<_>>(),
+                            OutputIntegerMode.Full64(),
+                            false,
+                            false,
+                            false,
+                            false,
+                        ),
+                        StoreMOp::store(
+                            MOpDestReg::new_sim(&[], &[]),
+                            [
+                                MOpRegNum::power_isa_temp_reg().value,
+                                MOpRegNum::power_isa_gpr_reg_imm($rs).value,
+                            ],
+                            LoadStoreWidth.$width(),
+                            LoadStoreConversion.ZeroExt(),
+                        ),
+                        MoveRegMOp::move_reg(
+                            MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($ra)], &[]),
+                            [MOpRegNum::power_isa_temp_reg().value],
+                            0.cast_to_static::<SInt<_>>(),
+                        ),
+                    ],
+                ));
+            } else {
+                retval.push(insn_double(
+                    concat!($mnemonic, " ", $rs, ", ", $disp, "(", $ra, ")"),
+                    $encoding,
+                    None,
+                    [
+                        AddSubMOp::add_sub_i(
+                            MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($ra)], &[]),
+                            [
+                                MOpRegNum::power_isa_gpr_reg_imm($ra).value,
+                                MOpRegNum::const_zero().value,
+                            ],
+                            ($disp as i64).cast_to_static::<SInt<_>>(),
+                            OutputIntegerMode.Full64(),
+                            false,
+                            false,
+                            false,
+                            false,
+                        ),
+                        StoreMOp::store(
+                            MOpDestReg::new_sim(&[], &[]),
+                            [
+                                MOpRegNum::power_isa_gpr_reg_imm($ra).value,
+                                MOpRegNum::power_isa_gpr_reg_imm($rs).value,
+                            ],
+                            LoadStoreWidth.$width(),
+                            LoadStoreConversion.ZeroExt(),
+                        ),
+                    ],
+                ));
+            }
+        };
+    }
+    macro_rules! store_indexed {
+        (
+            $mnemonic:literal $rs:literal, $ra:literal, $rb:literal;
+            $encoding:literal;
+            $width:ident;
+        ) => {
+            retval.push(insn_double(
+                concat!($mnemonic, " ", $rs, ", ", $ra, ", ", $rb),
+                $encoding,
+                None,
+                [
+                    AddSubMOp::add_sub_i(
+                        MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]),
+                        [
+                            if $ra == 0 {
+                                MOpRegNum::const_zero().value
+                            } else {
+                                MOpRegNum::power_isa_gpr_reg_imm($ra).value
+                            },
+                            MOpRegNum::power_isa_gpr_reg_imm($rb).value,
+                        ],
+                        0.cast_to_static::<SInt<_>>(),
+                        OutputIntegerMode.Full64(),
+                        false,
+                        false,
+                        false,
+                        false,
+                    ),
+                    StoreMOp::store(
+                        MOpDestReg::new_sim(&[], &[]),
+                        [
+                            MOpRegNum::power_isa_temp_reg().value,
+                            MOpRegNum::power_isa_gpr_reg_imm($rs).value,
+                        ],
+                        LoadStoreWidth.$width(),
+                        LoadStoreConversion.ZeroExt(),
+                    ),
+                ],
+            ));
+        };
+    }
+    macro_rules! store_update_indexed {
+        (
+            $mnemonic:literal $rs:literal, $ra:literal, $rb:literal;
+            $encoding:literal;
+            $width:ident;
+        ) => {
+            if $ra == $rs {
+                retval.push(insn_triple(
+                    concat!($mnemonic, " ", $rs, ", ", $ra, ", ", $rb),
+                    $encoding,
+                    None,
+                    [
+                        AddSubMOp::add_sub_i(
+                            MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]),
+                            [
+                                MOpRegNum::power_isa_gpr_reg_imm($ra).value,
+                                MOpRegNum::power_isa_gpr_reg_imm($rb).value,
+                            ],
+                            0.cast_to_static::<SInt<_>>(),
+                            OutputIntegerMode.Full64(),
+                            false,
+                            false,
+                            false,
+                            false,
+                        ),
+                        StoreMOp::store(
+                            MOpDestReg::new_sim(&[], &[]),
+                            [
+                                MOpRegNum::power_isa_temp_reg().value,
+                                MOpRegNum::power_isa_gpr_reg_imm($rs).value,
+                            ],
+                            LoadStoreWidth.$width(),
+                            LoadStoreConversion.ZeroExt(),
+                        ),
+                        MoveRegMOp::move_reg(
+                            MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($ra)], &[]),
+                            [MOpRegNum::power_isa_temp_reg().value],
+                            0.cast_to_static::<SInt<_>>(),
+                        ),
+                    ],
+                ));
+            } else {
+                retval.push(insn_double(
+                    concat!($mnemonic, " ", $rs, ", ", $ra, ", ", $rb),
+                    $encoding,
+                    None,
+                    [
+                        AddSubMOp::add_sub_i(
+                            MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($ra)], &[]),
+                            [
+                                if $ra == 0 {
+                                    MOpRegNum::const_zero().value
+                                } else {
+                                    MOpRegNum::power_isa_gpr_reg_imm($ra).value
+                                },
+                                MOpRegNum::power_isa_gpr_reg_imm($rb).value,
+                            ],
+                            0.cast_to_static::<SInt<_>>(),
+                            OutputIntegerMode.Full64(),
+                            false,
+                            false,
+                            false,
+                            false,
+                        ),
+                        StoreMOp::store(
+                            MOpDestReg::new_sim(&[], &[]),
+                            [
+                                MOpRegNum::power_isa_gpr_reg_imm($ra).value,
+                                MOpRegNum::power_isa_gpr_reg_imm($rs).value,
+                            ],
+                            LoadStoreWidth.$width(),
+                            LoadStoreConversion.ZeroExt(),
+                        ),
+                    ],
+                ));
+            }
+        };
+    }
+
+    store! {
+        "stb" 3, 0x1234(4);
+        0x98641234;
+        Width8Bit;
+    }
+    store! {
+        "stb" 3, 0x1234(0);
+        0x98601234;
+        Width8Bit;
+    }
+    store_prefixed! {
+        "pstb" 3, 0x123456789(4), 0;
+        0x06012345, 0x98646789;
+        Width8Bit;
+    }
+    store_prefixed! {
+        "pstb" 3, 0x123456789(0), 0;
+        0x06012345, 0x98606789;
+        Width8Bit;
+    }
+    store_prefixed! {
+        "pstb" 3, 0x123456789(0), 1;
+        0x06112345, 0x98606789;
+        Width8Bit;
+    }
+    store_indexed! {
+        "stbx" 3, 4, 5;
+        0x7c6429ae;
+        Width8Bit;
+    }
+    store_indexed! {
+        "stbx" 3, 0, 5;
+        0x7c6029ae;
+        Width8Bit;
+    }
+    store_update! {
+        "stbu" 3, 0x1234(4);
+        0x9c641234;
+        Width8Bit;
+    }
+    store_update! {
+        "stbu" 3, 0x1234(3);
+        0x9c631234;
+        Width8Bit;
+    }
+    store_update_indexed! {
+        "stbux" 3, 4, 5;
+        0x7c6429ee;
+        Width8Bit;
+    }
+    store_update_indexed! {
+        "stbux" 3, 3, 5;
+        0x7c6329ee;
+        Width8Bit;
+    }
+
+    store! {
+        "sth" 3, 0x1234(4);
+        0xb0641234;
+        Width16Bit;
+    }
+    store! {
+        "sth" 3, 0x1234(0);
+        0xb0601234;
+        Width16Bit;
+    }
+    store_prefixed! {
+        "psth" 3, 0x123456789(4), 0;
+        0x06012345, 0xb0646789;
+        Width16Bit;
+    }
+    store_prefixed! {
+        "psth" 3, 0x123456789(0), 0;
+        0x06012345, 0xb0606789;
+        Width16Bit;
+    }
+    store_prefixed! {
+        "psth" 3, 0x123456789(0), 1;
+        0x06112345, 0xb0606789;
+        Width16Bit;
+    }
+    store_indexed! {
+        "sthx" 3, 4, 5;
+        0x7c642b2e;
+        Width16Bit;
+    }
+    store_indexed! {
+        "sthx" 3, 0, 5;
+        0x7c602b2e;
+        Width16Bit;
+    }
+    store_update! {
+        "sthu" 3, 0x1234(4);
+        0xb4641234;
+        Width16Bit;
+    }
+    store_update! {
+        "sthu" 3, 0x1234(3);
+        0xb4631234;
+        Width16Bit;
+    }
+    store_update_indexed! {
+        "sthux" 3, 4, 5;
+        0x7c642b6e;
+        Width16Bit;
+    }
+    store_update_indexed! {
+        "sthux" 3, 3, 5;
+        0x7c632b6e;
+        Width16Bit;
+    }
+
+    store! {
+        "stw" 3, 0x1234(4);
+        0x90641234;
+        Width32Bit;
+    }
+    store! {
+        "stw" 3, 0x1234(0);
+        0x90601234;
+        Width32Bit;
+    }
+    store_prefixed! {
+        "pstw" 3, 0x123456789(4), 0;
+        0x06012345, 0x90646789;
+        Width32Bit;
+    }
+    store_prefixed! {
+        "pstw" 3, 0x123456789(0), 0;
+        0x06012345, 0x90606789;
+        Width32Bit;
+    }
+    store_prefixed! {
+        "pstw" 3, 0x123456789(0), 1;
+        0x06112345, 0x90606789;
+        Width32Bit;
+    }
+    store_indexed! {
+        "stwx" 3, 4, 5;
+        0x7c64292e;
+        Width32Bit;
+    }
+    store_indexed! {
+        "stwx" 3, 0, 5;
+        0x7c60292e;
+        Width32Bit;
+    }
+    store_update! {
+        "stwu" 3, 0x1234(4);
+        0x94641234;
+        Width32Bit;
+    }
+    store_update! {
+        "stwu" 3, 0x1234(3);
+        0x94631234;
+        Width32Bit;
+    }
+    store_update_indexed! {
+        "stwux" 3, 4, 5;
+        0x7c64296e;
+        Width32Bit;
+    }
+    store_update_indexed! {
+        "stwux" 3, 3, 5;
+        0x7c63296e;
+        Width32Bit;
+    }
+
+    store! {
+        "std" 3, 0x1234(4);
+        0xf8641234;
+        Width64Bit;
+    }
+    store! {
+        "std" 3, 0x1234(0);
+        0xf8601234;
+        Width64Bit;
+    }
+    store_prefixed! {
+        "pstd" 3, 0x123456789(4), 0;
+        0x04012345, 0xf4646789;
+        Width64Bit;
+    }
+    store_prefixed! {
+        "pstd" 3, 0x123456789(0), 0;
+        0x04012345, 0xf4606789;
+        Width64Bit;
+    }
+    store_prefixed! {
+        "pstd" 3, 0x123456789(0), 1;
+        0x04112345, 0xf4606789;
+        Width64Bit;
+    }
+    store_indexed! {
+        "stdx" 3, 4, 5;
+        0x7c64292a;
+        Width64Bit;
+    }
+    store_indexed! {
+        "stdx" 3, 0, 5;
+        0x7c60292a;
+        Width64Bit;
+    }
+    store_update! {
+        "stdu" 3, 0x1234(4);
+        0xf8641235;
+        Width64Bit;
+    }
+    store_update! {
+        "stdu" 3, 0x1234(3);
+        0xf8631235;
+        Width64Bit;
+    }
+    store_update_indexed! {
+        "stdux" 3, 4, 5;
+        0x7c64296a;
+        Width64Bit;
+    }
+    store_update_indexed! {
+        "stdux" 3, 3, 5;
+        0x7c63296a;
+        Width64Bit;
+    }
+}
--- a/crates/cpu/tests/simple_power_isa_decoder/test_cases/move_to_from_system_register.rs
+++ b/crates/cpu/tests/simple_power_isa_decoder/test_cases/move_to_from_system_register.rs
@ -0,0 +1,149 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+
+use crate::test_cases::{TestCase, insn_single};
+use cpu::instruction::{
+    LogicalFlagsMOp, LogicalFlagsMOpImm, Lut4, MOpDestReg, MOpRegNum, MoveRegMOp, ReadSpecialMOp,
+    ReadSpecialMOpImm,
+};
+use fayalite::prelude::*;
+
+/// covers instructions in PowerISA v3.1C Book I 3.3.19 Move To/From System Register Instructions
+pub fn test_cases_book_i_3_3_19_move_to_from_system_register(retval: &mut Vec<TestCase>) {
+    // mfspr/mtspr are covered by test_cases_book_iii_5_4_4_move_to_from_system_register
+    #[hdl]
+    fn mcrxrx_imm() -> SimValue<LogicalFlagsMOpImm> {
+        #[hdl(sim)]
+        LogicalFlagsMOpImm {
+            // if the order of flags in PRegFlags changes, this will need to be updated
+            src0_start: 4usize.cast_to(LogicalFlagsMOpImm.src0_start),
+            src1_start: 4usize.cast_to(LogicalFlagsMOpImm.src1_start),
+            src2_start: 4usize.cast_to(LogicalFlagsMOpImm.src2_start),
+            dest_start: 0usize.cast_to(LogicalFlagsMOpImm.dest_start),
+            dest_count: 6usize.cast_to(LogicalFlagsMOpImm.dest_count),
+        }
+    }
+    retval.push(insn_single(
+        "mcrxrx 3",
+        0x7d800480,
+        None,
+        LogicalFlagsMOp::logical_flags(
+            MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
+            [
+                MOpRegNum::power_isa_xer_ca_ca32_reg().value,
+                MOpRegNum::const_zero().value,
+                MOpRegNum::power_isa_xer_so_ov_ov32_reg().value,
+            ],
+            mcrxrx_imm(),
+            Lut4::from_fn(|a, b| a | b),
+        ),
+    ));
+}
+
+/// covers instructions in PowerISA v3.1C Book III 5.4.4 Move To/From System Register Instructions
+pub fn test_cases_book_iii_5_4_4_move_to_from_system_register(retval: &mut Vec<TestCase>) {
+    retval.push(insn_single(
+        "mflr 3",
+        0x7c6802a6,
+        None,
+        MoveRegMOp::move_reg(
+            MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
+            [MOpRegNum::power_isa_lr_reg().value],
+            0.cast_to_static::<SInt<_>>(),
+        ),
+    ));
+    retval.push(insn_single(
+        "mtlr 3",
+        0x7c6803a6,
+        None,
+        MoveRegMOp::move_reg(
+            MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_LR_REG_NUM], &[]),
+            [MOpRegNum::power_isa_gpr_reg_imm(3).value],
+            0.cast_to_static::<SInt<_>>(),
+        ),
+    ));
+    retval.push(insn_single(
+        "mfctr 3",
+        0x7c6902a6,
+        None,
+        MoveRegMOp::move_reg(
+            MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
+            [MOpRegNum::power_isa_ctr_reg().value],
+            0.cast_to_static::<SInt<_>>(),
+        ),
+    ));
+    retval.push(insn_single(
+        "mtctr 3",
+        0x7c6903a6,
+        None,
+        MoveRegMOp::move_reg(
+            MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_CTR_REG_NUM], &[]),
+            [MOpRegNum::power_isa_gpr_reg_imm(3).value],
+            0.cast_to_static::<SInt<_>>(),
+        ),
+    ));
+    retval.push(insn_single(
+        "mfspr 3, 815 # mftar 3",
+        0x7c6fcaa6,
+        None,
+        MoveRegMOp::move_reg(
+            MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
+            [MOpRegNum::power_isa_tar_reg().value],
+            0.cast_to_static::<SInt<_>>(),
+        ),
+    ));
+    retval.push(insn_single(
+        "mtspr 815, 3 # mttar 3",
+        0x7c6fcba6,
+        None,
+        MoveRegMOp::move_reg(
+            MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TAR_REG_NUM], &[]),
+            [MOpRegNum::power_isa_gpr_reg_imm(3).value],
+            0.cast_to_static::<SInt<_>>(),
+        ),
+    ));
+    // make sure we generate mfspr and not the phased-out mftb
+    retval.push(insn_single(
+        "mfspr 3, 268 # mftb 3",
+        0x7c6c42a6,
+        None,
+        ReadSpecialMOp::read_special(
+            MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
+            [MOpRegNum::const_zero().value; 0],
+            ReadSpecialMOpImm.PowerIsaTimeBase(),
+        ),
+    ));
+    // make sure we generate mfspr and not the phased-out mftb
+    retval.push(insn_single(
+        "mfspr 3, 269 # mftbu 3",
+        0x7c6d42a6,
+        None,
+        ReadSpecialMOp::read_special(
+            MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
+            [MOpRegNum::const_zero().value; 0],
+            ReadSpecialMOpImm.PowerIsaTimeBaseU(),
+        ),
+    ));
+    // phased-out mftb -- not actually generated by the assembler so we have to use .long
+    retval.push(insn_single(
+        ".long 0x7c6c42e6 # mftb 3, 268",
+        0x7c6c42e6,
+        None,
+        ReadSpecialMOp::read_special(
+            MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
+            [MOpRegNum::const_zero().value; 0],
+            ReadSpecialMOpImm.PowerIsaTimeBase(),
+        ),
+    ));
+    // phased-out mftb -- not actually generated by the assembler so we have to use .long
+    retval.push(insn_single(
+        ".long 0x7c6d42e6 # mftb 3, 269",
+        0x7c6d42e6,
+        None,
+        ReadSpecialMOp::read_special(
+            MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
+            [MOpRegNum::const_zero().value; 0],
+            ReadSpecialMOpImm.PowerIsaTimeBaseU(),
+        ),
+    ));
+}
--- a/crates/cpu/tests/simple_power_isa_decoder/test_cases/prefixed_no_operation.rs
+++ b/crates/cpu/tests/simple_power_isa_decoder/test_cases/prefixed_no_operation.rs
@ -0,0 +1,16 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+
+use crate::test_cases::{TestCase, insn_empty};
+
+/// covers instructions in PowerISA v3.1C Book I 3.3.20 Prefixed No-Operation Instruction
+pub fn test_cases_book_i_3_3_20_prefixed_no_operation(retval: &mut Vec<TestCase>) {
+    // ensure pnop decodes to zero instructions
+    retval.push(insn_empty(
+        // LLVM doesn't support the pnop instruction:
+        // https://github.com/llvm/llvm-project/issues/176831
+        ".long 0x07000000, 0 # pnop",
+        0x07000000,
+        Some(0),
+    ));
+}
--- a/crates/cpu/tests/simple_uart.rs
+++ b/crates/cpu/tests/simple_uart.rs
@ -0,0 +1,958 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+
+use cpu::{
+    config::{CpuConfig, UnitConfig},
+    main_memory_and_io::{
+        MemoryInterface, MemoryOperationErrorKind, MemoryOperationFinish,
+        MemoryOperationFinishKind, MemoryOperationKind, MemoryOperationStart,
+        simple_uart::{
+            ReceiverQueueStatus, SIMPLE_UART_RECEIVE_OFFSET, SIMPLE_UART_SIZE,
+            SIMPLE_UART_STATUS_OFFSET, SIMPLE_UART_TRANSMIT_OFFSET, receiver, receiver_no_queue,
+            simple_uart, transmitter, uart_clock_gen,
+        },
+    },
+    next_pc::FETCH_BLOCK_ID_WIDTH,
+    unit::UnitKind,
+    util::array_vec::ArrayVec,
+};
+use fayalite::{
+    bundle::BundleType,
+    intern::{Intern, Interned},
+    prelude::*,
+    sim::vcd::VcdWriterDecls,
+    util::{RcWriter, ready_valid::ReadyValid},
+};
+use std::{borrow::BorrowMut, marker::PhantomData, num::NonZeroUsize};
+
+const fn half_period(frequency: f64) -> SimDuration {
+    SimDuration::from_attos((SimDuration::from_secs(1).as_attos() as f64 / frequency / 2.0) as u128)
+}
+
+const CLOCK_FREQUENCY: f64 = 200_000.0;
+const CLOCK_HALF_PERIOD: SimDuration = half_period(CLOCK_FREQUENCY);
+const BAUD_RATE: f64 = 9600.0;
+const BAUD_HALF_PERIOD: SimDuration = half_period(BAUD_RATE);
+const BAUD_PERIOD: SimDuration = BAUD_HALF_PERIOD.saturating_add(BAUD_HALF_PERIOD);
+
+const fn baud_period_slow_percentage(percent: i128) -> SimDuration {
+    let v = BAUD_PERIOD.as_attos();
+    let v = v.strict_add_signed(v as i128 * percent / 100);
+    SimDuration::from_attos(v)
+}
+
+/// 3% slow BAUD_PERIOD
+const BAUD_PERIOD_SLOW: SimDuration = baud_period_slow_percentage(3);
+/// 3% fast BAUD_PERIOD
+const BAUD_PERIOD_FAST: SimDuration = baud_period_slow_percentage(-3);
+
+const _: () = {
+    assert!(BAUD_HALF_PERIOD.as_attos() < BAUD_PERIOD_FAST.as_attos());
+    assert!(BAUD_PERIOD_FAST.as_attos() < BAUD_PERIOD.as_attos());
+    assert!(BAUD_PERIOD.as_attos() < BAUD_PERIOD_SLOW.as_attos());
+};
+
+fn clock_input_properties() -> PhantomConst<peripherals::ClockInputProperties> {
+    peripherals::ClockInput::new(CLOCK_FREQUENCY).properties
+}
+
+#[hdl_module(extern)]
+fn reference_baud_rate_clk_gen() {
+    #[hdl]
+    let reference_baud_rate_clk: Clock = m.output();
+    m.extern_module_simulation_fn(
+        reference_baud_rate_clk,
+        async |reference_baud_rate_clk, mut sim| {
+            loop {
+                sim.write_clock(reference_baud_rate_clk, false).await;
+                sim.advance_time(BAUD_HALF_PERIOD).await;
+                sim.write_clock(reference_baud_rate_clk, true).await;
+                sim.advance_time(BAUD_HALF_PERIOD).await;
+            }
+        },
+    );
+}
+
+#[hdl_module(extern)]
+fn sim_receiver() {
+    #[hdl]
+    let tx: Bool = m.input();
+    #[hdl]
+    let text_out: SimOnly<String> = m.output();
+    m.extern_module_simulation_fn((tx, text_out), async |(tx, text_out), mut sim| {
+        let mut text = SimOnlyValue::new(String::new());
+        sim.write(text_out, &text).await;
+        loop {
+            // wait for the starting edge of the start bit
+            while sim.read_bool(tx).await {
+                sim.wait_for_changes([tx], None).await;
+            }
+            // wait till the middle of the start bit
+            sim.advance_time(BAUD_HALF_PERIOD).await;
+            let mut byte = 0u8;
+            for i in 0..u8::BITS {
+                // wait till the middle of the next data bit
+                sim.advance_time(BAUD_PERIOD).await;
+                if sim.read_bool(tx).await {
+                    byte |= 1 << i;
+                }
+            }
+            assert!(byte.is_ascii());
+            text.push(byte as char);
+            sim.write(text_out, &text).await;
+            // wait till the middle of the stop bit
+            sim.advance_time(BAUD_PERIOD).await;
+            // we're in the middle of the stop bit, the stop bit is a one so we can just loop and wait for
+            // the next transition to zero which is the next start bit.
+        }
+    });
+}
+
+#[hdl_module]
+fn transmitter_and_uart_clock_gen() {
+    #[hdl]
+    let cd: ClockDomain = m.input();
+    #[hdl]
+    let tx: Bool = m.output();
+    #[hdl]
+    let input_byte: ReadyValid<UInt<8>> = m.input();
+    #[hdl]
+    let reference_baud_rate_clk: Clock = m.output();
+    #[hdl]
+    let text_out: SimOnly<String> = m.output();
+
+    #[hdl]
+    let sim_receiver = instance(sim_receiver());
+    connect(sim_receiver.tx, tx);
+    connect(text_out, sim_receiver.text_out);
+
+    #[hdl]
+    let reference_baud_rate_clk_gen = instance(reference_baud_rate_clk_gen());
+    connect(
+        reference_baud_rate_clk,
+        reference_baud_rate_clk_gen.reference_baud_rate_clk,
+    );
+
+    #[hdl]
+    let transmitter = instance(transmitter());
+    connect(transmitter.cd, cd);
+    connect(transmitter.input_byte, input_byte);
+    connect(tx, transmitter.tx);
+    #[hdl]
+    let clock_gen = instance(uart_clock_gen(clock_input_properties(), BAUD_RATE));
+    connect(clock_gen.cd, cd);
+    connect(transmitter.tick, clock_gen.tick);
+}
+
+#[test]
+#[hdl]
+fn test_transmitter_and_uart_clock_gen() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let m = transmitter_and_uart_clock_gen();
+    let mut sim = Simulation::new(m);
+    let writer = RcWriter::default();
+    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
+    struct DumpVcdOnDrop {
+        writer: Option<RcWriter>,
+    }
+    impl Drop for DumpVcdOnDrop {
+        fn drop(&mut self) {
+            if let Some(mut writer) = self.writer.take() {
+                let vcd = String::from_utf8(writer.take()).unwrap();
+                println!("####### VCD:\n{vcd}\n#######");
+            }
+        }
+    }
+    let mut writer = DumpVcdOnDrop {
+        writer: Some(writer),
+    };
+    sim.write_clock(sim.io().cd.clk, false);
+    sim.write_reset(sim.io().cd.rst, true);
+    let text = "Hi!\n";
+    let mut bytes = text.as_bytes().iter();
+    for cycle in 0..1000 {
+        let input_byte = match bytes.clone().next() {
+            Some(b) if cycle > 10 =>
+            {
+                #[hdl(sim)]
+                HdlSome(b)
+            }
+            _ =>
+            {
+                #[hdl(sim)]
+                HdlNone()
+            }
+        };
+        sim.write(sim.io().input_byte.data, &input_byte);
+        sim.advance_time(CLOCK_HALF_PERIOD);
+        sim.write_clock(sim.io().cd.clk, true);
+        sim.advance_time(CLOCK_HALF_PERIOD);
+        if sim.read_bool(sim.io().input_byte.ready) {
+            #[hdl(sim)]
+            if let HdlSome(_) = input_byte {
+                bytes.next();
+            }
+        }
+        sim.write_clock(sim.io().cd.clk, false);
+        sim.write_reset(sim.io().cd.rst, false);
+    }
+    assert_eq!(sim.read(sim.io().text_out).as_str(), text);
+    assert!(bytes.as_slice().is_empty());
+    let vcd = String::from_utf8(writer.writer.take().unwrap().take()).unwrap();
+    println!("####### VCD:\n{vcd}\n#######");
+    if vcd != include_str!("expected/transmitter_and_uart_clock_gen.vcd") {
+        panic!();
+    }
+}
+
+#[hdl_module(extern)]
+fn receiver_no_queue_test_cases(text: Interned<str>) {
+    #[hdl]
+    let rx: Bool = m.output();
+    #[hdl]
+    let cur_byte: UInt<8> = m.output();
+    m.extern_module_simulation_fn(
+        (rx, cur_byte, text),
+        async |(rx, cur_byte, text), mut sim| {
+            // ensure the receiver can properly handle slightly fast or slow baud rates
+            let baud_periods = [
+                BAUD_PERIOD_FAST,
+                BAUD_PERIOD_FAST,
+                BAUD_PERIOD_FAST,
+                BAUD_PERIOD_FAST,
+                BAUD_PERIOD,
+                BAUD_PERIOD,
+                BAUD_PERIOD,
+                BAUD_PERIOD,
+                BAUD_PERIOD_SLOW,
+                BAUD_PERIOD_SLOW,
+                BAUD_PERIOD_SLOW,
+                BAUD_PERIOD_SLOW,
+            ]
+            .iter()
+            .copied()
+            .cycle();
+            sim.write(rx, true).await;
+            sim.write(cur_byte, 0u8).await;
+            // allow time for reset and stuff
+            sim.advance_time(SimDuration::from_micros(100)).await;
+            for (byte, baud_period) in text.bytes().cycle().zip(baud_periods) {
+                sim.write(cur_byte, byte).await;
+                sim.write(rx, false).await; // start bit
+                sim.advance_time(baud_period).await;
+                for i in 0..u8::BITS {
+                    sim.write(rx, byte & (1 << i) != 0).await; // data bit
+                    sim.advance_time(baud_period).await;
+                }
+                sim.write(rx, true).await; // stop bit
+                sim.advance_time(baud_period).await;
+            }
+        },
+    );
+}
+
+#[hdl_module]
+fn receiver_no_queue_and_uart_clock_gen(text: Interned<str>) {
+    #[hdl]
+    let cd: ClockDomain = m.input();
+    #[hdl]
+    let rx: Bool = m.output();
+    #[hdl]
+    let output_byte: HdlOption<UInt<8>> = m.output();
+    #[hdl]
+    let cur_byte: UInt<8> = m.output();
+    #[hdl]
+    let reference_baud_rate_clk: Clock = m.output();
+
+    #[hdl]
+    let test_cases = instance(receiver_no_queue_test_cases(text));
+    connect(rx, test_cases.rx);
+    connect(cur_byte, test_cases.cur_byte);
+
+    #[hdl]
+    let reference_baud_rate_clk_gen = instance(reference_baud_rate_clk_gen());
+    connect(
+        reference_baud_rate_clk,
+        reference_baud_rate_clk_gen.reference_baud_rate_clk,
+    );
+
+    // only need one stage of synchronization in the simulator
+    #[hdl]
+    let rx_synchronized = reg_builder().clock_domain(cd).reset(true);
+
+    connect(rx_synchronized, rx);
+
+    #[hdl]
+    let receiver = instance(receiver_no_queue());
+    connect(receiver.cd, cd);
+    connect(receiver.rx_synchronized, rx_synchronized);
+    connect(output_byte, receiver.output_byte);
+    #[hdl]
+    let clock_gen = instance(uart_clock_gen(clock_input_properties(), BAUD_RATE));
+    connect(clock_gen.cd, cd);
+    connect(receiver.tick, clock_gen.tick);
+}
+
+#[test]
+#[hdl]
+fn test_receiver_no_queue_and_uart_clock_gen() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let text = "Testing 123, testing, testing.\n".intern();
+    let m = receiver_no_queue_and_uart_clock_gen(text);
+    let mut sim = Simulation::new(m);
+    let writer = RcWriter::default();
+    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
+    struct DumpVcdOnDrop {
+        writer: Option<RcWriter>,
+    }
+    impl Drop for DumpVcdOnDrop {
+        fn drop(&mut self) {
+            if let Some(mut writer) = self.writer.take() {
+                let vcd = String::from_utf8(writer.take()).unwrap();
+                println!("####### VCD:\n{vcd}\n#######");
+            }
+        }
+    }
+    let mut writer = DumpVcdOnDrop {
+        writer: Some(writer),
+    };
+    sim.write_clock(sim.io().cd.clk, false);
+    sim.write_reset(sim.io().cd.rst, true);
+    let mut received_text = String::new();
+    for _cycle in 0..10000 {
+        sim.advance_time(CLOCK_HALF_PERIOD);
+        sim.write_clock(sim.io().cd.clk, true);
+        sim.advance_time(CLOCK_HALF_PERIOD);
+        sim.write_clock(sim.io().cd.clk, false);
+        sim.write_reset(sim.io().cd.rst, false);
+        #[hdl(sim)]
+        if let HdlSome(byte) = sim.read(sim.io().output_byte) {
+            let byte = byte.as_int();
+            let expected_byte = sim.read(sim.io().cur_byte).as_int();
+            assert_eq!(
+                byte, expected_byte,
+                "byte={:#x} {:?}, expected_byte={:#x} {:?}",
+                byte, byte as char, expected_byte, expected_byte as char,
+            );
+            assert!(byte.is_ascii());
+            received_text.push(byte as char);
+        }
+    }
+    println!("{received_text:?}");
+    assert!(received_text.len() >= text.len());
+    let mut expected_text = text.repeat(received_text.len().div_ceil(text.len()));
+    expected_text.truncate(received_text.len());
+    assert_eq!(received_text, expected_text);
+    let vcd = String::from_utf8(writer.writer.take().unwrap().take()).unwrap();
+    println!("####### VCD:\n{vcd}\n#######");
+    if vcd != include_str!("expected/receiver_no_queue_and_uart_clock_gen.vcd") {
+        panic!();
+    }
+}
+
+#[hdl_module(extern)]
+fn receiver_test_cases() {
+    #[hdl]
+    let clk: Clock = m.input();
+    #[hdl]
+    let rx: Bool = m.output();
+    #[hdl]
+    let cur_byte: UInt<8> = m.output();
+    #[hdl]
+    let ready: Bool = m.output();
+    #[hdl]
+    let text: SimOnly<String> = m.input();
+    m.register_clock_for_past(clk);
+    m.extern_module_simulation_fn(
+        (clk, rx, cur_byte, ready, text),
+        async |(clk, rx, cur_byte, ready, text), mut sim| {
+            sim.write(rx, true).await;
+            sim.write(ready, false).await;
+            loop {
+                sim.write(cur_byte, 0u8).await;
+                sim.wait_for_clock_edge(clk).await;
+                sim.write(ready, true).await;
+                let text = loop {
+                    sim.wait_for_clock_edge(clk).await;
+                    let text = sim.read_past(text, clk).await;
+                    if text.is_empty() {
+                        continue;
+                    }
+                    break text;
+                };
+                sim.write(ready, false).await;
+                sim.wait_for_clock_edge(clk).await;
+                for byte in text.bytes() {
+                    sim.write(cur_byte, byte).await;
+                    sim.write(rx, false).await; // start bit
+                    sim.advance_time(BAUD_PERIOD).await;
+                    for i in 0..u8::BITS {
+                        sim.write(rx, byte & (1 << i) != 0).await; // data bit
+                        sim.advance_time(BAUD_PERIOD).await;
+                    }
+                    sim.write(rx, true).await; // stop bit
+                    sim.advance_time(BAUD_PERIOD).await;
+                }
+            }
+        },
+    );
+}
+
+#[hdl_module]
+fn receiver_and_uart_clock_gen(queue_capacity: NonZeroUsize) {
+    #[hdl]
+    let cd: ClockDomain = m.input();
+    #[hdl]
+    let rx: Bool = m.output();
+    #[hdl]
+    let reference_baud_rate_clk: Clock = m.output();
+    #[hdl]
+    let cur_byte: UInt<8> = m.output();
+    #[hdl]
+    let ready: Bool = m.output();
+    #[hdl]
+    let text: SimOnly<String> = m.input();
+    #[hdl]
+    let output_byte: ReadyValid<UInt<8>> = m.output();
+    #[hdl]
+    let queue_status: ReceiverQueueStatus = m.output();
+
+    #[hdl]
+    let test_cases = instance(receiver_test_cases());
+    connect(test_cases.clk, cd.clk);
+    connect(rx, test_cases.rx);
+    connect(cur_byte, test_cases.cur_byte);
+    connect(ready, test_cases.ready);
+    connect(test_cases.text, text);
+
+    #[hdl]
+    let reference_baud_rate_clk_gen = instance(reference_baud_rate_clk_gen());
+    connect(
+        reference_baud_rate_clk,
+        reference_baud_rate_clk_gen.reference_baud_rate_clk,
+    );
+
+    // only need one stage of synchronization in the simulator
+    #[hdl]
+    let rx_synchronized = reg_builder().clock_domain(cd).reset(true);
+
+    connect(rx_synchronized, rx);
+
+    #[hdl]
+    let receiver = instance(receiver(queue_capacity));
+    connect(receiver.cd, cd);
+    connect(receiver.rx_synchronized, rx_synchronized);
+    connect(output_byte, receiver.output_byte);
+    connect(queue_status, receiver.queue_status);
+    #[hdl]
+    let clock_gen = instance(uart_clock_gen(clock_input_properties(), BAUD_RATE));
+    connect(clock_gen.cd, cd);
+    connect(receiver.tick, clock_gen.tick);
+}
+
+#[test]
+#[hdl]
+fn test_receiver_and_uart_clock_gen() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    const QUEUE_SIZE: NonZeroUsize = NonZeroUsize::new(4).expect("not zero");
+    let m = receiver_and_uart_clock_gen(QUEUE_SIZE);
+    let mut sim = Simulation::new(m);
+    let writer = RcWriter::default();
+    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
+    struct DumpVcdOnDrop {
+        writer: Option<RcWriter>,
+    }
+    impl Drop for DumpVcdOnDrop {
+        fn drop(&mut self) {
+            if let Some(mut writer) = self.writer.take() {
+                let vcd = String::from_utf8(writer.take()).unwrap();
+                println!("####### VCD:\n{vcd}\n#######");
+            }
+        }
+    }
+    let mut writer = DumpVcdOnDrop {
+        writer: Some(writer),
+    };
+    sim.write_clock(sim.io().cd.clk, false);
+    sim.write_reset(sim.io().cd.rst, true);
+    let empty_text = SimOnlyValue::new(String::new());
+    sim.write(sim.io().text, &empty_text);
+    sim.write_bool(sim.io().output_byte.ready, false);
+    sim.advance_time(CLOCK_HALF_PERIOD);
+    sim.write_clock(sim.io().cd.clk, true);
+    sim.advance_time(CLOCK_HALF_PERIOD);
+    sim.write_clock(sim.io().cd.clk, false);
+    sim.write_reset(sim.io().cd.rst, false);
+    const TEST_TEXT: &str = "Test\n";
+    const { assert!(TEST_TEXT.len() > QUEUE_SIZE.get()) }
+    for bytes_before_dequeue in 0..=TEST_TEXT.len() {
+        println!("\nbytes_before_dequeue={bytes_before_dequeue}");
+        for _cycle in 0..10 {
+            if sim.read_bool(sim.io().ready) {
+                break;
+            }
+            sim.advance_time(CLOCK_HALF_PERIOD);
+            sim.write_clock(sim.io().cd.clk, true);
+            sim.advance_time(CLOCK_HALF_PERIOD);
+            sim.write_clock(sim.io().cd.clk, false);
+        }
+        assert!(sim.read_bool(sim.io().ready));
+        let text = SimOnlyValue::new(TEST_TEXT[..bytes_before_dequeue].to_string());
+        dbg!(&text);
+        sim.write(sim.io().text, &text);
+        sim.advance_time(CLOCK_HALF_PERIOD);
+        sim.write_clock(sim.io().cd.clk, true);
+        sim.advance_time(CLOCK_HALF_PERIOD);
+        sim.write_clock(sim.io().cd.clk, false);
+        sim.write(sim.io().text, &empty_text);
+        for _cycle in 0..2000 {
+            if sim.read_bool(sim.io().ready) {
+                break;
+            }
+            sim.advance_time(CLOCK_HALF_PERIOD);
+            sim.write_clock(sim.io().cd.clk, true);
+            sim.advance_time(CLOCK_HALF_PERIOD);
+            sim.write_clock(sim.io().cd.clk, false);
+        }
+        assert!(sim.read_bool(sim.io().ready));
+        for _cycle in 0..10 {
+            sim.advance_time(CLOCK_HALF_PERIOD);
+            sim.write_clock(sim.io().cd.clk, true);
+            sim.advance_time(CLOCK_HALF_PERIOD);
+            sim.write_clock(sim.io().cd.clk, false);
+        }
+        dbg!(bytes_before_dequeue);
+        #[hdl(sim)]
+        match dbg!(sim.read(sim.io().queue_status)) {
+            ReceiverQueueStatus::QueueEmpty => {
+                assert_eq!(bytes_before_dequeue, 0);
+            }
+            ReceiverQueueStatus::QueueNotEmpty => {
+                assert!(bytes_before_dequeue > 0 && bytes_before_dequeue < QUEUE_SIZE.get() - 1);
+            }
+            ReceiverQueueStatus::QueueAlmostFull => {
+                assert_eq!(bytes_before_dequeue, QUEUE_SIZE.get() - 1);
+            }
+            ReceiverQueueStatus::QueueFull => {
+                assert_eq!(bytes_before_dequeue, QUEUE_SIZE.get());
+            }
+            ReceiverQueueStatus::QueueOverflowed => {
+                assert!(bytes_before_dequeue > QUEUE_SIZE.get());
+            }
+            ReceiverQueueStatus::Unknown => unreachable!(),
+        }
+        let expected_text = &TEST_TEXT[..bytes_before_dequeue.min(QUEUE_SIZE.get())];
+        dbg!(expected_text);
+        let mut received_text = String::new();
+        for expected_byte in expected_text.bytes() {
+            sim.write_bool(sim.io().output_byte.ready, true);
+            #[hdl(sim)]
+            if let HdlSome(byte) = sim.read(sim.io().output_byte.data) {
+                let byte = byte.as_int();
+                assert_eq!(
+                    byte, expected_byte,
+                    "byte={:#x} {:?}, expected_byte={:#x} {:?}",
+                    byte, byte as char, expected_byte, expected_byte as char,
+                );
+                assert!(byte.is_ascii());
+                received_text.push(byte as char);
+            } else {
+                break;
+            }
+            sim.advance_time(CLOCK_HALF_PERIOD);
+            sim.write_clock(sim.io().cd.clk, true);
+            sim.advance_time(CLOCK_HALF_PERIOD);
+            sim.write_clock(sim.io().cd.clk, false);
+        }
+        #[hdl(sim)]
+        if let HdlSome(_) = sim.read(sim.io().output_byte.data) {
+            panic!("queue should be empty now");
+        }
+        sim.write_bool(sim.io().output_byte.ready, false);
+    }
+    let vcd = String::from_utf8(writer.writer.take().unwrap().take()).unwrap();
+    println!("####### VCD:\n{vcd}\n#######");
+    if vcd != include_str!("expected/receiver_and_uart_clock_gen.vcd") {
+        panic!();
+    }
+}
+
+#[hdl_module]
+fn simple_uart_loopback(
+    config: PhantomConst<CpuConfig>,
+    clock_input_properties: PhantomConst<peripherals::ClockInputProperties>,
+    baud_rate: f64,
+    receiver_queue_size: NonZeroUsize,
+) {
+    #[hdl]
+    let cd: ClockDomain = m.input();
+    #[hdl]
+    let memory_interface: MemoryInterface<PhantomConst<CpuConfig>> =
+        m.input(MemoryInterface[config]);
+    #[hdl]
+    let tx: Bool = m.output();
+    #[hdl]
+    let inner = instance(simple_uart(
+        config,
+        clock_input_properties,
+        baud_rate,
+        receiver_queue_size,
+    ));
+    connect(inner.cd, cd);
+    connect(inner.memory_interface, memory_interface);
+    connect(tx, inner.uart.tx);
+    connect(inner.uart.rx, inner.uart.tx);
+}
+
+struct MemoryOperationRunner<Sim: BorrowMut<Simulation<T>>, T: BundleType> {
+    sim: Sim,
+    clk: Expr<Clock>,
+    memory_interface: Expr<MemoryInterface<PhantomConst<CpuConfig>>>,
+    next_fetch_block_id: u64,
+    _phantom: PhantomData<T>,
+}
+
+const FETCH_WIDTH_IN_BYTES: usize = 1 << CpuConfig::DEFAULT_LOG2_FETCH_WIDTH_IN_BYTES;
+
+impl<Sim: BorrowMut<Simulation<T>>, T: BundleType> MemoryOperationRunner<Sim, T> {
+    #[hdl]
+    fn run_memory_operation(
+        &mut self,
+        kind: impl ToSimValue<Type = MemoryOperationKind>,
+        addr: u64,
+        write_data: [u8; FETCH_WIDTH_IN_BYTES],
+        rw_mask: [bool; FETCH_WIDTH_IN_BYTES],
+        timeout_cycles: usize,
+    ) -> Result<[u8; FETCH_WIDTH_IN_BYTES], SimValue<MemoryOperationErrorKind>> {
+        let kind = kind.into_sim_value();
+        assert_eq!(addr % FETCH_WIDTH_IN_BYTES as u64, 0);
+        let config = self.memory_interface.ty().config;
+        let fetch_block_id = self
+            .next_fetch_block_id
+            .cast_to_static::<UInt<{ FETCH_BLOCK_ID_WIDTH }>>();
+        self.next_fetch_block_id += 1;
+        println!(
+            "started: MemoryOperationStart {{\n    \
+            kind: {kind:?},\n    \
+            addr: {addr:#x},\n    \
+            write_data: {write_data:?},\n    \
+            rw_mask: {rw_mask:?},\n    \
+            fetch_block_id: {fetch_block_id},\n\
+            }}"
+        );
+        let start_value = #[hdl(sim)]
+        MemoryOperationStart::<_> {
+            kind,
+            addr,
+            write_data: &write_data[..],
+            rw_mask: &rw_mask[..],
+            fetch_block_id,
+            config,
+        };
+        #[hdl]
+        let MemoryInterface::<_> {
+            start,
+            finish,
+            next_fetch_block_ids,
+            config: _,
+        } = self.memory_interface;
+        let sim = self.sim.borrow_mut();
+        let check_io = |sim: &mut Simulation<T>,
+                        expected_start_ready: bool,
+                        expected_finish_data_is_some: bool,
+                        expected_next_fetch_block_ids: &[_]| {
+            assert_eq!(sim.read_bool(start.ready), expected_start_ready);
+            let finish_data = sim.read(finish.data);
+            let finish_data_is_some = #[hdl(sim)]
+            if let HdlSome(_) = &finish_data {
+                true
+            } else {
+                false
+            };
+            assert_eq!(
+                finish_data_is_some, expected_finish_data_is_some,
+                "finish.data: {finish_data:?}"
+            );
+
+            #[hdl(sim)]
+            if let HdlSome(next_fetch_block_ids) = sim.read(next_fetch_block_ids) {
+                let next_fetch_block_ids: Vec<_> =
+                    ArrayVec::elements_sim_ref(&next_fetch_block_ids)
+                        .iter()
+                        .map(|v| v.as_int())
+                        .collect();
+                assert_eq!(next_fetch_block_ids, expected_next_fetch_block_ids);
+            } else {
+                panic!("next_fetch_block_ids should be HdlSome");
+            }
+        };
+        check_io(sim, true, false, &[]);
+        sim.write(
+            start.data,
+            #[hdl(sim)]
+            (start.ty().data).HdlSome(&start_value),
+        );
+        sim.write(finish.ready, true);
+        sim.advance_time(CLOCK_HALF_PERIOD);
+        sim.write_clock(self.clk, true);
+        sim.advance_time(CLOCK_HALF_PERIOD);
+        sim.write_clock(self.clk, false);
+        sim.write(
+            start.data,
+            #[hdl(sim)]
+            (start.ty().data).HdlNone(),
+        );
+        check_io(sim, false, false, &[start_value.fetch_block_id.as_int()]);
+        for _ in 0..timeout_cycles {
+            sim.advance_time(CLOCK_HALF_PERIOD);
+            sim.write_clock(self.clk, true);
+            sim.advance_time(CLOCK_HALF_PERIOD);
+            sim.write_clock(self.clk, false);
+            #[hdl(sim)]
+            if let HdlSome(finish_data) = sim.read(finish.data) {
+                #[hdl(sim)]
+                let MemoryOperationFinish::<_> {
+                    kind,
+                    read_data,
+                    config: _,
+                } = finish_data;
+                assert_eq!(read_data.len(), FETCH_WIDTH_IN_BYTES);
+                let read_data = std::array::from_fn(|i| read_data[i].as_int());
+                println!(
+                    "finished: MemoryOperationFinish {{\n    \
+                    kind: {kind:?},\n    \
+                    read_data: {read_data:?},\n\
+                    }}"
+                );
+                check_io(sim, false, true, &[start_value.fetch_block_id.as_int()]);
+                sim.advance_time(CLOCK_HALF_PERIOD);
+                sim.write_clock(self.clk, true);
+                sim.advance_time(CLOCK_HALF_PERIOD);
+                sim.write_clock(self.clk, false);
+                sim.write(finish.ready, false);
+                check_io(sim, true, false, &[]);
+                return #[hdl(sim)]
+                match kind {
+                    MemoryOperationFinishKind::Success(kind) => {
+                        assert_eq!(
+                            SimValue::bits(&kind),
+                            SimValue::bits(&start_value.kind),
+                            "finish_data.kind={kind:?}",
+                        );
+                        Ok(read_data)
+                    }
+                    MemoryOperationFinishKind::Error(error) => Err(error),
+                };
+            }
+            check_io(sim, false, false, &[start_value.fetch_block_id.as_int()]);
+        }
+        panic!("memory operation took too long");
+    }
+    #[hdl]
+    fn rw_bytes(
+        &mut self,
+        start_addr: u64,
+        is_read: bool,
+        bytes: &mut [u8],
+        timeout_cycles: usize,
+    ) -> Result<(), SimValue<MemoryOperationErrorKind>> {
+        let offset_in_chunk = start_addr as usize % FETCH_WIDTH_IN_BYTES;
+        let masked_addr = start_addr - offset_in_chunk as u64;
+        assert!(
+            offset_in_chunk
+                .checked_add(bytes.len())
+                .is_some_and(|v| v <= FETCH_WIDTH_IN_BYTES)
+        );
+        let bytes_range = offset_in_chunk..(offset_in_chunk + bytes.len());
+        let mut write_data = [0u8; FETCH_WIDTH_IN_BYTES];
+        let mut rw_mask = [false; FETCH_WIDTH_IN_BYTES];
+        rw_mask[bytes_range.clone()].fill(true);
+        if !is_read {
+            write_data[bytes_range.clone()].copy_from_slice(bytes);
+        }
+        let read_bytes = self.run_memory_operation(
+            if is_read {
+                #[hdl(sim)]
+                MemoryOperationKind.Read()
+            } else {
+                #[hdl(sim)]
+                MemoryOperationKind.Write()
+            },
+            masked_addr,
+            write_data,
+            rw_mask,
+            timeout_cycles,
+        )?;
+        if is_read {
+            bytes.copy_from_slice(&read_bytes[bytes_range]);
+        }
+        Ok(())
+    }
+    #[hdl]
+    fn read_bytes<const N: usize>(
+        &mut self,
+        start_addr: u64,
+        timeout_cycles: usize,
+    ) -> Result<[u8; N], SimValue<MemoryOperationErrorKind>> {
+        let mut retval = [0; _];
+        self.rw_bytes(start_addr, true, &mut retval, timeout_cycles)?;
+        Ok(retval)
+    }
+    #[hdl]
+    fn write_bytes<const N: usize>(
+        &mut self,
+        start_addr: u64,
+        mut bytes: [u8; N],
+        timeout_cycles: usize,
+    ) -> Result<(), SimValue<MemoryOperationErrorKind>> {
+        self.rw_bytes(start_addr, false, &mut bytes, timeout_cycles)
+    }
+}
+
+#[test]
+#[hdl]
+fn test_simple_uart() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let config = CpuConfig::new(
+        vec![
+            UnitConfig::new(UnitKind::AluBranch),
+            UnitConfig::new(UnitKind::AluBranch),
+        ],
+        NonZeroUsize::new(20).unwrap(),
+    );
+    const RECEIVER_QUEUE_SIZE: NonZeroUsize = NonZeroUsize::new(16).expect("not zero");
+    let m = simple_uart_loopback(
+        PhantomConst::new_sized(config),
+        clock_input_properties(),
+        BAUD_RATE,
+        RECEIVER_QUEUE_SIZE,
+    );
+    let mut sim = Simulation::new(m);
+    let writer = RcWriter::default();
+    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
+    struct DumpVcdOnDrop {
+        writer: Option<RcWriter>,
+    }
+    impl Drop for DumpVcdOnDrop {
+        fn drop(&mut self) {
+            if let Some(mut writer) = self.writer.take() {
+                let vcd = String::from_utf8(writer.take()).unwrap();
+                println!("####### VCD:\n{vcd}\n#######");
+            }
+        }
+    }
+    let mut writer = DumpVcdOnDrop {
+        writer: Some(writer),
+    };
+    sim.write(
+        sim.io().memory_interface.start.data,
+        sim.io().ty().memory_interface.start.data.HdlNone(),
+    );
+    sim.write(sim.io().memory_interface.finish.ready, false);
+    sim.write_clock(sim.io().cd.clk, false);
+    sim.write_reset(sim.io().cd.rst, true);
+    sim.advance_time(CLOCK_HALF_PERIOD);
+    sim.write_clock(sim.io().cd.clk, true);
+    sim.advance_time(CLOCK_HALF_PERIOD);
+    sim.write_clock(sim.io().cd.clk, false);
+    sim.write_reset(sim.io().cd.rst, false);
+    let mut mem_op_runner = MemoryOperationRunner {
+        clk: sim.io().cd.clk,
+        memory_interface: sim.io().memory_interface,
+        next_fetch_block_id: 0,
+        _phantom: PhantomData,
+        sim,
+    };
+
+    let empty_status = ReceiverQueueStatus::sim_as_u8(
+        #[hdl(sim)]
+        ReceiverQueueStatus.QueueEmpty(),
+    );
+
+    assert_eq!(
+        mem_op_runner
+            .read_bytes(SIMPLE_UART_STATUS_OFFSET, 1)
+            .unwrap(),
+        [empty_status],
+    );
+
+    mem_op_runner
+        .write_bytes(SIMPLE_UART_STATUS_OFFSET, [0], 1)
+        .unwrap_err();
+
+    assert_eq!(
+        mem_op_runner
+            .read_bytes(SIMPLE_UART_RECEIVE_OFFSET, 1)
+            .unwrap(),
+        [0],
+    );
+
+    const { assert!(SIMPLE_UART_RECEIVE_OFFSET + 1 == SIMPLE_UART_STATUS_OFFSET) };
+
+    assert_eq!(
+        mem_op_runner
+            .read_bytes(SIMPLE_UART_RECEIVE_OFFSET, 1)
+            .unwrap(),
+        [0, empty_status],
+    );
+
+    for i in 0..2 * FETCH_WIDTH_IN_BYTES as u64 {
+        mem_op_runner
+            .read_bytes::<1>(SIMPLE_UART_SIZE + i, 1)
+            .unwrap_err();
+        mem_op_runner
+            .write_bytes(SIMPLE_UART_SIZE + i, [0], 1)
+            .unwrap_err();
+    }
+
+    const TEST_TEXT: &str = "Test test test test\n";
+
+    const DELAY: usize = 2;
+
+    const {
+        assert!(
+            TEST_TEXT.len() > RECEIVER_QUEUE_SIZE.get() + DELAY,
+            "TEST_TEXT must be long enough to make the queue overflow when accounting for DELAY"
+        )
+    };
+
+    for (i, b) in TEST_TEXT.bytes().enumerate() {
+        let current_count = i + 1;
+        mem_op_runner
+            .write_bytes(SIMPLE_UART_TRANSMIT_OFFSET, [b], 300)
+            .unwrap();
+        let expected_status = ReceiverQueueStatus::for_queue_len_as_u8(
+            current_count.saturating_sub(DELAY),
+            RECEIVER_QUEUE_SIZE,
+        );
+        assert_eq!(
+            mem_op_runner
+                .read_bytes(SIMPLE_UART_STATUS_OFFSET, 1)
+                .unwrap(),
+            [expected_status],
+        );
+    }
+
+    for (i, mut expected_byte) in TEST_TEXT.bytes().enumerate() {
+        let read = mem_op_runner
+            .read_bytes(SIMPLE_UART_RECEIVE_OFFSET, 1)
+            .unwrap();
+        let current_count = if i == 0 {
+            RECEIVER_QUEUE_SIZE.get() + 1 // initial read starts with overflow
+        } else {
+            RECEIVER_QUEUE_SIZE.get().saturating_sub(i)
+        };
+        if current_count == 0 {
+            expected_byte = 0;
+        }
+        let expected_status =
+            ReceiverQueueStatus::for_queue_len_as_u8(current_count, RECEIVER_QUEUE_SIZE);
+        assert_eq!(read, [expected_byte, expected_status]);
+    }
+
+    let vcd = String::from_utf8(writer.writer.take().unwrap().take()).unwrap();
+    println!("####### VCD:\n{vcd}\n#######");
+    if vcd != include_str!("expected/simple_uart.vcd") {
+        panic!();
+    }
+}
--- a/scripts/check-copyright.sh
+++ b/scripts/check-copyright.sh
@ -31,6 +31,7 @@ function check_file()
 POUND_HEADER=('^"# SPDX-License-Identifier: LGPL-3.0-or-later"$' '^"# See Notices.txt for copyright information"$')
 SLASH_HEADER=('^"// SPDX-License-Identifier: LGPL-3.0-or-later"$' '^"// See Notices.txt for copyright information"$')
 MD_HEADER=('^"<!--"$' '^"SPDX-License-Identifier: LGPL-3.0-or-later"$' '^"See Notices.txt for copyright information"$')
+MERMAID_HEADER=('^"%% SPDX-License-Identifier: LGPL-3.0-or-later"$' '^"%% See Notices.txt for copyright information"$')

 function main()
 {
@ -45,12 +46,15 @@ function main()
        */LICENSE.md|*/Notices.txt)
            # copyright file
            ;;
-        /crates/cpu/tests/expected/*.vcd|/crates/cpu/tests/expected/*.txt)
+        /crates/cpu/tests*/expected/*.vcd|/crates/cpu/tests*/expected/*.txt)
            # file that can't contain copyright header
            ;;
-        /.forgejo/workflows/*.yml|*/.gitignore|*.toml)
+        /.forgejo/workflows/*.yml|*/.gitignore|*/.gitattributes|*.toml)
            check_file "$file" "${POUND_HEADER[@]}"
            ;;
+        *.mermaid)
+            check_file "$file" "${MERMAID_HEADER[@]}"
+            ;;
        *.md)
            check_file "$file" "${MD_HEADER[@]}"
            ;;
Author	SHA1	Message	Date
Jacob Lifshay	7f7e316b7b	implement simple_uart::simple_uart	2026-02-26 21:34:58 -08:00
Jacob Lifshay	61e8ed96b1	add test for simple_uart::receiver	2026-02-26 17:48:42 -08:00
Jacob Lifshay	b07ef2b363	add main_memory_and_io::simple_uart::receiver* and test for receiver_no_queue	2026-02-25 18:05:50 -08:00
Jacob Lifshay	e6caa320ef	add main_memory_and_io::simple_uart::{transmitter, uart_clock_gen} and tests	2026-02-25 15:22:34 -08:00
Jacob Lifshay	3fcd1c7338	add MemoryOperationStart.rw_mask	2026-02-25 00:08:42 -08:00
Jacob Lifshay	cd7823e81d	move MemoryInterface and related types to crate::main_memory_and_io	2026-02-25 00:08:42 -08:00
Jacob Lifshay	2a1813bff3	update to latest fayalite	2026-02-25 00:08:42 -08:00
Jacob Lifshay	e69c92c8da	add fetch::fetch and fetch::l1_i_cache with some testing	2026-02-21 18:32:01 -08:00
Jacob Lifshay	c62d33048c	update fayalite to c632e5d570 to speed up simulation	2026-02-04 16:33:46 -08:00
Jacob Lifshay	596440755c	update fayalite to include 1bc835803b for a major speedup of the decoder tests	2026-02-03 18:17:31 -08:00
Jacob Lifshay	68a4373bbd	update rust version to 1.93.0	2026-02-03 18:17:18 -08:00
Jacob Lifshay	f88346ea37	implement decoding mtspr/mfspr/mftb	2026-01-28 17:35:09 -08:00
Jacob Lifshay	a42b76b468	implement decoding all rotate instructions	2026-01-27 19:18:27 -08:00
Jacob Lifshay	130c1b2892	change CommonMOp to directly contain a generic immediate type	2026-01-27 17:03:14 -08:00
Jacob Lifshay	167bc4b6a6	implement decoding extswsli[.]	2026-01-26 19:18:44 -08:00
Jacob Lifshay	faa8dde774	reduce the number of wires to have one per form/field pair instead of one per insn/field pair	2026-01-26 16:11:03 -08:00
Jacob Lifshay	1db65ae753	implement decoding shifts: s[lr][wd][.] and sra[wd][i][.]	2026-01-26 15:14:26 -08:00
Jacob Lifshay	59874b9b29	add shift/rotate MOp definition	2026-01-25 20:34:38 -08:00
Jacob Lifshay	2ad469e331	simplify getting IMM_WIDTH for LogicalFlagsMOpImm	2026-01-25 20:25:25 -08:00
Jacob Lifshay	0824b63d31	implement decoding 8/16/32/64-bit store instructions -- all of Power ISA v3.1c Book I 3.3.3	2026-01-25 15:06:14 -08:00
Jacob Lifshay	706d54ae0d	implement decoding 8/16/32/64-bit load instructions -- all of Power ISA v3.1C Book I 3.3.2	2026-01-23 16:06:16 -08:00
Jacob Lifshay	d361a2b578	make LogicalFlagsMOp also copy the dest PRegValue.flags into PRegValue.int_fp	2026-01-23 12:13:06 -08:00
Jacob Lifshay	aa07e24c78	make check-copyright.sh also handle other tests/.../expected/... files	2026-01-23 12:13:06 -08:00
Jacob Lifshay	29757a568c	implement decoding mcrf	2026-01-23 11:47:06 -08:00
Jacob Lifshay	33529a2296	implement decoding condition register logical instructions	2026-01-23 11:27:48 -08:00
Jacob Lifshay	5e9d0957f6	reorder the decoder test cases to match the PowerISA v3.1C PDF	2026-01-23 09:46:29 -08:00
Jacob Lifshay	fc8a6cd959	split up tests/simple_power_isa_decoder into separate modules	2026-01-23 09:38:45 -08:00
Jacob Lifshay	87112c681a	move simple_power_isa_decoder integration test into its own folder	2026-01-23 08:46:28 -08:00
Jacob Lifshay	e6f876f9af	fix & clean up MOp definitions and ensure_reg_fields_are_in_the_same_place	2026-01-22 08:28:02 -08:00
Jacob Lifshay	9b8d99e9af	implement decoding mcrxrx	2026-01-22 07:34:53 -08:00
Jacob Lifshay	ffc3d4283c	refactor PRegFlags to use view structs instead of a long list of accessor methods	2026-01-20 19:07:46 -08:00
Jacob Lifshay	0433e4f8f1	mark .vcd files as generated	2026-01-20 16:20:40 -08:00
Jacob Lifshay	a93dca25ac	extract lut out into separate Lut4 type and add test	2026-01-20 16:03:28 -08:00
Jacob Lifshay	85ada6e55a	add tests for and fix decoding branch instructions	2026-01-19 22:38:48 -08:00
Jacob Lifshay	2e05329c36	add branch instructions, no tests yet	2026-01-19 20:09:21 -08:00
Jacob Lifshay	1fc56e02f9	decode exts[bhw][.] and pnop	2026-01-19 15:41:56 -08:00
Jacob Lifshay	aa85ecab01	simplify tests/simple_power_isa_decoder::test_cases somewhat	2026-01-19 14:16:00 -08:00
Jacob Lifshay	62a330ed4d	update reg_alloc.vcd	2026-01-18 23:23:54 -08:00
Jacob Lifshay	c9a3de19b7	add test that UnitMOp has all the register fields aligned across the different variants	2026-01-18 22:50:38 -08:00
Jacob Lifshay	7ebcd5de1e	decode bitwise logic instructions; also nop and mr special cases	2026-01-18 19:12:48 -08:00
Jacob Lifshay	3a35a698e2	decode fixed-point compare instructions	2026-01-18 16:37:00 -08:00
Jacob Lifshay	a4b052f5f3	decode all fixed-point add/sub instructions other than addex	2026-01-18 15:02:15 -08:00
Jacob Lifshay	62512960c3	decode some more add instructions	2026-01-15 16:10:03 -08:00
Jacob Lifshay	b7b6a02777	decodes an addi instruction	2026-01-14 21:41:25 -08:00
Jacob Lifshay	6d40eaadb3	WIP adding simple power isa decoder	2026-01-12 07:10:58 -08:00
Jacob Lifshay	305d7b0ae6	rename src/powerisa.rs -> src/powerisa_instructions_xml.rs	2026-01-12 03:31:06 -08:00
Jacob Lifshay	781dbc6bcb	add copyright header to build.rs	2026-01-09 02:05:08 -08:00
Jacob Lifshay	5faf0899a8	fully parse powerisa-instructions.xml	2026-01-09 02:03:59 -08:00
Jacob Lifshay	8c02483b65	wip parsing the xml	2026-01-08 00:09:20 -08:00
Jacob Lifshay	e4a7d9f59c	add build script that parses the PowerISA v3.1C pdf and produces an xml file	2026-01-07 14:19:46 -08:00
Jacob Lifshay	3b5104c8fa	fix vcd to match test output	2025-12-16 23:25:54 -08:00
Jacob Lifshay	2de4a67360	add link to other NLnet task and note lack of optimization	2025-12-16 23:10:07 -08:00
Jacob Lifshay	d5a7d9dd9e	next_pc works afaict	2025-12-16 23:06:32 -08:00
Jacob Lifshay	59da0aec06	WIP fixing bugs	2025-12-16 02:32:19 -08:00
Jacob Lifshay	5e1238b5c7	replace tests/next_pc's demo program with a simple expression parser as a better demo	2025-12-15 21:40:11 -08:00
Jacob Lifshay	bc9a3a5ce7	add missing copyright header and check-copyright.sh support for .mermaid	2025-12-15 03:00:37 -08:00
Jacob Lifshay	d42f010cda	WIP fixing bugs	2025-12-15 02:48:40 -08:00
Jacob Lifshay	84e4fde512	fix queueing errors	2025-12-15 00:47:53 -08:00
Jacob Lifshay	8ab63f3c6a	update fayalite	2025-12-14 21:05:59 -08:00
Jacob Lifshay	f39f40ce1f	fix next_pc::Queue and add test	2025-12-14 20:39:15 -08:00
Jacob Lifshay	cbd52c60a8	WIP: next_pc test fails	2025-12-14 01:26:18 -08:00
Jacob Lifshay	c87a1b8e1e	wrote out all of next_pc and tests/next_pc	2025-12-13 22:42:34 -08:00
Jacob Lifshay	cfd04469ce	WIP linking next_pc stages together	2025-12-10 20:31:04 -08:00
Jacob Lifshay	231f5e72ec	WIP: completed stages of next-pc logic, still need to combine them into a pipeline	2025-12-10 20:31:04 -08:00
Jacob Lifshay	033d5d4f34	WIP adding next_pc: add call stack	2025-12-10 20:31:04 -08:00
Jacob Lifshay	7a77c02cda	WIP adding next_pc: added mock_fetch_decode_pipe	2025-12-10 20:31:04 -08:00
Jacob Lifshay	61d52bd028	add Serialize/Deserialize impls for CpuConfig	2025-12-10 20:31:04 -08:00
Jacob Lifshay	554238c544	update for new fayalite	2025-12-10 20:31:04 -08:00
Jacob Lifshay	24d6537ffe	update Fayalite to get new features and bug fixes	2025-12-10 20:31:04 -08:00
Jacob Lifshay	c30bd0737f	add readme	2025-10-24 16:36:31 -07:00
Jacob Lifshay	291ad59b02	update CI to use new fayalite-deps container	2025-10-24 02:54:03 -07:00
Jacob Lifshay	5e8bc3e580	upgrade to Fayalite edcc5927a5f9ebca6 as part of this I switched to using Fayalite's UIntInRangeInclusive instead of using a custom Length struct	2025-10-24 02:53:35 -07:00
Jacob Lifshay	0e7a518bd0	switch to use server's new actions org	2025-10-10 00:03:53 -07:00