forked from libre-chip/cpu
decodes an addi instruction
This commit is contained in:
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SSH key fingerprint:
SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
4 changed files with 1560 additions and 399 deletions
File diff suppressed because it is too large
Load diff
667
crates/cpu/tests/expected/decode_one_insn.vcd
Normal file
667
crates/cpu/tests/expected/decode_one_insn.vcd
Normal file
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@ -0,0 +1,667 @@
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$upscope $end
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$upscope $end
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$upscope $end
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$scope struct dest $end
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$scope struct \[0] $end
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$upscope $end
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$upscope $end
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$upscope $end
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$upscope $end
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$var wire 4 L lut $end
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$upscope $end
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$upscope $end
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$scope struct src $end
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$upscope $end
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$scope struct src $end
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$upscope $end
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$scope struct src $end
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$upscope $end
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$upscope $end
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$upscope $end
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$upscope $end
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$upscope $end
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$upscope $end
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$scope struct src $end
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$scope struct _phantom $end
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$upscope $end
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$upscope $end
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$upscope $end
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$scope struct LoadStore $end
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$scope struct dest $end
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$scope struct normal_regs $end
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$scope struct \[0] $end
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$upscope $end
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$scope struct \[1] $end
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$upscope $end
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$upscope $end
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$scope struct flag_regs $end
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$scope struct \[0] $end
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$scope struct HdlSome $end
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$upscope $end
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$upscope $end
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$scope struct \[1] $end
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$var string 1 I" \$tag $end
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$scope struct HdlSome $end
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$upscope $end
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$upscope $end
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$upscope $end
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$upscope $end
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$scope struct src $end
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$upscope $end
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$scope struct _phantom $end
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$upscope $end
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$upscope $end
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$scope struct dest $end
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$scope struct normal_regs $end
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$scope struct \[0] $end
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$var wire 8 P" value $end
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$upscope $end
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$scope struct \[1] $end
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$upscope $end
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$upscope $end
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$scope struct flag_regs $end
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$scope struct \[0] $end
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$scope struct HdlSome $end
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$upscope $end
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$upscope $end
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$scope struct \[1] $end
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$var string 1 S" \$tag $end
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$scope struct HdlSome $end
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$upscope $end
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$upscope $end
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$upscope $end
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$upscope $end
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$scope struct src $end
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$upscope $end
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$scope struct _phantom $end
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$upscope $end
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$upscope $end
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$upscope $end
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$upscope $end
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$upscope $end
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$scope struct len $end
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$var wire 2 Y" value $end
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||||
$var string 1 Z" range $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 1 [" is_illegal $end
|
||||
$var wire 32 \" first_input $end
|
||||
$scope struct second_input $end
|
||||
$var string 1 ]" \$tag $end
|
||||
$var wire 32 ^" HdlSome $end
|
||||
$upscope $end
|
||||
$var wire 1 _" second_input_used $end
|
||||
$var wire 16 `" addi_SI $end
|
||||
$var wire 5 a" addi_RA $end
|
||||
$var wire 5 b" addi_RT $end
|
||||
$scope struct translate_gpr_or_zero $end
|
||||
$var wire 8 c" value $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
$dumpvars
|
||||
sAluBranch\x20(0) !
|
||||
sAddSubI\x20(1) "
|
||||
s0 #
|
||||
b100011 $
|
||||
b0 %
|
||||
sHdlNone\x20(0) &
|
||||
sHdlNone\x20(0) '
|
||||
b100100 (
|
||||
b0 )
|
||||
b0 *
|
||||
b1001000110100 +
|
||||
0,
|
||||
sFull64\x20(0) -
|
||||
0.
|
||||
0/
|
||||
00
|
||||
01
|
||||
s0 2
|
||||
b100011 3
|
||||
b0 4
|
||||
sHdlNone\x20(0) 5
|
||||
sHdlNone\x20(0) 6
|
||||
b100100 7
|
||||
b0 8
|
||||
b0 9
|
||||
b1001000110100 :
|
||||
0;
|
||||
sFull64\x20(0) <
|
||||
0=
|
||||
0>
|
||||
0?
|
||||
0@
|
||||
s0 A
|
||||
b100011 B
|
||||
b0 C
|
||||
sHdlNone\x20(0) D
|
||||
sHdlNone\x20(0) E
|
||||
b100100 F
|
||||
b0 G
|
||||
b0 H
|
||||
b1001000110100 I
|
||||
0J
|
||||
sFull64\x20(0) K
|
||||
b0 L
|
||||
b1 M
|
||||
b100011 N
|
||||
b0 O
|
||||
sHdlNone\x20(0) P
|
||||
sHdlNone\x20(0) Q
|
||||
b100100 R
|
||||
b0 S
|
||||
b0 T
|
||||
b1001000110100 U
|
||||
0V
|
||||
sStore\x20(1) W
|
||||
0X
|
||||
b100011 Y
|
||||
b0 Z
|
||||
sHdlNone\x20(0) [
|
||||
sHdlNone\x20(0) \
|
||||
b100100 ]
|
||||
b0 ^
|
||||
b0 _
|
||||
b1001000110100 `
|
||||
0a
|
||||
0b
|
||||
b100011 c
|
||||
b0 d
|
||||
sHdlNone\x20(0) e
|
||||
sHdlNone\x20(0) f
|
||||
b100100 g
|
||||
b0 h
|
||||
b0 i
|
||||
b1001000110100 j
|
||||
0k
|
||||
sAluBranch\x20(0) l
|
||||
sAddSub\x20(0) m
|
||||
s0 n
|
||||
b0 o
|
||||
b0 p
|
||||
sHdlNone\x20(0) q
|
||||
sHdlNone\x20(0) r
|
||||
b0 s
|
||||
b0 t
|
||||
b0 u
|
||||
b0 v
|
||||
0w
|
||||
sFull64\x20(0) x
|
||||
0y
|
||||
0z
|
||||
0{
|
||||
0|
|
||||
s0 }
|
||||
b0 ~
|
||||
b0 !"
|
||||
sHdlNone\x20(0) ""
|
||||
sHdlNone\x20(0) #"
|
||||
b0 $"
|
||||
b0 %"
|
||||
b0 &"
|
||||
b0 '"
|
||||
0("
|
||||
sFull64\x20(0) )"
|
||||
0*"
|
||||
0+"
|
||||
0,"
|
||||
0-"
|
||||
s0 ."
|
||||
b0 /"
|
||||
b0 0"
|
||||
sHdlNone\x20(0) 1"
|
||||
sHdlNone\x20(0) 2"
|
||||
b0 3"
|
||||
b0 4"
|
||||
b0 5"
|
||||
b0 6"
|
||||
07"
|
||||
sFull64\x20(0) 8"
|
||||
b0 9"
|
||||
b0 :"
|
||||
b0 ;"
|
||||
b0 <"
|
||||
sHdlNone\x20(0) ="
|
||||
sHdlNone\x20(0) >"
|
||||
b0 ?"
|
||||
b0 @"
|
||||
b0 A"
|
||||
b0 B"
|
||||
0C"
|
||||
sLoad\x20(0) D"
|
||||
0E"
|
||||
b0 F"
|
||||
b0 G"
|
||||
sHdlNone\x20(0) H"
|
||||
sHdlNone\x20(0) I"
|
||||
b0 J"
|
||||
b0 K"
|
||||
b0 L"
|
||||
b0 M"
|
||||
0N"
|
||||
0O"
|
||||
b0 P"
|
||||
b0 Q"
|
||||
sHdlNone\x20(0) R"
|
||||
sHdlNone\x20(0) S"
|
||||
b0 T"
|
||||
b0 U"
|
||||
b0 V"
|
||||
b0 W"
|
||||
0X"
|
||||
b1 Y"
|
||||
sPhantomConst(\"0..=2\") Z"
|
||||
0["
|
||||
b111000011001000001001000110100 \"
|
||||
sHdlNone\x20(0) ]"
|
||||
b0 ^"
|
||||
0_"
|
||||
b1001000110100 `"
|
||||
b100 a"
|
||||
b11 b"
|
||||
b100100 c"
|
||||
$end
|
||||
#1000000
|
||||
|
|
@ -2,7 +2,7 @@
|
|||
// See Notices.txt for copyright information
|
||||
|
||||
use cpu::{
|
||||
decoder::simple_power_isa::decode_one_32bit_insn,
|
||||
decoder::simple_power_isa::decode_one_insn,
|
||||
instruction::{AddSubMOp, MOp, MOpDestReg, MOpRegNum, OutputIntegerMode},
|
||||
util::array_vec::ArrayVec,
|
||||
};
|
||||
|
|
@ -15,7 +15,8 @@ use std::{
|
|||
|
||||
struct TestCase {
|
||||
mnemonic: &'static str,
|
||||
input: u32,
|
||||
first_input: u32,
|
||||
second_input: Option<u32>,
|
||||
output: SimValue<ArrayVec<MOp, ConstUsize<2>>>,
|
||||
loc: &'static std::panic::Location<'static>,
|
||||
}
|
||||
|
|
@ -24,13 +25,21 @@ impl fmt::Debug for TestCase {
|
|||
fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
|
||||
let Self {
|
||||
mnemonic,
|
||||
input,
|
||||
first_input,
|
||||
second_input,
|
||||
output,
|
||||
loc,
|
||||
} = self;
|
||||
f.debug_struct("TestCase")
|
||||
let mut debug_struct = f.debug_struct("TestCase");
|
||||
debug_struct
|
||||
.field("mnemonic", mnemonic)
|
||||
.field("input", &format_args!("0x{input:08x}"))
|
||||
.field("first_input", &format_args!("0x{first_input:08x}"));
|
||||
if let Some(second_input) = second_input {
|
||||
debug_struct.field("second_input", &format_args!("0x{second_input:08x}"));
|
||||
} else {
|
||||
debug_struct.field("second_input", &format_args!("None"));
|
||||
}
|
||||
debug_struct
|
||||
.field("output", &ArrayVec::elements_sim_ref(output))
|
||||
.field("loc", &format_args!("{loc}"))
|
||||
.finish()
|
||||
|
|
@ -43,7 +52,8 @@ fn test_cases() -> Vec<TestCase> {
|
|||
#[track_caller]
|
||||
fn insn_single(
|
||||
mnemonic: &'static str,
|
||||
input: u32,
|
||||
first_input: u32,
|
||||
second_input: Option<u32>,
|
||||
output: impl ToSimValue<Type = MOp>,
|
||||
) -> TestCase {
|
||||
let zero_mop = UInt::new_dyn(MOp.canonical().bit_width())
|
||||
|
|
@ -54,7 +64,8 @@ fn test_cases() -> Vec<TestCase> {
|
|||
ArrayVec::elements_sim_mut(&mut single_storage)[0] = output.to_sim_value();
|
||||
TestCase {
|
||||
mnemonic,
|
||||
input,
|
||||
first_input,
|
||||
second_input,
|
||||
output: single_storage.clone(),
|
||||
loc: std::panic::Location::caller(),
|
||||
}
|
||||
|
|
@ -62,8 +73,9 @@ fn test_cases() -> Vec<TestCase> {
|
|||
retval.push(insn_single(
|
||||
"addi 3, 4, 0x1234",
|
||||
0x38641234,
|
||||
None,
|
||||
AddSubMOp::add_sub_i(
|
||||
MOpDestReg::new_sim(&[3], &[]),
|
||||
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_GPR_REG_NUMS.start + 3], &[]),
|
||||
[
|
||||
(MOpRegNum::POWER_ISA_GPR_REG_NUMS.start + 4).cast_to_static::<UInt<_>>(),
|
||||
MOpRegNum::CONST_ZERO_REG_NUM.cast_to_static::<UInt<_>>(),
|
||||
|
|
@ -91,7 +103,8 @@ fn test_test_cases_assembly() -> std::io::Result<()> {
|
|||
let mut assembly = String::new();
|
||||
for TestCase {
|
||||
mnemonic,
|
||||
input: _,
|
||||
first_input: _,
|
||||
second_input: _,
|
||||
output: _,
|
||||
loc: _,
|
||||
} in &test_cases
|
||||
|
|
@ -123,15 +136,29 @@ fn test_test_cases_assembly() -> std::io::Result<()> {
|
|||
let mut lines = stdout.lines();
|
||||
let text_line = lines.next();
|
||||
assert_eq!(text_line, Some("\t.text"));
|
||||
for test_case in test_cases {
|
||||
for test_case @ TestCase {
|
||||
mnemonic: _,
|
||||
first_input,
|
||||
second_input,
|
||||
output: _,
|
||||
loc: _,
|
||||
} in test_cases
|
||||
{
|
||||
let Some(line) = lines.next() else {
|
||||
panic!("output missing line for: {test_case:?}");
|
||||
};
|
||||
let Some((_, comment)) = line.split_once('#') else {
|
||||
panic!("output line missing comment. test_case={test_case:?}\nline:\n{line}");
|
||||
};
|
||||
let [b0, b1, b2, b3] = test_case.input.to_le_bytes();
|
||||
let expected_comment = format!(" encoding: [0x{b0:02x},0x{b1:02x},0x{b2:02x},0x{b3:02x}]");
|
||||
let [b0, b1, b2, b3] = first_input.to_le_bytes();
|
||||
let expected_comment = if let Some(second_input) = second_input {
|
||||
let [b4, b5, b6, b7] = second_input.to_le_bytes();
|
||||
format!(
|
||||
" encoding: [0x{b0:02x},0x{b1:02x},0x{b2:02x},0x{b3:02x},0x{b4:02x},0x{b5:02x},0x{b6:02x},0x{b7:02x}]"
|
||||
)
|
||||
} else {
|
||||
format!(" encoding: [0x{b0:02x},0x{b1:02x},0x{b2:02x},0x{b3:02x}]")
|
||||
};
|
||||
assert_eq!(
|
||||
comment, expected_comment,
|
||||
"test_case={test_case:?}\nline:\n{line}"
|
||||
|
|
@ -145,9 +172,9 @@ fn test_test_cases_assembly() -> std::io::Result<()> {
|
|||
|
||||
#[hdl]
|
||||
#[test]
|
||||
fn test_decode_one_32bit_insn() {
|
||||
fn test_decode_insn() {
|
||||
let _n = SourceLocation::normalize_files_for_tests();
|
||||
let m = decode_one_32bit_insn();
|
||||
let m = decode_one_insn();
|
||||
let mut sim = Simulation::new(m);
|
||||
let writer = RcWriter::default();
|
||||
sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
|
||||
|
|
@ -165,20 +192,60 @@ fn test_decode_one_32bit_insn() {
|
|||
let mut writer = DumpVcdOnDrop {
|
||||
writer: Some(writer),
|
||||
};
|
||||
for test_case in test_cases() {
|
||||
sim.write(sim.io().input, test_case.input);
|
||||
for test_case @ TestCase {
|
||||
mnemonic: _,
|
||||
first_input,
|
||||
second_input,
|
||||
output: _,
|
||||
loc: _,
|
||||
} in test_cases()
|
||||
{
|
||||
sim.write(sim.io().first_input, first_input);
|
||||
sim.write(
|
||||
sim.io().second_input,
|
||||
if let Some(v) = second_input {
|
||||
#[hdl(sim)]
|
||||
HdlSome(v)
|
||||
} else {
|
||||
#[hdl(sim)]
|
||||
HdlNone()
|
||||
},
|
||||
);
|
||||
sim.advance_time(SimDuration::from_micros(1));
|
||||
let second_input_used = sim.read_bool(sim.io().second_input_used);
|
||||
let is_illegal = sim.read_bool(sim.io().is_illegal);
|
||||
let output = sim.read(sim.io().output);
|
||||
let expected = format!("{:?}", ArrayVec::elements_sim_ref(&test_case.output));
|
||||
let output = format!("{:?}", ArrayVec::elements_sim_ref(&output));
|
||||
#[derive(Debug)]
|
||||
#[expect(dead_code, reason = "used only for Debug formatting")]
|
||||
struct FormattedOutput<'a> {
|
||||
insns: &'a [SimValue<MOp>],
|
||||
second_input_used: bool,
|
||||
is_illegal: bool,
|
||||
}
|
||||
let expected = format!(
|
||||
"{:#?}",
|
||||
FormattedOutput {
|
||||
insns: ArrayVec::elements_sim_ref(&test_case.output),
|
||||
second_input_used: second_input.is_some(),
|
||||
is_illegal: false,
|
||||
},
|
||||
);
|
||||
let output = format!(
|
||||
"{:#?}",
|
||||
FormattedOutput {
|
||||
insns: ArrayVec::elements_sim_ref(&output),
|
||||
second_input_used,
|
||||
is_illegal,
|
||||
},
|
||||
);
|
||||
assert!(
|
||||
expected == output,
|
||||
"test_case={test_case:?}\noutput={output}"
|
||||
"test_case={test_case:#?}\noutput={output}"
|
||||
);
|
||||
}
|
||||
let vcd = String::from_utf8(writer.writer.take().unwrap().take()).unwrap();
|
||||
println!("####### VCD:\n{vcd}\n#######");
|
||||
if vcd != include_str!("expected/decode_one_32bit_insn.vcd") {
|
||||
if vcd != include_str!("expected/decode_one_insn.vcd") {
|
||||
panic!();
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue