forked from libre-chip/cpu
implement simple_uart::simple_uart
This commit is contained in:
parent
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commit
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SSH key fingerprint:
SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
3 changed files with 185443 additions and 6 deletions
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@ -3,7 +3,14 @@
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use std::num::NonZeroUsize;
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use crate::config::CpuConfig;
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use crate::{
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config::{CpuConfig, PhantomConstCpuConfig},
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main_memory_and_io::{
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MemoryInterface, MemoryOperationErrorKind, MemoryOperationFinish,
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MemoryOperationFinishKind, MemoryOperationKind, MemoryOperationStart,
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},
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util::array_vec::ArrayVec,
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};
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use fayalite::{
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int::UIntInRange,
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prelude::*,
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@ -258,6 +265,37 @@ pub enum ReceiverQueueStatus {
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QueueOverflowed,
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}
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impl ReceiverQueueStatus {
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pub fn sim_as_u8(this: impl ToSimValue<Type = Self>) -> u8 {
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SimValue::bits(&this.into_sim_value())
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.cast_to_static::<UInt<8>>()
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.as_int()
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}
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#[hdl]
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pub fn for_queue_len_sim(current_count: usize, queue_size: NonZeroUsize) -> SimValue<Self> {
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if current_count == 0 {
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#[hdl(sim)]
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ReceiverQueueStatus.QueueEmpty()
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} else if current_count == queue_size.get() {
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#[hdl(sim)]
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ReceiverQueueStatus.QueueFull()
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} else if current_count == queue_size.get() - 1 {
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#[hdl(sim)]
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ReceiverQueueStatus.QueueAlmostFull()
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} else if current_count > queue_size.get() {
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#[hdl(sim)]
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ReceiverQueueStatus.QueueOverflowed()
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} else {
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#[hdl(sim)]
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ReceiverQueueStatus.QueueNotEmpty()
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}
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}
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#[hdl]
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pub fn for_queue_len_as_u8(current_count: usize, queue_size: NonZeroUsize) -> u8 {
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Self::sim_as_u8(Self::for_queue_len_sim(current_count, queue_size))
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}
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}
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/// `rx_synchronized` is [`peripherals::Uart::rx`], but after being synchronized to `cd.clk`.
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#[hdl_module]
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pub fn receiver(queue_capacity: NonZeroUsize) {
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@ -317,16 +355,32 @@ pub fn receiver(queue_capacity: NonZeroUsize) {
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connect(queue.inp.data, inner.output_byte);
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}
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pub const SIMPLE_UART_RECEIVE_OFFSET: u64 = 0;
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pub const SIMPLE_UART_TRANSMIT_OFFSET: u64 = 0;
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pub const SIMPLE_UART_STATUS_OFFSET: u64 = 1;
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pub const SIMPLE_UART_SIZE: u64 = 2;
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#[hdl(no_static)]
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struct Operation<C: PhantomConstGet<CpuConfig> + PhantomConstCpuConfig> {
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start: MemoryOperationStart<C>,
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finish: HdlOption<MemoryOperationFinish<C>>,
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}
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#[hdl_module]
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pub fn simple_uart(
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config: PhantomConst<CpuConfig>,
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clock_input_properties: PhantomConst<peripherals::ClockInputProperties>,
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baud_rate: f64,
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receiver_queue_size: NonZeroUsize,
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) {
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#[hdl]
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let cd: ClockDomain = m.input();
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#[hdl]
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let memory_interface: MemoryInterface<PhantomConst<CpuConfig>> =
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m.input(MemoryInterface[config]);
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#[hdl]
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let uart: peripherals::Uart = m.output();
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#[hdl]
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let rx_sync_intermediate_reg: Bool = reg_builder().clock_domain(cd).reset(true);
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annotate(rx_sync_intermediate_reg, DontTouchAnnotation);
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@ -340,5 +394,194 @@ pub fn simple_uart(
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annotate(rx_synchronized, DontTouchAnnotation);
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connect(rx_synchronized, rx_sync_final_reg);
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todo!("add transmitter and receiver");
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#[hdl]
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let clk_gen = instance(uart_clock_gen(clock_input_properties, baud_rate));
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connect(clk_gen.cd, cd);
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#[hdl]
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let transmitter = instance(transmitter());
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connect(transmitter.cd, cd);
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connect(transmitter.tick, clk_gen.tick);
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connect(uart.tx, transmitter.tx);
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#[hdl]
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let receiver = instance(receiver(receiver_queue_size));
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connect(receiver.cd, cd);
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connect(receiver.tick, clk_gen.tick);
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connect(receiver.rx_synchronized, rx_synchronized);
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#[hdl]
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let operation_reg = reg_builder()
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.clock_domain(cd)
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.reset(HdlOption[Operation[config]].HdlNone());
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let next_fetch_block_ids_ty = memory_interface.ty().next_fetch_block_ids.HdlSome;
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#[hdl]
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if let HdlSome(operation) = operation_reg {
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#[hdl]
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let MemoryInterface::<_> {
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start,
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finish,
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next_fetch_block_ids,
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config: _,
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} = memory_interface;
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connect(start.ready, false);
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connect(finish.data, operation.finish);
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connect(
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next_fetch_block_ids,
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HdlSome(ArrayVec::from_parts_unchecked(
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repeat(
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operation.start.fetch_block_id,
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next_fetch_block_ids_ty.capacity(),
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),
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1u8.cast_to(next_fetch_block_ids_ty.len_ty()),
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)),
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);
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connect(transmitter.input_byte.data, HdlNone());
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connect(receiver.output_byte.ready, false);
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#[hdl]
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if let HdlSome(_) = operation.finish {
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#[hdl]
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if finish.ready {
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connect(operation_reg, operation_reg.ty().HdlNone());
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}
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} else {
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#[hdl]
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let MemoryOperationStart::<_> {
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kind,
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addr,
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write_data,
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rw_mask,
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fetch_block_id: _,
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config: _,
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} = operation.start;
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#[hdl]
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let valid_addr = wire();
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connect(valid_addr, true);
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#[hdl]
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let all_ready = wire();
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connect(all_ready, true);
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#[hdl]
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let read_data = wire(write_data.ty());
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for (byte_index, ((rw_mask, write_data), read_data)) in rw_mask
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.into_iter()
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.zip(write_data)
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.zip(read_data)
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.enumerate()
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{
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let byte_addr = (addr | byte_index).cast_to_static::<UInt<64>>();
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connect(read_data, 0u8);
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#[hdl]
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if rw_mask {
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#[hdl]
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match kind {
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MemoryOperationKind::Read => {
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#[hdl]
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if byte_addr.cmp_eq(SIMPLE_UART_RECEIVE_OFFSET) {
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connect(receiver.output_byte.ready, valid_addr);
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#[hdl]
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if let HdlSome(byte) = receiver.output_byte.data {
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connect(read_data, byte);
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}
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// if there is no byte ready yet, we read a zero to avoid blocking the CPU on external inputs.
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} else if byte_addr.cmp_eq(SIMPLE_UART_STATUS_OFFSET) {
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connect(
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read_data,
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receiver
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.queue_status
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.cast_to_bits()
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.cast_to_static::<UInt<8>>(),
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);
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} else {
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connect(valid_addr, false);
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}
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}
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MemoryOperationKind::Write => {
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#[hdl]
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if byte_addr.cmp_eq(SIMPLE_UART_TRANSMIT_OFFSET) {
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#[hdl]
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if !transmitter.input_byte.ready {
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connect(all_ready, false);
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}
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#[hdl]
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if valid_addr {
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connect(transmitter.input_byte.data, HdlSome(write_data));
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}
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} else {
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connect(valid_addr, false);
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}
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}
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}
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}
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}
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#[hdl]
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if !valid_addr {
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connect(
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operation_reg,
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HdlSome(
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#[hdl]
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Operation::<_> {
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start: operation.start,
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finish: HdlSome(
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#[hdl]
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MemoryOperationFinish::<_> {
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kind: MemoryOperationFinishKind
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.Error(MemoryOperationErrorKind.Generic()),
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read_data,
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config,
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},
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),
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},
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),
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);
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} else if all_ready {
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connect(
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operation_reg,
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HdlSome(
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#[hdl]
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Operation::<_> {
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start: operation.start,
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finish: HdlSome(
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#[hdl]
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MemoryOperationFinish::<_> {
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kind: MemoryOperationFinishKind.Success(kind),
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read_data,
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config,
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},
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),
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},
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),
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);
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}
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}
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} else {
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#[hdl]
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let MemoryInterface::<_> {
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start,
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finish,
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next_fetch_block_ids,
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config: _,
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} = memory_interface;
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connect(start.ready, true);
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connect(finish.data, finish.ty().data.HdlNone());
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connect(
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next_fetch_block_ids,
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HdlSome(next_fetch_block_ids_ty.new_sim(next_fetch_block_ids_ty.element().zero())),
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);
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#[hdl]
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if let HdlSome(start) = start.data {
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connect(
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operation_reg,
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HdlSome(
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#[hdl]
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Operation::<_> {
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start,
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finish: operation_reg.ty().HdlSome.finish.HdlNone(),
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},
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),
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);
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}
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connect(transmitter.input_byte.data, HdlNone());
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connect(receiver.output_byte.ready, false);
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}
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}
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184803
crates/cpu/tests/expected/simple_uart.vcd
generated
Normal file
184803
crates/cpu/tests/expected/simple_uart.vcd
generated
Normal file
File diff suppressed because it is too large
Load diff
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@ -1,16 +1,29 @@
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// SPDX-License-Identifier: LGPL-3.0-or-later
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// See Notices.txt for copyright information
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use cpu::main_memory_and_io::simple_uart::{
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ReceiverQueueStatus, receiver, receiver_no_queue, transmitter, uart_clock_gen,
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use cpu::{
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config::{CpuConfig, UnitConfig},
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main_memory_and_io::{
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MemoryInterface, MemoryOperationErrorKind, MemoryOperationFinish,
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MemoryOperationFinishKind, MemoryOperationKind, MemoryOperationStart,
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simple_uart::{
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ReceiverQueueStatus, SIMPLE_UART_RECEIVE_OFFSET, SIMPLE_UART_SIZE,
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SIMPLE_UART_STATUS_OFFSET, SIMPLE_UART_TRANSMIT_OFFSET, receiver, receiver_no_queue,
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simple_uart, transmitter, uart_clock_gen,
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},
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},
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next_pc::FETCH_BLOCK_ID_WIDTH,
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unit::UnitKind,
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util::array_vec::ArrayVec,
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};
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use fayalite::{
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bundle::BundleType,
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intern::{Intern, Interned},
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prelude::*,
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sim::vcd::VcdWriterDecls,
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util::{RcWriter, ready_valid::ReadyValid},
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};
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use std::num::NonZeroUsize;
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use std::{borrow::BorrowMut, marker::PhantomData, num::NonZeroUsize};
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const fn half_period(frequency: f64) -> SimDuration {
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SimDuration::from_attos((SimDuration::from_secs(1).as_attos() as f64 / frequency / 2.0) as u128)
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@ -564,4 +577,382 @@ fn test_receiver_and_uart_clock_gen() {
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}
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}
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// TODO: test simple_uart()
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#[hdl_module]
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fn simple_uart_loopback(
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config: PhantomConst<CpuConfig>,
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clock_input_properties: PhantomConst<peripherals::ClockInputProperties>,
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baud_rate: f64,
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receiver_queue_size: NonZeroUsize,
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) {
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#[hdl]
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let cd: ClockDomain = m.input();
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#[hdl]
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let memory_interface: MemoryInterface<PhantomConst<CpuConfig>> =
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m.input(MemoryInterface[config]);
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#[hdl]
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let tx: Bool = m.output();
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#[hdl]
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let inner = instance(simple_uart(
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config,
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clock_input_properties,
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baud_rate,
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receiver_queue_size,
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));
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connect(inner.cd, cd);
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connect(inner.memory_interface, memory_interface);
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connect(tx, inner.uart.tx);
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connect(inner.uart.rx, inner.uart.tx);
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}
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struct MemoryOperationRunner<Sim: BorrowMut<Simulation<T>>, T: BundleType> {
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sim: Sim,
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clk: Expr<Clock>,
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memory_interface: Expr<MemoryInterface<PhantomConst<CpuConfig>>>,
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next_fetch_block_id: u64,
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_phantom: PhantomData<T>,
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}
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const FETCH_WIDTH_IN_BYTES: usize = 1 << CpuConfig::DEFAULT_LOG2_FETCH_WIDTH_IN_BYTES;
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impl<Sim: BorrowMut<Simulation<T>>, T: BundleType> MemoryOperationRunner<Sim, T> {
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#[hdl]
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fn run_memory_operation(
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&mut self,
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kind: impl ToSimValue<Type = MemoryOperationKind>,
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addr: u64,
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write_data: [u8; FETCH_WIDTH_IN_BYTES],
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rw_mask: [bool; FETCH_WIDTH_IN_BYTES],
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timeout_cycles: usize,
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) -> Result<[u8; FETCH_WIDTH_IN_BYTES], SimValue<MemoryOperationErrorKind>> {
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let kind = kind.into_sim_value();
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assert_eq!(addr % FETCH_WIDTH_IN_BYTES as u64, 0);
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let config = self.memory_interface.ty().config;
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let fetch_block_id = self
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.next_fetch_block_id
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.cast_to_static::<UInt<{ FETCH_BLOCK_ID_WIDTH }>>();
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self.next_fetch_block_id += 1;
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println!(
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"started: MemoryOperationStart {{\n \
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kind: {kind:?},\n \
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addr: {addr:#x},\n \
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write_data: {write_data:?},\n \
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rw_mask: {rw_mask:?},\n \
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fetch_block_id: {fetch_block_id},\n\
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}}"
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);
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let start_value = #[hdl(sim)]
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MemoryOperationStart::<_> {
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kind,
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addr,
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write_data: &write_data[..],
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rw_mask: &rw_mask[..],
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fetch_block_id,
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config,
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};
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#[hdl]
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let MemoryInterface::<_> {
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start,
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finish,
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next_fetch_block_ids,
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config: _,
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} = self.memory_interface;
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let sim = self.sim.borrow_mut();
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let check_io = |sim: &mut Simulation<T>,
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expected_start_ready: bool,
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expected_finish_data_is_some: bool,
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expected_next_fetch_block_ids: &[_]| {
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assert_eq!(sim.read_bool(start.ready), expected_start_ready);
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let finish_data = sim.read(finish.data);
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let finish_data_is_some = #[hdl(sim)]
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if let HdlSome(_) = &finish_data {
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true
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} else {
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false
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};
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assert_eq!(
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finish_data_is_some, expected_finish_data_is_some,
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"finish.data: {finish_data:?}"
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);
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#[hdl(sim)]
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if let HdlSome(next_fetch_block_ids) = sim.read(next_fetch_block_ids) {
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let next_fetch_block_ids: Vec<_> =
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ArrayVec::elements_sim_ref(&next_fetch_block_ids)
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.iter()
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.map(|v| v.as_int())
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.collect();
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assert_eq!(next_fetch_block_ids, expected_next_fetch_block_ids);
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} else {
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panic!("next_fetch_block_ids should be HdlSome");
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}
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};
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check_io(sim, true, false, &[]);
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sim.write(
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start.data,
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#[hdl(sim)]
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(start.ty().data).HdlSome(&start_value),
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);
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sim.write(finish.ready, true);
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sim.advance_time(CLOCK_HALF_PERIOD);
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sim.write_clock(self.clk, true);
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sim.advance_time(CLOCK_HALF_PERIOD);
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sim.write_clock(self.clk, false);
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sim.write(
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start.data,
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#[hdl(sim)]
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(start.ty().data).HdlNone(),
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);
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check_io(sim, false, false, &[start_value.fetch_block_id.as_int()]);
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for _ in 0..timeout_cycles {
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sim.advance_time(CLOCK_HALF_PERIOD);
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sim.write_clock(self.clk, true);
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sim.advance_time(CLOCK_HALF_PERIOD);
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sim.write_clock(self.clk, false);
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#[hdl(sim)]
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if let HdlSome(finish_data) = sim.read(finish.data) {
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#[hdl(sim)]
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let MemoryOperationFinish::<_> {
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kind,
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read_data,
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config: _,
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} = finish_data;
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assert_eq!(read_data.len(), FETCH_WIDTH_IN_BYTES);
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let read_data = std::array::from_fn(|i| read_data[i].as_int());
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||||
println!(
|
||||
"finished: MemoryOperationFinish {{\n \
|
||||
kind: {kind:?},\n \
|
||||
read_data: {read_data:?},\n\
|
||||
}}"
|
||||
);
|
||||
check_io(sim, false, true, &[start_value.fetch_block_id.as_int()]);
|
||||
sim.advance_time(CLOCK_HALF_PERIOD);
|
||||
sim.write_clock(self.clk, true);
|
||||
sim.advance_time(CLOCK_HALF_PERIOD);
|
||||
sim.write_clock(self.clk, false);
|
||||
sim.write(finish.ready, false);
|
||||
check_io(sim, true, false, &[]);
|
||||
return #[hdl(sim)]
|
||||
match kind {
|
||||
MemoryOperationFinishKind::Success(kind) => {
|
||||
assert_eq!(
|
||||
SimValue::bits(&kind),
|
||||
SimValue::bits(&start_value.kind),
|
||||
"finish_data.kind={kind:?}",
|
||||
);
|
||||
Ok(read_data)
|
||||
}
|
||||
MemoryOperationFinishKind::Error(error) => Err(error),
|
||||
};
|
||||
}
|
||||
check_io(sim, false, false, &[start_value.fetch_block_id.as_int()]);
|
||||
}
|
||||
panic!("memory operation took too long");
|
||||
}
|
||||
#[hdl]
|
||||
fn rw_bytes(
|
||||
&mut self,
|
||||
start_addr: u64,
|
||||
is_read: bool,
|
||||
bytes: &mut [u8],
|
||||
timeout_cycles: usize,
|
||||
) -> Result<(), SimValue<MemoryOperationErrorKind>> {
|
||||
let offset_in_chunk = start_addr as usize % FETCH_WIDTH_IN_BYTES;
|
||||
let masked_addr = start_addr - offset_in_chunk as u64;
|
||||
assert!(
|
||||
offset_in_chunk
|
||||
.checked_add(bytes.len())
|
||||
.is_some_and(|v| v <= FETCH_WIDTH_IN_BYTES)
|
||||
);
|
||||
let bytes_range = offset_in_chunk..(offset_in_chunk + bytes.len());
|
||||
let mut write_data = [0u8; FETCH_WIDTH_IN_BYTES];
|
||||
let mut rw_mask = [false; FETCH_WIDTH_IN_BYTES];
|
||||
rw_mask[bytes_range.clone()].fill(true);
|
||||
if !is_read {
|
||||
write_data[bytes_range.clone()].copy_from_slice(bytes);
|
||||
}
|
||||
let read_bytes = self.run_memory_operation(
|
||||
if is_read {
|
||||
#[hdl(sim)]
|
||||
MemoryOperationKind.Read()
|
||||
} else {
|
||||
#[hdl(sim)]
|
||||
MemoryOperationKind.Write()
|
||||
},
|
||||
masked_addr,
|
||||
write_data,
|
||||
rw_mask,
|
||||
timeout_cycles,
|
||||
)?;
|
||||
if is_read {
|
||||
bytes.copy_from_slice(&read_bytes[bytes_range]);
|
||||
}
|
||||
Ok(())
|
||||
}
|
||||
#[hdl]
|
||||
fn read_bytes<const N: usize>(
|
||||
&mut self,
|
||||
start_addr: u64,
|
||||
timeout_cycles: usize,
|
||||
) -> Result<[u8; N], SimValue<MemoryOperationErrorKind>> {
|
||||
let mut retval = [0; _];
|
||||
self.rw_bytes(start_addr, true, &mut retval, timeout_cycles)?;
|
||||
Ok(retval)
|
||||
}
|
||||
#[hdl]
|
||||
fn write_bytes<const N: usize>(
|
||||
&mut self,
|
||||
start_addr: u64,
|
||||
mut bytes: [u8; N],
|
||||
timeout_cycles: usize,
|
||||
) -> Result<(), SimValue<MemoryOperationErrorKind>> {
|
||||
self.rw_bytes(start_addr, false, &mut bytes, timeout_cycles)
|
||||
}
|
||||
}
|
||||
|
||||
#[test]
|
||||
#[hdl]
|
||||
fn test_simple_uart() {
|
||||
let _n = SourceLocation::normalize_files_for_tests();
|
||||
let config = CpuConfig::new(
|
||||
vec![
|
||||
UnitConfig::new(UnitKind::AluBranch),
|
||||
UnitConfig::new(UnitKind::AluBranch),
|
||||
],
|
||||
NonZeroUsize::new(20).unwrap(),
|
||||
);
|
||||
const RECEIVER_QUEUE_SIZE: NonZeroUsize = NonZeroUsize::new(16).expect("not zero");
|
||||
let m = simple_uart_loopback(
|
||||
PhantomConst::new_sized(config),
|
||||
clock_input_properties(),
|
||||
BAUD_RATE,
|
||||
RECEIVER_QUEUE_SIZE,
|
||||
);
|
||||
let mut sim = Simulation::new(m);
|
||||
let writer = RcWriter::default();
|
||||
sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
|
||||
struct DumpVcdOnDrop {
|
||||
writer: Option<RcWriter>,
|
||||
}
|
||||
impl Drop for DumpVcdOnDrop {
|
||||
fn drop(&mut self) {
|
||||
if let Some(mut writer) = self.writer.take() {
|
||||
let vcd = String::from_utf8(writer.take()).unwrap();
|
||||
println!("####### VCD:\n{vcd}\n#######");
|
||||
}
|
||||
}
|
||||
}
|
||||
let mut writer = DumpVcdOnDrop {
|
||||
writer: Some(writer),
|
||||
};
|
||||
sim.write(
|
||||
sim.io().memory_interface.start.data,
|
||||
sim.io().ty().memory_interface.start.data.HdlNone(),
|
||||
);
|
||||
sim.write(sim.io().memory_interface.finish.ready, false);
|
||||
sim.write_clock(sim.io().cd.clk, false);
|
||||
sim.write_reset(sim.io().cd.rst, true);
|
||||
sim.advance_time(CLOCK_HALF_PERIOD);
|
||||
sim.write_clock(sim.io().cd.clk, true);
|
||||
sim.advance_time(CLOCK_HALF_PERIOD);
|
||||
sim.write_clock(sim.io().cd.clk, false);
|
||||
sim.write_reset(sim.io().cd.rst, false);
|
||||
let mut mem_op_runner = MemoryOperationRunner {
|
||||
clk: sim.io().cd.clk,
|
||||
memory_interface: sim.io().memory_interface,
|
||||
next_fetch_block_id: 0,
|
||||
_phantom: PhantomData,
|
||||
sim,
|
||||
};
|
||||
|
||||
let empty_status = ReceiverQueueStatus::sim_as_u8(
|
||||
#[hdl(sim)]
|
||||
ReceiverQueueStatus.QueueEmpty(),
|
||||
);
|
||||
|
||||
assert_eq!(
|
||||
mem_op_runner
|
||||
.read_bytes(SIMPLE_UART_STATUS_OFFSET, 1)
|
||||
.unwrap(),
|
||||
[empty_status],
|
||||
);
|
||||
|
||||
mem_op_runner
|
||||
.write_bytes(SIMPLE_UART_STATUS_OFFSET, [0], 1)
|
||||
.unwrap_err();
|
||||
|
||||
assert_eq!(
|
||||
mem_op_runner
|
||||
.read_bytes(SIMPLE_UART_RECEIVE_OFFSET, 1)
|
||||
.unwrap(),
|
||||
[0],
|
||||
);
|
||||
|
||||
const { assert!(SIMPLE_UART_RECEIVE_OFFSET + 1 == SIMPLE_UART_STATUS_OFFSET) };
|
||||
|
||||
assert_eq!(
|
||||
mem_op_runner
|
||||
.read_bytes(SIMPLE_UART_RECEIVE_OFFSET, 1)
|
||||
.unwrap(),
|
||||
[0, empty_status],
|
||||
);
|
||||
|
||||
for i in 0..2 * FETCH_WIDTH_IN_BYTES as u64 {
|
||||
mem_op_runner
|
||||
.read_bytes::<1>(SIMPLE_UART_SIZE + i, 1)
|
||||
.unwrap_err();
|
||||
mem_op_runner
|
||||
.write_bytes(SIMPLE_UART_SIZE + i, [0], 1)
|
||||
.unwrap_err();
|
||||
}
|
||||
|
||||
const TEST_TEXT: &str = "Test test test test\n";
|
||||
|
||||
const DELAY: usize = 2;
|
||||
|
||||
const {
|
||||
assert!(
|
||||
TEST_TEXT.len() > RECEIVER_QUEUE_SIZE.get() + DELAY,
|
||||
"TEST_TEXT must be long enough to make the queue overflow when accounting for DELAY"
|
||||
)
|
||||
};
|
||||
|
||||
for (i, b) in TEST_TEXT.bytes().enumerate() {
|
||||
let current_count = i + 1;
|
||||
mem_op_runner
|
||||
.write_bytes(SIMPLE_UART_TRANSMIT_OFFSET, [b], 300)
|
||||
.unwrap();
|
||||
let expected_status = ReceiverQueueStatus::for_queue_len_as_u8(
|
||||
current_count.saturating_sub(DELAY),
|
||||
RECEIVER_QUEUE_SIZE,
|
||||
);
|
||||
assert_eq!(
|
||||
mem_op_runner
|
||||
.read_bytes(SIMPLE_UART_STATUS_OFFSET, 1)
|
||||
.unwrap(),
|
||||
[expected_status],
|
||||
);
|
||||
}
|
||||
|
||||
for (i, mut expected_byte) in TEST_TEXT.bytes().enumerate() {
|
||||
let read = mem_op_runner
|
||||
.read_bytes(SIMPLE_UART_RECEIVE_OFFSET, 1)
|
||||
.unwrap();
|
||||
let current_count = if i == 0 {
|
||||
RECEIVER_QUEUE_SIZE.get() + 1 // initial read starts with overflow
|
||||
} else {
|
||||
RECEIVER_QUEUE_SIZE.get().saturating_sub(i)
|
||||
};
|
||||
if current_count == 0 {
|
||||
expected_byte = 0;
|
||||
}
|
||||
let expected_status =
|
||||
ReceiverQueueStatus::for_queue_len_as_u8(current_count, RECEIVER_QUEUE_SIZE);
|
||||
assert_eq!(read, [expected_byte, expected_status]);
|
||||
}
|
||||
|
||||
let vcd = String::from_utf8(writer.writer.take().unwrap().take()).unwrap();
|
||||
println!("####### VCD:\n{vcd}\n#######");
|
||||
if vcd != include_str!("expected/simple_uart.vcd") {
|
||||
panic!();
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue