drewbabel 3006280d70 xilinx_srl: keep the clock enable on FDRE shift registers ... run_fixed inferred a fixed length shift register from a chain of FDRE flops but assigned it ENPOL 2, which the cells_map template reads as no enable and ties the enable high. FDRE has an active high clock enable, so the shift register shifted every cycle and ignored stalls. Give FDRE and FDRE_1 chains ENPOL 1 so the active high enable is kept. Add tests/arch/xilinx/xilinx_srl_enable.ys covering the FDRE path.		2026-07-20 23:59:40 -07:00
..
aiger	Move rename logic to abc_ops_reintegrate	2026-06-19 10:46:47 +01:00
alumacc	Use generic testing on few more places	2026-04-16 11:00:44 +02:00
arch	xilinx_srl: keep the clock enable on FDRE shift registers	2026-07-20 23:59:40 -07:00
arith_tree	End of file fix	2026-06-23 07:23:41 +02:00
asicworld	Remove trailing whitespaces	2026-06-23 07:24:59 +02:00
bind	Use generic testing on few more places	2026-04-16 11:00:44 +02:00
blif	Cleanup	2026-04-16 11:00:44 +02:00
bram	Add initial codecov support	2026-07-10 12:19:59 +02:00
bugpoint	Remove trailing whitespaces	2026-06-23 07:24:59 +02:00
check_mem	tests/check_mem: Drop unused init check	2026-05-30 11:06:11 +12:00
cxxrtl	Remove trailing whitespaces	2026-06-23 07:24:59 +02:00
errors	End of file fix	2026-06-23 07:23:41 +02:00
fmt	Cleanup	2026-04-16 11:00:44 +02:00
fsm	Did share, opt_share and fsm	2026-04-16 11:00:44 +02:00
functional	Remove trailing whitespaces	2026-06-23 07:24:59 +02:00
hana	Remove trailing whitespaces	2026-06-23 07:24:59 +02:00
liberty	Add scl caching test.	2026-07-10 14:52:06 +02:00
lut	Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files.	2025-07-22 10:38:38 +00:00
memfile	Update CI scripts for CMake	2026-06-03 08:58:11 +00:00
memlib	Remove trailing whitespaces	2026-06-23 07:24:59 +02:00
memories	Remove trailing whitespaces	2026-06-23 07:24:59 +02:00
opt	Merge pull request #6012 from YosysHQ/nella/fix-opt-reduce	2026-07-08 13:36:04 +00:00
opt_share	Did share, opt_share and fsm	2026-04-16 11:00:44 +02:00
peepopt	Converted some more	2026-04-16 11:00:44 +02:00
proc	Merge branch 'main' into nella/latch-toggle	2026-07-08 11:41:08 +02:00
pyosys	End of file fix	2026-06-23 07:23:41 +02:00
realmath	Cleanup	2026-04-16 11:00:44 +02:00
rpc	Make out of tree build testing possible	2026-05-19 14:26:07 +02:00
rtlil	Testcases for new truncation checks	2026-07-10 14:37:19 +02:00
sat	Remove trailing whitespaces	2026-06-23 07:24:59 +02:00
sdc	Remove trailing whitespaces	2026-06-23 07:24:59 +02:00
select	Converted some more	2026-04-16 11:00:44 +02:00
share	Did share, opt_share and fsm	2026-04-16 11:00:44 +02:00
sim	Remove trailing whitespaces	2026-06-23 07:24:59 +02:00
simple	End of file fix	2026-06-23 07:23:41 +02:00
simple_abc9	Convert autotest script wrapper	2026-04-16 11:00:44 +02:00
smv	End of file fix	2026-06-23 07:23:41 +02:00
sva	End of file fix	2026-06-23 07:23:41 +02:00
svinterfaces	Cleanup	2026-04-16 11:00:44 +02:00
svtypes	Remove trailing whitespaces	2026-06-23 07:24:59 +02:00
symfpu	symfpu: Run pre-commit	2026-07-15 14:56:11 +12:00
techmap	mul2dsp: normalize operand order	2026-07-15 16:21:07 +02:00
tools	End of file fix	2026-06-23 07:23:41 +02:00
unit	Tescases for Width Limit, Resize and Overflow	2026-07-09 14:34:56 +02:00
various	autoname: selection determines what gets renamed, not the name it gets renamed to	2026-07-17 22:48:46 +02:00
verific	Remove trailing whitespaces	2026-06-23 07:24:59 +02:00
verilog	Rm.	2026-07-07 04:03:17 +02:00
vloghtb	End of file fix	2026-06-23 07:23:41 +02:00
write_verilog	tests: Add mixed_upto write_verilog test	2026-06-19 11:20:01 +12:00
xprop	Update CI scripts for CMake	2026-06-03 08:58:11 +00:00
.gitignore	Save results, and create summary and report	2026-04-16 11:00:44 +02:00
common.mk	Add VERBOSE (and V) option to Makefiles	2026-06-15 14:48:11 +02:00
gen_tests_makefile.py	Add VERBOSE (and V) option to Makefiles	2026-06-15 14:48:11 +02:00
Makefile	symfpu: Add flags	2026-07-15 14:50:25 +12:00
pass-fuzzing.md	Remove trailing whitespaces	2026-06-23 07:24:59 +02:00