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Code Activity
yosys/techlibs/intel_le/common
History
Artur Swiderski dd9c11c035 fix input -> output timings
2020-12-06 14:07:41 +01:00
..
abc9_map.v start implementing support for intel le based logic devices 2020-10-10 19:08:54 +02:00
abc9_model.v start implementing support for intel le based logic devices 2020-10-10 19:08:54 +02:00
abc9_unmap.v start implementing support for intel le based logic devices 2020-10-10 19:08:54 +02:00
arith_le_map.v minor changes 2020-12-06 12:24:44 +01:00
bram_m9k.txt minor fix 2020-12-06 12:32:30 +01:00
dff_map.v start implementing support for intel le based logic devices 2020-10-10 19:08:54 +02:00
dff_sim.v remove cycloneive 2020-11-14 18:05:14 +01:00
le_map.v before some refactoring 2020-10-31 00:59:48 +01:00
le_sim.v fix input -> output timings 2020-12-06 14:07:41 +01:00
megafunction_bb.v before some refactoring 2020-10-31 00:59:48 +01:00
mem_sim.v minor changes 2020-12-06 12:24:44 +01:00
quartus_rename.v remove cycloneive 2020-11-14 18:05:14 +01:00