mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-22 16:45:32 +00:00
Code Activity

minor changes

Browse source
This commit is contained in:
Artur Swiderski 2020-12-06 12:24:44 +01:00
parent 1452cd88e8
commit cab1f9872b
4 changed files with 18 additions and 40 deletions
Download patch file Download diff file Expand all files Collapse all files

23
techlibs/intel_le/common/arith_le_map.v
View file

@ -39,17 +39,7 @@ generate
if (_TECHMAP_CONSTMSK_CI_ == 1) begin
assign LE_CARRY[0] = _TECHMAP_CONSTVAL_CI_;
end else begin
/*
MISTRAL_ALUT_ARITH #(
.LUT(16'b1010_1010_1010_1010), // Q = A
) le_start (
.A(CI), .B(1'b1), .C(1'b1), .D0(1'b1), .D1(1'b1),
.CI(1'b0),
.SO(),
.CO(LE_CARRY[0])
);
*/
assign LE_CARRY[0] = CI;
end
endgenerate
@ -57,21 +47,10 @@ endgenerate
// Carry chain
genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
/*
MISTRAL_ALUT_ARITH #(
.LUT(16'b0110_0110_0110_0110), // Q = A ? ~B : B
.sum_lutc_input("cin")
) le_not_i (
.A(BI), .B(BX[i]), .C(1'b0), .D(1'b0),
.CI(1'b0),
.SO(BTOADDER[i]),
.CO()
);
*/
MISTRAL_ALUT_ARITH #(
.LUT(16'b1001_0110_1110_1000), // SUM = A xor B xor CI
// CARRYi+1 = A and B or A and CI or B and CI
// CARRYi+1 = A and B or A and CI or B and CI
) le_i (
.A(AA[i]), .B(BB[i]), .C(1'b1), .D(1'b1),

12
techlibs/intel_le/common/le_sim.v
View file

@ -34,7 +34,7 @@ module MISTRAL_ALUT4(input A, B, C, D, output Q);
parameter [15:0] LUT = 16'h0000;
`ifdef cycloneiv
`ifdef cycloneiv
specify
(A => Q) = 319;
(B => Q) = 323;
@ -98,7 +98,7 @@ module MISTRAL_ALUT_ARITH(input A, B, C, D, (* abc9_carry *) input CI, output SO
parameter LUT = 16'h0000;
`ifdef cycloneiv
`ifdef cycloneiv
specify
(A => SO) = 1342;
(B => SO) = 1323;
@ -106,11 +106,9 @@ specify
(D => SO) = 887;
(CI => SO) = 368;
(A => CO) = 1082;
(B => CO) = 1062;
(C => CO) = 813;
(D => CO) = 866;
(CI => CO) = 36; // Divided by 2 to account for there being two ALUT_ARITHs in an ALM)
(A => CO) = 376;
(B => CO) = 385;
(CI => CO) = 200;
endspecify
`endif
wire q0, q1;

4
techlibs/intel_le/common/mem_sim.v
View file

@ -5,8 +5,8 @@
module MISTRAL_M9K(CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CFG_ABITS = 10;
parameter CFG_DBITS = 10;
parameter CFG_ABITS = 9;
parameter CFG_DBITS = 9;
input CLK1;
input [CFG_ABITS-1:0] A1ADDR, B1ADDR;

19
tests/arch/intel_le/mux.ys
View file

@ -17,8 +17,10 @@ proc
equiv_opt -assert -map +/intel_le/common/le_sim.v synth_intel_le -family cycloneiv # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux4 # Constrain all select calls below inside the top module
select -assert-count 3 t:MISTRAL_ALUT3
select -assert-none t:MISTRAL_ALUT3 %% t:* %D
select -assert-count 1 t:MISTRAL_ALUT3
select -assert-count 2 t:MISTRAL_ALUT4
select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 %% t:* %D
design -load read
@ -27,9 +29,9 @@ proc
equiv_opt -assert -map +/intel_le/common/le_sim.v synth_intel_le -family cycloneiv # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux8 # Constrain all select calls below inside the top module
select -assert-count 3 t:MISTRAL_ALUT3
select -assert-count 3 t:MISTRAL_ALUT4
select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 %% t:* %D
select -assert-count 2 t:MISTRAL_ALUT2
select -assert-count 5 t:MISTRAL_ALUT4
select -assert-none t:MISTRAL_ALUT2 t:MISTRAL_ALUT4 %% t:* %D
design -load read
@ -38,8 +40,7 @@ proc
equiv_opt -assert -map +/intel_le/common/le_sim.v synth_intel_le -family cycloneiv # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module
select -assert-count 1 t:MISTRAL_ALUT2
select -assert-max 6 t:MISTRAL_ALUT3
select -assert-max 7 t:MISTRAL_ALUT4
select -assert-none t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 %% t:* %D
select -assert-max 4 t:MISTRAL_ALUT3
select -assert-max 9 t:MISTRAL_ALUT4
select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 %% t:* %D