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remove cycloneive

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This commit is contained in:
Artur Swiderski 2020-11-14 18:05:14 +01:00
parent f8bcb78a32
commit 1452cd88e8
15 changed files with 24 additions and 333 deletions
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2
techlibs/intel_alm/common/alm_sim.v
View file

@ -169,7 +169,7 @@ module MISTRAL_ALUT3(input A, B, C, output Q);
parameter [7:0] LUT = 8'h00;
`ifdef cyclonev
`ifdef cyclonev
specify
(A => Q) = 510;
(B => Q) = 400;

26
techlibs/intel_le/common/dff_sim.v
View file

@ -1,10 +1,3 @@
// The four D flip-flops (DFFs) in a Cyclone V/10GX Adaptive Logic Module (ALM)
// act as one-bit memory cells that can be placed very flexibly (wherever there's
// an ALM); each flop is represented by a MISTRAL_FF cell.
//
// The flops in these chips are rather flexible in some ways, but in practice
// quite crippled by FPGA standards.
//
// What the flops can do
// ---------------------
// The core flop acts as a single-bit memory that initialises to zero at chip
@ -60,7 +53,7 @@ module MISTRAL_FF(
output reg Q
);
`ifdef cycloneiv
`ifdef cycloneiv
specify
if (ENA && ACLR !== 1'b0 && !SCLR && !SLOAD) (posedge CLK => (Q : DATAIN)) = 731;
if (ENA && SCLR) (posedge CLK => (Q : 1'b0)) = 890;
@ -75,23 +68,6 @@ specify
if (ACLR === 1'b0) (ACLR => Q) = 282;
endspecify
`endif
`ifdef cycloneive
specify
// TODO (long-term): investigate these numbers.
// It seems relying on the Quartus Timing Analyzer was not the best idea; it's too fiddly.
if (ENA && ACLR !== 1'b0 && !SCLR && !SLOAD) (posedge CLK => (Q : DATAIN)) = 219;
if (ENA && SCLR) (posedge CLK => (Q : 1'b0)) = 219;
if (ENA && !SCLR && SLOAD) (posedge CLK => (Q : SDATA)) = 219;
$setup(DATAIN, posedge CLK, 268);
$setup(ENA, posedge CLK, 268);
$setup(SCLR, posedge CLK, 268);
$setup(SLOAD, posedge CLK, 268);
$setup(SDATA, posedge CLK, 268);
if (ACLR === 1'b0) (ACLR => Q) = 0;
endspecify
`endif
initial begin
// Altera flops initialise to zero.

130
techlibs/intel_le/common/le_sim.v
View file

@ -1,81 +1,32 @@
// The core logic primitive of the Cyclone V/10GX is the Adaptive Logic Module
// (ALM). Each ALM is made up of an 8-input, 2-output look-up table, covered
// in this file, connected to combinational outputs, a carry chain, and four
// D flip-flops (which are covered as MISTRAL_FF in dff_sim.v).
// The core logic primitive of the Cyclone IVE/IVGX is the Logic Element
// (LE). Each LE is made up of an 4-input, 1-output look-up table, covered
// in this file, connected to combinational outputs, a carry chain, and one
// D flip-flop (which are covered as MISTRAL_FF in dff_sim.v).
//
// The ALM is vertically symmetric, so I find it helps to think in terms of
// half-ALMs, as that's predominantly the unit that synth_intel_alm uses.
//
// ALMs are quite flexible, having multiple modes.
// LEs are have two modes of operation
//
// Normal (combinational) mode
// ---------------------------
// The ALM can implement:
// - a single 6-input function (with the other inputs usable for flip-flop access)
// - two 5-input functions that share two inputs
// - a 5-input and a 4-input function that share one input
// - a 5-input and a 3-or-less-input function that share no inputs
// - two 4-or-less-input functions that share no inputs
// The LE can implement:
// - a single 4-input(or less) function
//
// Normal-mode functions are represented as MISTRAL_ALUTN cells with N inputs.
// It would be possible to represent a normal mode function as a single cell -
// the vendor cyclone{v,10gx}_lcell_comb cell does exactly that - but I felt
// it was more user-friendly to print out the specific function sizes
// separately.
//
// With the exception of MISTRAL_ALUT6, you can think of two normal-mode cells
// fitting inside a single ALM.
//
// Extended (7-input) mode
// -----------------------
// The ALM can also fit a 7-input function made of two 5-input functions that
// share four inputs, multiplexed by another input.
//
// Because this can't accept arbitrary 7-input functions, Yosys can't handle
// it, so it doesn't have a cell, but I would likely call it MISTRAL_ALUT7(E?)
// if it did, and it would take up a full ALM.
//
// It might be possible to add an extraction pass to examine all ALUT5 cells
// that feed into ALUT3 cells to see if they can be combined into an extended
// ALM, but I don't think it will be worth it.
//
// Arithmetic mode
// ---------------
// In arithmetic mode, each half-ALM uses its carry chain to perform fast addition
// of two four-input functions that share three inputs. Oddly, the result of
// one of the functions is inverted before being added (you can see this as
// the dot on a full-adder input of Figure 1-8 in the Handbook).
// In arithmetic mode, LE implements two bit adder and carry chain
// It can drive either registered or unregistered output.
//
// The cell for an arithmetic-mode half-ALM is MISTRAL_ALM_ARITH. One idea
// I've had (or rather was suggested by mwk) is that functions that feed into
// arithmetic-mode cells could be packed directly into the arithmetic-mode
// cell as a function, which reduces the number of ALMs needed.
// The cell for an arithmetic-mode is MISTRAL_ALM_ARITH.
//
// Shared arithmetic mode
// ----------------------
// Shared arithmetic mode looks a lot like arithmetic mode, but here the
// output of every other four-input function goes to the input of the adder
// the next bit along. What this means is that adding three bits together can
// be done in an ALM, because functions can be used to implement addition that
// then feeds into the carry chain. This means that three bits can be added per
// ALM, as opposed to two in the arithmetic mode.
//
// Shared arithmetic mode doesn't currently have a cell, but I intend to add
// it as MISTRAL_ALM_SHARED, and have it occupy a full ALM. Because it adds
// three bits per cell, it makes addition shorter and use less ALMs, but
// I don't know enough to tell whether it's more efficient to use shared
// arithmetic mode to shorten the carry chain, or plain arithmetic mode with
// the functions packed in.
`default_nettype none
// Cyclone V LUT output timings (picoseconds):
//
// CARRY A B C D E F G
// COMBOUT - 605 583 510 512 - 97 400 (LUT6)
// COMBOUT - 602 583 457 510 302 93 483 (LUT7)
// SUMOUT 368 1342 1323 887 927 - 785 -
// CARRYOUT 71 1082 1062 866 813 - 1198 -
// CARRY A B C D
// COMBOUT ?408? 319 323 211 114
// CARRYOUT 200 376 385 ? -
(* abc9_lut=1, lib_whitebox *)
@ -83,22 +34,14 @@ module MISTRAL_ALUT4(input A, B, C, D, output Q);
parameter [15:0] LUT = 16'h0000;
`ifdef cycloneiv
`ifdef cycloneiv
specify
(A => Q) = 510;
(B => Q) = 512;
(C => Q) = 400;
(D => Q) = 97;
(A => Q) = 319;
(B => Q) = 323;
(C => Q) = 211;
(D => Q) = 114;
endspecify
`endif
`ifdef cycloneive
specify
(A => Q) = 510;
(B => Q) = 512;
(C => Q) = 400;
(D => Q) = 97;
endspecify
`endif
assign Q = LUT >> {D, C, B, A};
@ -110,20 +53,13 @@ module MISTRAL_ALUT3(input A, B, C, output Q);
parameter [7:0] LUT = 8'h00;
`ifdef cycloneiv
`ifdef cycloneiv
specify
(A => Q) = 510;
(B => Q) = 400;
(C => Q) = 97;
endspecify
`endif
`ifdef cycloneive
specify
(A => Q) = 510;
(B => Q) = 400;
(C => Q) = 97;
endspecify
`endif
assign Q = LUT >> {C, B, A};
endmodule
@ -134,18 +70,12 @@ module MISTRAL_ALUT2(input A, B, output Q);
parameter [3:0] LUT = 4'h0;
`ifdef cycloneiv
`ifdef cycloneiv
specify
(A => Q) = 400;
(B => Q) = 97;
endspecify
`endif
`ifdef cycloneive
specify
(A => Q) = 400;
(B => Q) = 97;
endspecify
`endif
assign Q = LUT >> {B, A};
endmodule
@ -159,11 +89,6 @@ specify
(A => Q) = 97;
endspecify
`endif
`ifdef cycloneive
specify
(A => Q) = 97;
endspecify
`endif
assign Q = ~A;
endmodule
@ -188,21 +113,6 @@ specify
(CI => CO) = 36; // Divided by 2 to account for there being two ALUT_ARITHs in an ALM)
endspecify
`endif
`ifdef cycloneive
specify
(A => SO) = 1342;
(B => SO) = 1323;
(C => SO) = 927;
(D => SO) = 887;
(CI => SO) = 368;
(A => CO) = 1082;
(B => CO) = 1062;
(C => CO) = 813;
(D => CO) = 866;
(CI => CO) = 36; // Divided by 2 to account for there being two ALUT_ARITHs in an ALM)
endspecify
`endif
wire q0, q1;

4
techlibs/intel_le/common/quartus_rename.v
View file

@ -2,10 +2,6 @@
`define LCELL cycloneiv_lcell_comb
`define M9K cycloneiv_ram_block
`endif
`ifdef cycloneive
`define LCELL cycloneive_lcell_comb
`define M9K cycloneive_ram_block
`endif
module __MISTRAL_VCC(output Q);

5
techlibs/intel_le/synth_intel_le.cc
View file

@ -43,7 +43,6 @@ struct SynthIntelLEPass : public ScriptPass {
log(" -family <family>\n");
log(" target one of:\n");
log(" \"cycloneiv\" - Cyclone IV (default)\n");
log(" \"cycloneive\" - Cyclone IV E \n");
log("\n");
log(" -vqm <file>\n");
log(" write the design to the specified Verilog Quartus Mapping File. Writing of an\n");
@ -145,7 +144,7 @@ struct SynthIntelLEPass : public ScriptPass {
if (!design->full_selection())
log_cmd_error("This command only operates on fully selected designs!\n");
if (family_opt == "cycloneiv" or family_opt == "cycloneive") {
if (family_opt == "cycloneiv") {
bram_type = "m9k";
} else {
log_cmd_error("Invalid family specified: '%s'\n", family_opt.c_str());
@ -167,7 +166,7 @@ struct SynthIntelLEPass : public ScriptPass {
}
if (check_label("begin")) {
if (family_opt == "cycloneiv" or family_opt == "cycloneive")
if (family_opt == "cycloneiv")
run(stringf("read_verilog -sv -lib +/intel_le/cycloneiv/cells_sim.v"));
run(stringf("read_verilog -specify -lib -D %s +/intel_le/common/le_sim.v", family_opt.c_str()));
run(stringf("read_verilog -specify -lib -D %s +/intel_le/common/dff_sim.v", family_opt.c_str()));

9
tests/arch/intel_le/add_sub.ys
View file

@ -10,12 +10,3 @@ select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT_ARITH %% t:* %D
design -reset
read_verilog ../common/add_sub.v
hierarchy -top top
equiv_opt -assert -map +/intel_le/common/le_sim.v synth_intel_le -family cycloneive # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 8 t:MISTRAL_ALUT_ARITH
select -assert-count 4 t:MISTRAL_NOT
select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT_ARITH %% t:* %D

45
tests/arch/intel_le/adffs.ys
View file

@ -12,18 +12,6 @@ select -assert-count 1 t:MISTRAL_NOT
select -assert-none t:MISTRAL_FF t:MISTRAL_NOT %% t:* %D
design -load read
hierarchy -top adff
proc
equiv_opt -async2sync -assert -map +/intel_le/common/le_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cycloneive # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd adff # Constrain all select calls below inside the top module
select -assert-count 1 t:MISTRAL_FF
select -assert-count 1 t:MISTRAL_NOT
select -assert-none t:MISTRAL_FF t:MISTRAL_NOT %% t:* %D
design -load read
hierarchy -top adffn
proc
@ -35,17 +23,6 @@ select -assert-count 1 t:MISTRAL_FF
select -assert-none t:MISTRAL_FF %% t:* %D
design -load read
hierarchy -top adffn
proc
equiv_opt -async2sync -assert -map +/intel_le/common/le_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cycloneive # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd adffn # Constrain all select calls below inside the top module
select -assert-count 1 t:MISTRAL_FF
select -assert-none t:MISTRAL_FF %% t:* %D
design -load read
hierarchy -top dffs
proc
@ -58,18 +35,6 @@ select -assert-count 1 t:MISTRAL_ALUT2
select -assert-none t:MISTRAL_FF t:MISTRAL_ALUT2 %% t:* %D
design -load read
hierarchy -top dffs
proc
equiv_opt -async2sync -assert -map +/intel_le/common/le_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cycloneive # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffs # Constrain all select calls below inside the top module
select -assert-count 1 t:MISTRAL_FF
select -assert-count 1 t:MISTRAL_ALUT2
select -assert-none t:MISTRAL_FF t:MISTRAL_ALUT2 %% t:* %D
design -load read
hierarchy -top ndffnr
proc
@ -82,13 +47,3 @@ select -assert-count 2 t:MISTRAL_NOT
select -assert-none t:MISTRAL_FF t:MISTRAL_NOT %% t:* %D
design -load read
hierarchy -top ndffnr
proc
equiv_opt -async2sync -assert -map +/intel_le/common/le_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cycloneive # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd ndffnr # Constrain all select calls below inside the top module
select -assert-count 1 t:MISTRAL_FF
select -assert-count 2 t:MISTRAL_NOT
select -assert-none t:MISTRAL_FF t:MISTRAL_NOT %% t:* %D

12
tests/arch/intel_le/counter.ys
View file

@ -14,15 +14,3 @@ select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT_ARITH t:MISTRAL_FF %% t:* %D
design -reset
read_verilog ../common/counter.v
hierarchy -top top
proc
flatten
equiv_opt -async2sync -map +/intel_le/common/le_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cycloneive # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 2 t:MISTRAL_NOT
select -assert-count 8 t:MISTRAL_ALUT_ARITH
select -assert-count 8 t:MISTRAL_FF
select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT_ARITH t:MISTRAL_FF %% t:* %D

19
tests/arch/intel_le/dffs.ys
View file

@ -10,16 +10,6 @@ select -assert-count 1 t:MISTRAL_FF
select -assert-none t:MISTRAL_FF %% t:* %D
design -load read
hierarchy -top dff
proc
equiv_opt -async2sync -assert -map +/intel_le/common/le_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cycloneive # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
select -assert-count 1 t:MISTRAL_FF
select -assert-none t:MISTRAL_FF %% t:* %D
design -load read
hierarchy -top dffe
@ -32,12 +22,3 @@ select -assert-count 1 t:MISTRAL_FF
select -assert-none t:MISTRAL_FF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -async2sync -assert -map +/intel_le/common/le_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cycloneive # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
select -assert-count 1 t:MISTRAL_FF
select -assert-none t:MISTRAL_FF %% t:* %D

19
tests/arch/intel_le/fsm.ys
View file

@ -19,22 +19,3 @@ select -assert-max 9 t:MISTRAL_ALUT4 #
select -assert-none t:MISTRAL_FF t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 %% t:* %D
design -reset
read_verilog ../common/fsm.v
hierarchy -top fsm
proc
flatten
equiv_opt -run :prove -map +/intel_le/common/le_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cycloneive
async2sync
miter -equiv -make_assert -flatten gold gate miter
sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd fsm # Constrain all select calls below inside the top module
select -assert-count 6 t:MISTRAL_FF
select -assert-max 1 t:MISTRAL_NOT
select -assert-max 5 t:MISTRAL_ALUT2 #
select -assert-max 1 t:MISTRAL_ALUT3
select -assert-max 9 t:MISTRAL_ALUT4 #
select -assert-none t:MISTRAL_FF t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 %% t:* %D

11
tests/arch/intel_le/logic.ys
View file

@ -12,14 +12,3 @@ select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT4 %% t:* %D
design -reset
read_verilog ../common/logic.v
hierarchy -top top
proc
equiv_opt -assert -map +/intel_le/common/le_sim.v synth_intel_le -family cycloneive # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:MISTRAL_NOT
select -assert-count 6 t:MISTRAL_ALUT2
select -assert-count 2 t:MISTRAL_ALUT4
select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT4 %% t:* %D

42
tests/arch/intel_le/mux.ys
View file

@ -11,16 +11,6 @@ select -assert-count 1 t:MISTRAL_ALUT3
select -assert-none t:MISTRAL_ALUT3 %% t:* %D
design -load read
hierarchy -top mux2
proc
equiv_opt -assert -map +/intel_le/common/le_sim.v synth_intel_le -family cycloneive # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux2 # Constrain all select calls below inside the top module
select -assert-count 1 t:MISTRAL_ALUT3
select -assert-none t:MISTRAL_ALUT3 %% t:* %D
design -load read
hierarchy -top mux4
proc
@ -31,16 +21,6 @@ select -assert-count 3 t:MISTRAL_ALUT3
select -assert-none t:MISTRAL_ALUT3 %% t:* %D
design -load read
hierarchy -top mux4
proc
equiv_opt -assert -map +/intel_le/common/le_sim.v synth_intel_le -family cycloneive # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux4 # Constrain all select calls below inside the top module
select -assert-count 3 t:MISTRAL_ALUT3
select -assert-none t:MISTRAL_ALUT3 %% t:* %D
design -load read
hierarchy -top mux8
proc
@ -52,17 +32,6 @@ select -assert-count 3 t:MISTRAL_ALUT4
select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 %% t:* %D
design -load read
hierarchy -top mux8
proc
equiv_opt -assert -map +/intel_le/common/le_sim.v synth_intel_le -family cycloneive # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux8 # Constrain all select calls below inside the top module
select -assert-count 3 t:MISTRAL_ALUT3
select -assert-count 3 t:MISTRAL_ALUT4
select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 %% t:* %D
design -load read
hierarchy -top mux16
proc
@ -74,14 +43,3 @@ select -assert-max 6 t:MISTRAL_ALUT3
select -assert-max 7 t:MISTRAL_ALUT4
select -assert-none t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 %% t:* %D
design -load read
hierarchy -top mux16
proc
equiv_opt -assert -map +/intel_le/common/le_sim.v synth_intel_le -family cycloneive # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module
select -assert-count 1 t:MISTRAL_ALUT2
select -assert-max 6 t:MISTRAL_ALUT3
select -assert-max 7 t:MISTRAL_ALUT4
select -assert-none t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 %% t:* %D

12
tests/arch/intel_le/quartus_ice.ys
View file

@ -12,15 +12,3 @@ synth_intel_le -family cycloneiv -quartus
select -assert-none w:*[* w:*]*
design -reset
read_verilog <<EOT
// Verilog has syntax for raw identifiers, where you start it with \ and end it with a space.
// This test crashes Quartus due to it parsing \a[10] as a wire slice and not a raw identifier.
module top();
(* keep *) wire [31:0] \a[10] ;
(* keep *) wire b;
assign b = \a[10] [31];
endmodule
EOT
synth_intel_le -family cycloneive -quartus
select -assert-none w:*[* w:*]*

9
tests/arch/intel_le/shifter.ys
View file

@ -10,12 +10,3 @@ select -assert-none t:MISTRAL_FF %% t:* %D
design -reset
read_verilog ../common/shifter.v
hierarchy -top top
proc
flatten
equiv_opt -async2sync -assert -map +/intel_le/common/le_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cycloneive # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 8 t:MISTRAL_FF
select -assert-none t:MISTRAL_FF %% t:* %D

12
tests/arch/intel_le/tribuf.ys
View file

@ -13,15 +13,3 @@ select -assert-none t:$_TBUF_ %% t:* %D
design -reset
read_verilog ../common/tribuf.v
hierarchy -top tristate
proc
tribuf
flatten
synth
equiv_opt -assert -map +/simcells.v synth_intel_le -family cycloneive # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd tristate # Constrain all select calls below inside the top module
#Internal cell type used. Need support it.
select -assert-count 1 t:$_TBUF_
select -assert-none t:$_TBUF_ %% t:* %D