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https://github.com/YosysHQ/yosys
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116 lines
2.8 KiB
Verilog
116 lines
2.8 KiB
Verilog
`ifdef cycloneiv
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`define LCELL cycloneiv_lcell_comb
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`define M9K cycloneiv_ram_block
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`endif
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module __MISTRAL_VCC(output Q);
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MISTRAL_ALUT2 #(.LUT(4'b1111)) _TECHMAP_REPLACE_ (.A(1'b1), .B(1'b1), .Q(Q));
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endmodule
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module __MISTRAL_GND(output Q);
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MISTRAL_ALUT2 #(.LUT(4'b0000)) _TECHMAP_REPLACE_ (.A(1'b1), .B(1'b1), .Q(Q));
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endmodule
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module MISTRAL_FF(input DATAIN, CLK, ACLR, ENA, SCLR, SLOAD, SDATA, output reg Q);
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dffeas #(.power_up("low"), .is_wysiwyg("true")) _TECHMAP_REPLACE_ (.d(DATAIN), .clk(CLK), .clrn(ACLR), .ena(ENA), .sclr(SCLR), .sload(SLOAD), .asdata(SDATA), .q(Q));
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endmodule
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module MISTRAL_ALUT4(input A, B, C, D, output Q);
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parameter [15:0] LUT = 16'h0000;
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`LCELL #(.lut_mask(LUT),.sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .combout(Q));
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endmodule
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module MISTRAL_ALUT3(input A, B, C, output Q);
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parameter [7:0] LUT = 8'h00;
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`LCELL #(.lut_mask({2{LUT}}),.sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .combout(Q));
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endmodule
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module MISTRAL_ALUT2(input A, B, output Q);
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parameter [3:0] LUT = 4'h0;
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`LCELL #(.lut_mask({4{LUT}}),.sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .combout(Q));
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endmodule
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module MISTRAL_NOT(input A, output Q);
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//NOT _TECHMAP_REPLACE_ (.IN(A), .OUT(Q));
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assign Q = ~A;
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endmodule
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module MISTRAL_ALUT_ARITH(input A, B, C, D, CI, output SO, CO);
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parameter LUT = 16'h0000;
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`LCELL #(.lut_mask({LUT}),.sum_lutc_input("cin")) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .cin(CI), .combout(SO), .cout(CO));
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endmodule
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module MISTRAL_M9K(A1ADDR, A1DATA, A1EN, CLK1, B1ADDR, B1DATA, B1EN);
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parameter CFG_ABITS = 9;
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parameter CFG_DBITS = 9;
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parameter _TECHMAP_CELLNAME_ = "";
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input [CFG_ABITS-1:0] A1ADDR, B1ADDR;
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input [CFG_DBITS-1:0] A1DATA;
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input CLK1, A1EN, B1EN;
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output [CFG_DBITS-1:0] B1DATA;
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// The M9K has mem_init[01234] parameters which would let
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// you initialise the RAM cell via hex literals. If they were implemented.
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`M9K #(
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.operation_mode("dual_port"),
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.logical_ram_name(_TECHMAP_CELLNAME_),
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.port_a_address_width(CFG_ABITS),
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.port_a_data_width(CFG_DBITS),
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.port_a_logical_ram_depth(2**CFG_ABITS),
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.port_a_logical_ram_width(CFG_DBITS),
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.port_a_first_address(0),
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.port_a_last_address(2**CFG_ABITS - 1),
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.port_a_first_bit_number(0),
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.port_b_address_width(CFG_ABITS),
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.port_b_data_width(CFG_DBITS),
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.port_b_logical_ram_depth(2**CFG_ABITS),
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.port_b_logical_ram_width(CFG_DBITS),
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.port_b_first_address(0),
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.port_b_last_address(2**CFG_ABITS - 1),
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.port_b_first_bit_number(0),
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.port_b_address_clock("clock0"),
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.port_b_read_enable_clock("clock0")
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) _TECHMAP_REPLACE_ (
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.portaaddr(A1ADDR),
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.portadatain(A1DATA),
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.portawe(A1EN),
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.portbaddr(B1ADDR),
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.portbdataout(B1DATA),
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.portbre(B1EN),
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.clk0(CLK1)
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);
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endmodule
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