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.gitignore
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Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files.
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2025-07-22 10:38:38 +00:00 |
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absurd_width.ys
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absurd_width_const.ys
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always_comb_latch_1.ys
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always_comb_latch_2.ys
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always_comb_latch_3.ys
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always_comb_latch_4.ys
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always_comb_nolatch_1.ys
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always_comb_nolatch_2.ys
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always_comb_nolatch_3.ys
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always_comb_nolatch_4.ys
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always_comb_nolatch_5.ys
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always_comb_nolatch_6.ys
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asgn_expr.sv
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fix width of post-increment/decrement expressions
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2023-09-18 23:46:06 -04:00 |
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asgn_expr.ys
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tests: Run async2sync before sat and/or sim to handle $check cells
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2024-02-01 16:14:11 +01:00 |
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asgn_expr_not_proc_1.ys
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sv: support assignments within expressions
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2023-09-05 22:27:55 -04:00 |
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asgn_expr_not_proc_2.ys
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sv: support assignments within expressions
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2023-09-05 22:27:55 -04:00 |
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asgn_expr_not_proc_3.ys
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sv: support assignments within expressions
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2023-09-05 22:27:55 -04:00 |
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asgn_expr_not_proc_4.ys
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sv: support assignments within expressions
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2023-09-05 22:27:55 -04:00 |
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asgn_expr_not_proc_5.ys
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sv: support assignments within expressions
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2023-09-05 22:27:55 -04:00 |
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asgn_expr_not_sv_1.ys
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sv: support assignments within expressions
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2023-09-05 22:27:55 -04:00 |
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asgn_expr_not_sv_2.ys
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sv: support assignments within expressions
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2023-09-05 22:27:55 -04:00 |
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asgn_expr_not_sv_3.ys
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sv: support assignments within expressions
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2023-09-05 22:27:55 -04:00 |
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asgn_expr_not_sv_4.ys
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sv: support assignments within expressions
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2023-09-05 22:27:55 -04:00 |
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assign_to_reg.ys
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Remove references to ilang
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2024-11-05 12:36:31 +13:00 |
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atom_type_signedness.ys
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tests: remove -seq 1 from sat with -tempinduct where possible
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2025-09-08 18:04:32 +02:00 |
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block_end_label_only.ys
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block_end_label_wrong.ys
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block_labels.ys
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Standard compliance for tests/verilog/block_labels.ys
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2023-05-21 16:38:14 -04:00 |
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bug656.v
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bug656.ys
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bug2037.ys
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bug2042-sv.ys
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tests: Run async2sync before sat and/or sim to handle $check cells
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2024-02-01 16:14:11 +01:00 |
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bug2042.ys
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bug2493.ys
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bug4785.ys
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simplify: Skip AST_PRIMITIVE in AST_CELLARRAY
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2025-03-25 12:15:54 +13:00 |
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conflict_assert.ys
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conflict_cell_memory.ys
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conflict_interface_port.ys
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conflict_memory_wire.ys
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conflict_pwire.ys
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conflict_wire_memory.ys
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const_arst.ys
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const_sr.ys
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constparser_f.ys
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fixup! const2ast: add diagnostics tests
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2025-06-16 22:50:31 +02:00 |
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constparser_f_file.sv
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const2ast: add diagnostics tests
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2025-06-16 21:48:12 +02:00 |
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constparser_f_file.ys
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const2ast: add diagnostics tests
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2025-06-16 21:48:12 +02:00 |
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constparser_g.ys
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const2ast: add diagnostics tests
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2025-06-16 21:48:12 +02:00 |
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delay_mintypmax.ys
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delay_risefall.ys
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delay_time_scale.ys
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doubleslash.ys
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dynamic_range_lhs.sh
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Include x bits in test of lhs dynamic part-select
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2024-01-10 20:28:36 +01:00 |
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dynamic_range_lhs.v
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Include x bits in test of lhs dynamic part-select
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2024-01-10 20:28:36 +01:00 |
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fcall_smoke.ys
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simplify: add smoke test for system function calls
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2025-08-12 12:59:31 +02:00 |
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for_decl_no_init.ys
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for_decl_no_sv.ys
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for_decl_shadow.sv
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for_decl_shadow.ys
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func_arg_mismatch_1.ys
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func_arg_mismatch_2.ys
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func_arg_mismatch_3.ys
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func_arg_mismatch_4.ys
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func_task_arg_copying.ys
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tests: add tests for task/function argument input/output copying
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2025-05-31 01:21:06 +01:00 |
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func_tern_hint.sv
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func_tern_hint.ys
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tests: Run async2sync before sat and/or sim to handle $check cells
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2024-02-01 16:14:11 +01:00 |
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func_typename_ret.sv
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func_typename_ret.ys
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func_upto.sv
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func_upto.ys
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tests: Run async2sync before sat and/or sim to handle $check cells
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2024-02-01 16:14:11 +01:00 |
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gen_block_end_label_only.ys
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gen_block_end_label_wrong.ys
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genblk_case.v
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genblk_case.ys
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genblk_port_decl.ys
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genfor_decl_no_init.ys
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genfor_decl_no_sv.ys
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genvar_loop_decl_1.sv
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genvar_loop_decl_1.ys
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genvar_loop_decl_2.sv
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genvar_loop_decl_2.ys
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genvar_loop_decl_3.sv
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genvar_loop_decl_3.ys
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global_parameter.ys
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hidden_decl.ys
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ifdef_nest.ys
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ifdef_unterminated.ys
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incdec.ys
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tests: add tests for verilog pre/post increment/decrement in expressions
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2025-05-30 14:38:25 +01:00 |
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include_self.v
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include_self.ys
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int_types.sv
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int_types.ys
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tests: remove -seq 1 from sat with -tempinduct where possible
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2025-09-08 18:04:32 +02:00 |
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localparam_no_default_1.ys
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localparam_no_default_2.ys
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macro_arg_tromp.sv
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macro_arg_tromp.ys
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macro_unapplied.ys
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macro_unapplied_newline.ys
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mem_bounds.sv
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mem_bounds.ys
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tests: remove -seq 1 from sat with -tempinduct where possible
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2025-09-08 18:04:32 +02:00 |
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module_end_label.ys
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net_types.sv
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net_types.ys
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tests: Run async2sync before sat and/or sim to handle $check cells
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2024-02-01 16:14:11 +01:00 |
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package_end_label.ys
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package_import_separate.sv
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use more standard naming conventions
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2025-08-06 15:39:30 -04:00 |
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package_import_separate.ys
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add newline - whitespace
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2025-08-06 19:00:11 -04:00 |
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package_import_separate_module.sv
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use more standard naming conventions
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2025-08-06 15:39:30 -04:00 |
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package_task_func.sv
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package_task_func.ys
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tests: Run async2sync before sat and/or sim to handle $check cells
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2024-02-01 16:14:11 +01:00 |
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param_default.ys
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tests: Add default param test file
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2025-05-05 10:18:52 +12:00 |
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param_int_types.sv
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param_int_types.ys
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param_no_default.sv
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param_no_default.ys
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tests: remove -seq 1 from sat with -tempinduct where possible
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2025-09-08 18:04:32 +02:00 |
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param_no_default_not_svmode.ys
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param_no_default_unbound_1.ys
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param_no_default_unbound_2.ys
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param_no_default_unbound_3.ys
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param_no_default_unbound_4.ys
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param_no_default_unbound_5.ys
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parameters_across_files.ys
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tests: remove -seq 1 from sat with -tempinduct where possible
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2025-09-08 18:04:32 +02:00 |
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past_signedness.ys
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tests: Run async2sync before sat and/or sim to handle $check cells
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2024-02-01 16:14:11 +01:00 |
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port_int_types.sv
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port_int_types.ys
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prefix.sv
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prefix.ys
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tests: Run async2sync before sat and/or sim to handle $check cells
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2024-02-01 16:14:11 +01:00 |
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priority_if_enc.ys
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Add semantic test cases for SystemVerilog priority/unique/unique0 "if".
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2025-05-24 08:44:04 -06:00 |
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roundtrip_proc.ys
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Test roundtripping some processes to Verilog and back
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2024-01-24 16:32:25 +00:00 |
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run-test.sh
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test: restore verific handling, nicer naming
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2024-12-13 10:24:47 +01:00 |
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sbvector.ys
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verific: support single_bit_vector
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2025-05-12 13:23:29 +02:00 |
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sign_array_query.ys
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tests: Run async2sync before sat and/or sim to handle $check cells
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2024-02-01 16:14:11 +01:00 |
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size_cast.sv
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Added cast to type support (#4284)
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2024-09-29 17:03:01 -04:00 |
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size_cast.ys
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tests: Run async2sync before sat and/or sim to handle $check cells
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2024-02-01 16:14:11 +01:00 |
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specify-ifnone.ys
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Add state_dependent_path_declaration so that ifnone can be parsed
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2025-09-09 13:04:52 +02:00 |
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string-literals.ys
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verilog: add support for SystemVerilog string literals.
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2025-07-03 20:51:12 -06:00 |
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struct_access.sv
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struct_access.ys
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tests: Run async2sync before sat and/or sim to handle $check cells
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2024-02-01 16:14:11 +01:00 |
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sva-in-case-expr.ys
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verilog: test cases that look like SVA labels #862
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2025-09-05 12:34:38 +02:00 |
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task_attr.ys
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sv: support assignments within expressions
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2023-09-05 22:27:55 -04:00 |
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typedef_across_files.ys
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tests: remove -seq 1 from sat with -tempinduct where possible
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2025-09-08 18:04:32 +02:00 |
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typedef_const_shadow.sv
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typedef_const_shadow.ys
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typedef_legacy_conflict.ys
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tests: remove -seq 1 from sat with -tempinduct where possible
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2025-09-08 18:04:32 +02:00 |
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unbased_unsized.sv
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unbased_unsized.ys
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tests: remove -seq 1 from sat with -tempinduct where possible
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2025-09-08 18:04:32 +02:00 |
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unbased_unsized_shift.sv
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verilog: Fix const eval of unbased unsized constants
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2023-04-20 12:12:50 +02:00 |
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unbased_unsized_shift.ys
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tests: remove -seq 1 from sat with -tempinduct where possible
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2025-09-08 18:04:32 +02:00 |
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unbased_unsized_tern.sv
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unbased_unsized_tern.ys
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unique0_if_enc.ys
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Add semantic test cases for SystemVerilog priority/unique/unique0 "if".
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2025-05-24 08:44:04 -06:00 |
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unique_if.ys
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Accept (and ignore) SystemVerilog unique/priority if.
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2025-05-22 19:28:28 -06:00 |
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unique_if_else.ys
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Accept (and ignore) SystemVerilog unique/priority if.
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2025-05-22 19:28:28 -06:00 |
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unique_if_else_begin.ys
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Accept (and ignore) SystemVerilog unique/priority if.
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2025-05-22 19:28:28 -06:00 |
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unique_if_enc.ys
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Add semantic test cases for SystemVerilog priority/unique/unique0 "if".
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2025-05-24 08:44:04 -06:00 |
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unique_priority_case.ys
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tests: add cases covering full_case and parallel_case semantics
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2025-05-29 20:45:57 -06:00 |
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unique_priority_if.ys
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tests: add cases covering full_case and parallel_case semantics
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2025-05-29 20:45:57 -06:00 |
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unmatched_else.ys
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unmatched_elsif.ys
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unmatched_endif.ys
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unmatched_endif_2.ys
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unnamed_block.ys
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unnamed_genblk.sv
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unnamed_genblk.ys
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unreachable_case_sign.ys
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tests: Run async2sync before sat and/or sim to handle $check cells
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2024-02-01 16:14:11 +01:00 |
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upto.ys
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void_func.ys
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verilog: Support void functions
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2023-03-20 12:52:46 +01:00 |
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wire_and_var.sv
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wire_and_var.ys
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