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add newline - whitespace

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Rahul Bhagwat 2025-08-06 19:00:11 -04:00
parent f12055d3e0
commit 5cc1365b32
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tests/verilog/package_import_separate.ys
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@ -2,4 +2,4 @@ read_verilog -sv package_import_separate.sv
read_verilog -sv package_import_separate_module.sv
hierarchy -check
proc
opt -full
opt -full