3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-01-24 19:14:07 +00:00
yosys/tests/verilog
..
.gitignore ignore generated file 2025-11-17 13:35:38 +01:00
absurd_width.ys
absurd_width_const.ys
always_comb_latch_1.ys
always_comb_latch_2.ys
always_comb_latch_3.ys sv: auto add nosync to certain always_comb local vars 2022-01-07 22:53:22 -07:00
always_comb_latch_4.ys
always_comb_nolatch_1.ys
always_comb_nolatch_2.ys
always_comb_nolatch_3.ys
always_comb_nolatch_4.ys
always_comb_nolatch_5.ys sv: fix always_comb auto nosync for nested and function blocks 2022-04-05 14:43:48 -06:00
always_comb_nolatch_6.ys sv: fix always_comb auto nosync for nested and function blocks 2022-04-05 14:43:48 -06:00
asgn_expr.sv
asgn_expr.ys
asgn_expr_not_proc_1.ys
asgn_expr_not_proc_2.ys
asgn_expr_not_proc_3.ys sv: support assignments within expressions 2023-09-05 22:27:55 -04:00
asgn_expr_not_proc_4.ys
asgn_expr_not_proc_5.ys
asgn_expr_not_sv_1.ys
asgn_expr_not_sv_2.ys sv: support assignments within expressions 2023-09-05 22:27:55 -04:00
asgn_expr_not_sv_3.ys sv: support assignments within expressions 2023-09-05 22:27:55 -04:00
asgn_expr_not_sv_4.ys
assign_to_reg.ys
atom_type_signedness.ys
block_end_label_only.ys
block_end_label_wrong.ys
block_labels.ys
bug656.v
bug656.ys
bug2037.ys test: add attribute-before-stmt test from @nakengelhardt 2020-05-25 07:36:53 -07:00
bug2042-sv.ys tests: Run async2sync before sat and/or sim to handle $check cells 2024-02-01 16:14:11 +01:00
bug2042.ys tests: update/extend task argument tests 2020-05-13 10:11:45 -07:00
bug2493.ys
bug4785.ys
conflict_assert.ys genrtlil: improve name conflict error messaging 2021-02-26 18:08:23 -05:00
conflict_cell_memory.ys
conflict_interface_port.ys
conflict_memory_wire.ys genrtlil: improve name conflict error messaging 2021-02-26 18:08:23 -05:00
conflict_pwire.ys
conflict_wire_memory.ys genrtlil: improve name conflict error messaging 2021-02-26 18:08:23 -05:00
const_arst.ys add tests 2020-09-28 18:16:08 +02:00
const_sr.ys
constparser_f.ys
constparser_f_file.sv
constparser_f_file.ys const2ast: add diagnostics tests 2025-06-16 21:48:12 +02:00
constparser_g.ys
delay_mintypmax.ys Extend "delay" expressions to handle pair and triplet, i.e. rise, fall and turn-off (#2566) 2021-02-24 15:48:15 -05:00
delay_risefall.ys Extend "delay" expressions to handle pair and triplet, i.e. rise, fall and turn-off (#2566) 2021-02-24 15:48:15 -05:00
delay_time_scale.ys verilog: support for time scale delay values 2022-02-14 15:58:31 +01:00
doubleslash.ys
dynamic_range_lhs.sh
dynamic_range_lhs.v Include x bits in test of lhs dynamic part-select 2024-01-10 20:28:36 +01:00
fcall_smoke.ys simplify: add smoke test for system function calls 2025-08-12 12:59:31 +02:00
for_decl_no_init.ys sv: support declaration in procedural for initialization 2021-08-30 15:19:21 -06:00
for_decl_no_sv.ys
for_decl_shadow.sv
for_decl_shadow.ys
func_arg_mismatch_1.ys
func_arg_mismatch_2.ys
func_arg_mismatch_3.ys
func_arg_mismatch_4.ys
func_task_arg_copying.ys tests: add tests for task/function argument input/output copying 2025-05-31 01:21:06 +01:00
func_tern_hint.sv verilog: fix width/sign detection for functions 2022-05-30 16:45:39 -04:00
func_tern_hint.ys
func_typename_ret.sv
func_typename_ret.ys
func_upto.sv
func_upto.ys tests: Run async2sync before sat and/or sim to handle $check cells 2024-02-01 16:14:11 +01:00
gen_block_end_label_only.ys sv: fix up end label checking 2021-06-16 21:48:05 -04:00
gen_block_end_label_wrong.ys
genblk_case.v
genblk_case.ys
genblk_port_decl.ys
genfor_decl_no_init.ys
genfor_decl_no_sv.ys
genvar_loop_decl_1.sv sv: support declaration in generate for initialization 2021-08-31 12:34:55 -06:00
genvar_loop_decl_1.ys
genvar_loop_decl_2.sv
genvar_loop_decl_2.ys
genvar_loop_decl_3.sv
genvar_loop_decl_3.ys
global_parameter.ys verilog: disallow overriding global parameters 2021-03-11 12:36:51 -05:00
hidden_decl.ys
ifdef_nest.ys
ifdef_unterminated.ys
incdec.ys
include_self.v
include_self.ys
int_types.sv
int_types.ys
local_include.sh
local_include.v
localparam_no_default_1.ys sv: support for parameters without default values 2021-03-02 10:43:53 -05:00
localparam_no_default_2.ys
macro_arg_tromp.sv
macro_arg_tromp.ys
macro_unapplied.ys
macro_unapplied_newline.ys
mem_bounds.sv
mem_bounds.ys
module_end_label.ys
net_types.sv sv: support wand and wor of data types 2021-09-21 14:52:28 -04:00
net_types.ys
package_end_label.ys
package_import_separate.sv
package_import_separate.ys add newline - whitespace 2025-08-06 19:00:11 -04:00
package_import_separate_module.sv use more standard naming conventions 2025-08-06 15:39:30 -04:00
package_import_specific.sv add specific package imports and tests 2025-11-08 23:05:10 +05:30
package_import_specific.ys
package_import_specific_module.sv add specific package imports and tests 2025-11-08 23:05:10 +05:30
package_task_func.sv
package_task_func.ys
param_default.ys
param_int_types.sv
param_int_types.ys sv: extended support for integer types 2021-02-28 16:31:56 -05:00
param_no_default.sv sv: support for parameters without default values 2021-03-02 10:43:53 -05:00
param_no_default.ys
param_no_default_not_svmode.ys
param_no_default_unbound_1.ys sv: support for parameters without default values 2021-03-02 10:43:53 -05:00
param_no_default_unbound_2.ys
param_no_default_unbound_3.ys sv: support for parameters without default values 2021-03-02 10:43:53 -05:00
param_no_default_unbound_4.ys
param_no_default_unbound_5.ys
parameters_across_files.ys
past_signedness.ys
port_int_types.sv verilog: fix sizing of ports with int types in module headers 2021-03-01 13:39:05 -05:00
port_int_types.ys verilog: fix sizing of ports with int types in module headers 2021-03-01 13:39:05 -05:00
prefix.sv verilog: fix multiple AST_PREFIX scope resolution issues 2021-09-21 12:10:59 -04:00
prefix.ys tests: Run async2sync before sat and/or sim to handle $check cells 2024-02-01 16:14:11 +01:00
priority_if_enc.ys
reset_auto_counter.ys
roundtrip_proc.ys
run-test.sh
sbvector.ys verific: support single_bit_vector 2025-05-12 13:23:29 +02:00
sign_array_query.ys
size_cast.sv
size_cast.ys
specify-ifnone.ys Add state_dependent_path_declaration so that ifnone can be parsed 2025-09-09 13:04:52 +02:00
string-literals.ys verilog: add support for SystemVerilog string literals. 2025-07-03 20:51:12 -06:00
struct_access.sv Fix access to whole sub-structs (#3086) 2022-02-14 14:34:20 +01:00
struct_access.ys
sva-in-case-expr.ys verilog: test cases that look like SVA labels #862 2025-09-05 12:34:38 +02:00
task_attr.ys sv: support assignments within expressions 2023-09-05 22:27:55 -04:00
typedef_across_files.ys
typedef_const_shadow.sv
typedef_const_shadow.ys
typedef_legacy_conflict.ys
unbased_unsized.sv
unbased_unsized.ys tests/verilog: Unsized params in cell 2025-11-07 17:13:12 +13:00
unbased_unsized_shift.sv
unbased_unsized_shift.ys
unbased_unsized_tern.sv
unbased_unsized_tern.ys verilog: use derived module info to elaborate cell connections 2021-10-25 18:25:50 -07:00
unique0_if_enc.ys
unique_if.ys Accept (and ignore) SystemVerilog unique/priority if. 2025-05-22 19:28:28 -06:00
unique_if_else.ys
unique_if_else_begin.ys
unique_if_enc.ys Add semantic test cases for SystemVerilog priority/unique/unique0 "if". 2025-05-24 08:44:04 -06:00
unique_priority_case.ys tests: add cases covering full_case and parallel_case semantics 2025-05-29 20:45:57 -06:00
unique_priority_if.ys tests: add cases covering full_case and parallel_case semantics 2025-05-29 20:45:57 -06:00
unmatched_else.ys verilog: fix handling of nested ifdef directives 2021-03-01 12:28:33 -05:00
unmatched_elsif.ys
unmatched_endif.ys verilog: fix handling of nested ifdef directives 2021-03-01 12:28:33 -05:00
unmatched_endif_2.ys
unnamed_block.ys
unnamed_genblk.sv
unnamed_genblk.ys
unreachable_case_sign.ys
upto.ys
void_func.ys verilog: Support void functions 2023-03-20 12:52:46 +01:00
wire_and_var.sv sv: fix support wire and var data type modifiers 2021-01-20 09:16:21 -07:00
wire_and_var.ys