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yosys/tests
Gary Wong e17ed5df88 verilog: add support for SystemVerilog string literals.
Differences are new escape sequences (including escaped newline
continuations and hex escapes) and triple-quoted literals.
2025-07-10 23:28:22 +02:00
..
aiger aiger: add regression test for sliced output segfault 2025-05-09 16:01:47 +02:00
alumacc macc_v2: Add test 2025-01-27 13:19:26 +01:00
arch URAM mapping : Add test for 2048 x 144b 2025-05-10 14:53:56 +02:00
asicworld
bind
blif
bram
cxxrtl Reinstate #4768 2025-04-08 11:58:05 +12:00
errors
fmt
fsm
functional
hana
liberty libcache: fix test 2025-05-09 12:40:38 +02:00
lut
memfile
memlib
memories rtlil: Adjust internal check for $mem_v2 cells 2024-11-08 15:18:43 +01:00
opt tests: add test for #5164 opt_dff -sat UAF 2025-06-06 23:46:23 +01:00
opt_share
peepopt Add muldiv_c peepopt pass 2025-04-30 08:06:59 -07:00
proc tests: add cases covering full_case and parallel_case semantics 2025-05-29 20:45:57 -06:00
realmath
rpc
sat share: Cleanup and additional testing 2025-04-15 12:34:46 +02:00
select design.cc: Fix selections when copying 2025-04-08 16:35:12 +12:00
share
sim fstdata.cc: Fix last step 2025-05-12 13:18:19 +12:00
simple
simple_abc9 Reinstate #4768 2025-04-08 11:58:05 +12:00
smv
sva
svinterfaces
svtypes Tests: Add svtypes/typedef_struct_global.ys 2025-05-26 12:16:58 +12:00
techmap dfflibmap: test negated state next_state with mixed polarities 2025-07-10 18:54:43 +02:00
tools
unit rtlil: Add {from,to}_hdl_index methods to Wire 2025-02-18 17:08:45 +01:00
various Merge pull request #5179 from YosysHQ/krys/assert2cover 2025-07-10 14:53:22 +02:00
verific Merge pull request #5179 from YosysHQ/krys/assert2cover 2025-07-10 14:53:22 +02:00
verilog verilog: add support for SystemVerilog string literals. 2025-07-10 23:28:22 +02:00
vloghtb
xprop
gen-tests-makefile.sh Update gen-tests-makefile.sh 2025-03-27 10:33:51 +13:00