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yosys/frontends/verilog
2024-10-15 08:32:55 -04:00
..
.gitignore Add "make coverage" 2018-08-27 14:22:21 +02:00
const2ast.cc
Makefile.inc
preproc.cc set default_nettype to wire for resetall 2022-08-10 13:28:19 +02:00
preproc.h
verilog_frontend.cc read_verilog: Add missing defaults for flags 2024-05-07 20:25:36 +02:00
verilog_frontend.h
verilog_lexer.l fmt: %t/$time support 2023-08-11 04:46:52 +02:00
verilog_parser.y verilog_parser: silence yynerrs warning 2024-10-15 08:32:55 -04:00