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yosys/techlibs/coolrunner2
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R. Ou 6a0682f5a0 coolrunner2: Separate and improve buffer cell insertion pass 
The new pass will contain all of the logic for inserting "passthrough"
product term and XOR cells as appropriate for the architecture. For
example, this commit fixes connecting an input pin directly to another
output pin with no logic in between.
2020-02-16 20:25:46 -08:00
..
cells_latch.v coolrunner2: Initial mapping of latches 2017-06-25 23:58:28 -07:00
cells_sim.v coolrunner2: Add INVERT parameter to some BUFGs 2017-08-14 12:13:33 -07:00
coolrunner2_fixup.cc coolrunner2: Separate and improve buffer cell insertion pass 2020-02-16 20:25:46 -08:00
coolrunner2_sop.cc coolrunner2: Separate and improve buffer cell insertion pass 2020-02-16 20:25:46 -08:00
Makefile.inc coolrunner2: Separate and improve buffer cell insertion pass 2020-02-16 20:25:46 -08:00
synth_coolrunner2.cc coolrunner2: Separate and improve buffer cell insertion pass 2020-02-16 20:25:46 -08:00
tff_extract.v coolrunner2: Add extraction for TFFs 2018-03-31 02:54:26 -07:00
xc2_dff.lib coolrunner2: Initial mapping of DFFs 2017-06-25 23:58:28 -07:00