mirror of
https://github.com/YosysHQ/yosys
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6a0682f5a0
The new pass will contain all of the logic for inserting "passthrough" product term and XOR cells as appropriate for the architecture. For example, this commit fixes connecting an input pin directly to another output pin with no logic in between.
261 lines
9.2 KiB
C++
261 lines
9.2 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2017 Robert Ou <rqou@robertou.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct Coolrunner2SopPass : public Pass {
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Coolrunner2SopPass() : Pass("coolrunner2_sop", "break $sop cells into ANDTERM/ORTERM cells") { }
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void help() YS_OVERRIDE
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{
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log("\n");
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log(" coolrunner2_sop [options] [selection]\n");
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log("\n");
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log("Break $sop cells into ANDTERM/ORTERM cells.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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log_header(design, "Executing COOLRUNNER2_SOP pass (break $sop cells into ANDTERM/ORTERM cells).\n");
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extra_args(args, 1, design);
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for (auto module : design->selected_modules())
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{
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pool<Cell*> cells_to_remove;
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SigMap sigmap(module);
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// Find all the $_NOT_ cells
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dict<SigBit, tuple<SigBit, Cell*>> not_cells;
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for (auto cell : module->selected_cells())
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{
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if (cell->type == "$_NOT_")
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{
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auto not_input = sigmap(cell->getPort("\\A")[0]);
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auto not_output = sigmap(cell->getPort("\\Y")[0]);
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not_cells[not_input] = tuple<SigBit, Cell*>(not_output, cell);
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}
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}
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// Find wires that need to become special product terms
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dict<SigBit, pool<tuple<Cell*, std::string>>> special_pterms_no_inv;
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dict<SigBit, pool<tuple<Cell*, std::string>>> special_pterms_inv;
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for (auto cell : module->selected_cells())
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{
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if (cell->type.in("\\FDCP", "\\FDCP_N", "\\FDDCP", "\\FTCP", "\\FTCP_N", "\\FTDCP",
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"\\FDCPE", "\\FDCPE_N", "\\FDDCPE", "\\LDCP", "\\LDCP_N"))
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{
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if (cell->hasPort("\\PRE"))
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special_pterms_no_inv[sigmap(cell->getPort("\\PRE")[0])].insert(
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tuple<Cell*, const char *>(cell, "\\PRE"));
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if (cell->hasPort("\\CLR"))
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special_pterms_no_inv[sigmap(cell->getPort("\\CLR")[0])].insert(
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tuple<Cell*, const char *>(cell, "\\CLR"));
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if (cell->hasPort("\\CE"))
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special_pterms_no_inv[sigmap(cell->getPort("\\CE")[0])].insert(
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tuple<Cell*, const char *>(cell, "\\CE"));
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if (cell->hasPort("\\C"))
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special_pterms_inv[sigmap(cell->getPort("\\C")[0])].insert(
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tuple<Cell*, const char *>(cell, "\\C"));
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if (cell->hasPort("\\G"))
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special_pterms_inv[sigmap(cell->getPort("\\G")[0])].insert(
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tuple<Cell*, const char *>(cell, "\\G"));
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}
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}
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// Process $sop cells
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for (auto cell : module->selected_cells())
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{
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if (cell->type == "$sop")
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{
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// Read the inputs/outputs/parameters of the $sop cell
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auto sop_inputs = sigmap(cell->getPort("\\A"));
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auto sop_output = sigmap(cell->getPort("\\Y"))[0];
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auto sop_depth = cell->getParam("\\DEPTH").as_int();
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auto sop_width = cell->getParam("\\WIDTH").as_int();
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auto sop_table = cell->getParam("\\TABLE");
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// Check for a $_NOT_ at the output
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bool has_invert = false;
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if (not_cells.count(sop_output))
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{
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auto not_cell = not_cells.at(sop_output);
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has_invert = true;
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sop_output = std::get<0>(not_cell);
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// remove the $_NOT_ cell because it gets folded into the xor
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cells_to_remove.insert(std::get<1>(not_cell));
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}
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// Check for special P-term usage
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bool is_special_pterm = false;
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bool special_pterm_can_invert = false;
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if (special_pterms_no_inv.count(sop_output) || special_pterms_inv.count(sop_output))
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{
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is_special_pterm = true;
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if (!special_pterms_no_inv[sop_output].size())
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special_pterm_can_invert = true;
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}
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// Construct AND cells
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pool<SigBit> intermed_wires;
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for (int i = 0; i < sop_depth; i++) {
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// Wire for the output
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auto and_out = module->addWire(NEW_ID);
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intermed_wires.insert(and_out);
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// Signals for the inputs
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pool<SigBit> and_in_true;
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pool<SigBit> and_in_comp;
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for (int j = 0; j < sop_width; j++)
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{
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if (sop_table[2 * (i * sop_width + j) + 0])
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{
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and_in_comp.insert(sop_inputs[j]);
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}
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if (sop_table[2 * (i * sop_width + j) + 1])
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{
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and_in_true.insert(sop_inputs[j]);
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}
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}
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// Construct the cell
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auto and_cell = module->addCell(NEW_ID, "\\ANDTERM");
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and_cell->setParam("\\TRUE_INP", GetSize(and_in_true));
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and_cell->setParam("\\COMP_INP", GetSize(and_in_comp));
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and_cell->setPort("\\OUT", and_out);
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and_cell->setPort("\\IN", and_in_true);
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and_cell->setPort("\\IN_B", and_in_comp);
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}
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if (sop_depth == 1)
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{
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// If there is only one term, don't construct an OR cell. Directly construct the XOR gate
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auto xor_cell = module->addCell(NEW_ID, "\\MACROCELL_XOR");
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xor_cell->setParam("\\INVERT_OUT", has_invert);
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xor_cell->setPort("\\IN_PTC", *intermed_wires.begin());
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xor_cell->setPort("\\OUT", sop_output);
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// Special P-term handling
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if (is_special_pterm)
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{
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if (!has_invert || special_pterm_can_invert)
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{
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// Can connect the P-term directly to the special term sinks
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for (auto x : special_pterms_inv[sop_output])
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std::get<0>(x)->setPort(std::get<1>(x), *intermed_wires.begin());
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for (auto x : special_pterms_no_inv[sop_output])
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std::get<0>(x)->setPort(std::get<1>(x), *intermed_wires.begin());
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}
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if (has_invert)
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{
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if (special_pterm_can_invert)
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{
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log_assert(special_pterms_no_inv[sop_output].size() == 0);
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for (auto x : special_pterms_inv[sop_output])
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{
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auto cell = std::get<0>(x);
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// Need to invert the polarity of the cell
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if (cell->type == "\\FDCP") cell->type = "\\FDCP_N";
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else if (cell->type == "\\FDCP_N") cell->type = "\\FDCP";
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else if (cell->type == "\\FTCP") cell->type = "\\FTCP_N";
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else if (cell->type == "\\FTCP_N") cell->type = "\\FTCP";
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else if (cell->type == "\\FDCPE") cell->type = "\\FDCPE_N";
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else if (cell->type == "\\FDCPE_N") cell->type = "\\FDCPE";
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else if (cell->type == "\\LDCP") cell->type = "\\LDCP_N";
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else if (cell->type == "\\LDCP_N") cell->type = "\\LDCP";
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else log_assert(!"Internal error! Bad cell type!");
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}
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}
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else
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{
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// Need to construct a feed-through term
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auto feedthrough_out = module->addWire(NEW_ID);
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auto feedthrough_cell = module->addCell(NEW_ID, "\\ANDTERM");
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feedthrough_cell->setParam("\\TRUE_INP", 1);
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feedthrough_cell->setParam("\\COMP_INP", 0);
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feedthrough_cell->setPort("\\OUT", feedthrough_out);
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feedthrough_cell->setPort("\\IN", sop_output);
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feedthrough_cell->setPort("\\IN_B", SigSpec());
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for (auto x : special_pterms_inv[sop_output])
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std::get<0>(x)->setPort(std::get<1>(x), feedthrough_out);
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for (auto x : special_pterms_no_inv[sop_output])
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std::get<0>(x)->setPort(std::get<1>(x), feedthrough_out);
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}
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}
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}
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}
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else
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{
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// Wire from OR to XOR
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auto or_to_xor_wire = module->addWire(NEW_ID);
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// Construct the OR cell
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auto or_cell = module->addCell(NEW_ID, "\\ORTERM");
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or_cell->setParam("\\WIDTH", sop_depth);
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or_cell->setPort("\\IN", intermed_wires);
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or_cell->setPort("\\OUT", or_to_xor_wire);
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// Construct the XOR cell
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auto xor_cell = module->addCell(NEW_ID, "\\MACROCELL_XOR");
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xor_cell->setParam("\\INVERT_OUT", has_invert);
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xor_cell->setPort("\\IN_ORTERM", or_to_xor_wire);
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xor_cell->setPort("\\OUT", sop_output);
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if (is_special_pterm)
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{
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// Need to construct a feed-through term
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auto feedthrough_out = module->addWire(NEW_ID);
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auto feedthrough_cell = module->addCell(NEW_ID, "\\ANDTERM");
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feedthrough_cell->setParam("\\TRUE_INP", 1);
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feedthrough_cell->setParam("\\COMP_INP", 0);
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feedthrough_cell->setPort("\\OUT", feedthrough_out);
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feedthrough_cell->setPort("\\IN", sop_output);
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feedthrough_cell->setPort("\\IN_B", SigSpec());
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for (auto x : special_pterms_inv[sop_output])
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std::get<0>(x)->setPort(std::get<1>(x), feedthrough_out);
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for (auto x : special_pterms_no_inv[sop_output])
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std::get<0>(x)->setPort(std::get<1>(x), feedthrough_out);
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}
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}
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// Finally, remove the $sop cell
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cells_to_remove.insert(cell);
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}
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}
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// Actually do the removal now that we aren't iterating
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for (auto cell : cells_to_remove)
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{
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module->remove(cell);
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}
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}
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}
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} Coolrunner2SopPass;
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PRIVATE_NAMESPACE_END
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