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yosys/techlibs
R. Ou 6a0682f5a0 coolrunner2: Separate and improve buffer cell insertion pass
The new pass will contain all of the logic for inserting "passthrough"
product term and XOR cells as appropriate for the architecture. For
example, this commit fixes connecting an input pin directly to another
output pin with no logic in between.
2020-02-16 20:25:46 -08:00
..
achronix Remove executable flag from files 2020-02-15 10:36:44 +01:00
anlogic synth_*: call 'opt -fast' after 'techmap' 2020-02-05 18:39:01 -08:00
common techmap: fix shiftx2mux decomposition 2020-02-07 11:02:48 -08:00
coolrunner2 coolrunner2: Separate and improve buffer cell insertion pass 2020-02-16 20:25:46 -08:00
easic Update doc that "-retime" calls abc with "-dff -D 1" 2019-12-30 13:28:29 -08:00
ecp5 synth_*: call 'opt -fast' after 'techmap' 2020-02-05 18:39:01 -08:00
efinix synth_*: call 'opt -fast' after 'techmap' 2020-02-05 18:39:01 -08:00
gowin Removing cells_sim.v from bram techmap pass 2020-02-06 14:38:29 -06:00
greenpak4 synth_*: call 'opt -fast' after 'techmap' 2020-02-05 18:39:01 -08:00
ice40 synth_*: call 'opt -fast' after 'techmap' 2020-02-05 18:39:01 -08:00
intel Add log_experimental() and experimental() API and "yosys -x" 2020-01-27 18:27:47 +01:00
sf2 synth_*: call 'opt -fast' after 'techmap' 2020-02-05 18:39:01 -08:00
xilinx abc9: deprecate abc9_ff.init wire for (* abc9_init *) attr 2020-02-13 12:33:58 -08:00
.gitignore added .gitignore files 2013-01-05 11:19:11 +01:00