Zachary Snow 2e697f5655 verilog: check for module scope identifiers during width detection ... The recent fix for case expression width detection causes the width of the expressions to be queried before they are simplified. Because the logic supporting module scope identifiers only existed in simplify, looking them up would fail during width detection. This moves the logic to a common helper used in both simplify() and detectSignWidthWorker().		2021-06-08 15:03:16 -04:00
..
.gitignore	added more .gitignore files (make test)	2013-01-05 11:35:52 +01:00
aes_kexp128.v	initial import	2013-01-05 11:13:26 +01:00
always01.v	Added test cases from 2012 paper on comparison of foss verilog synthesis tools	2013-03-31 11:17:56 +02:00
always02.v	Added test cases from 2012 paper on comparison of foss verilog synthesis tools	2013-03-31 11:17:56 +02:00
always03.v	Added test cases from 2012 paper on comparison of foss verilog synthesis tools	2013-03-31 11:17:56 +02:00
arraycells.v	Fixed typo in tests/simple/arraycells.v	2017-01-04 12:39:01 +01:00
arrays01.v	Added test cases from 2012 paper on comparison of foss verilog synthesis tools	2013-03-31 11:17:56 +02:00
arrays02.sv	Add proper test for SV-style arrays	2019-06-20 12:06:07 +02:00
asgn_binop.sv	sv: support remaining assignment operators	2021-05-25 16:15:57 -04:00
attrib01_module.v	Added tests for attributes	2019-06-03 09:25:20 +02:00
attrib02_port_decl.v	Added tests for attributes	2019-06-03 09:25:20 +02:00
attrib03_parameter.v	Added tests for attributes	2019-06-03 09:25:20 +02:00
attrib04_net_var.v	Added tests for attributes	2019-06-03 09:25:20 +02:00
attrib05_port_conn.v.DISABLED	Added tests for attributes	2019-06-03 09:25:20 +02:00
attrib06_operator_suffix.v	Added tests for attributes	2019-06-03 09:25:20 +02:00
attrib07_func_call.v.DISABLED	Added tests for attributes	2019-06-03 09:25:20 +02:00
attrib08_mod_inst.v	Added tests for attributes	2019-06-03 09:25:20 +02:00
attrib09_case.v	Added tests for attributes	2019-06-03 09:25:20 +02:00
carryadd.v	Bugfix in name resolution with generate blocks	2014-01-30 15:01:28 +01:00
case_expr_const.v	verilog: fix case expression sign and width handling	2021-05-25 16:16:46 -04:00
case_expr_non_const.v	verilog: fix case expression sign and width handling	2021-05-25 16:16:46 -04:00
const_branch_finish.v	Fix begin/end in generate	2020-11-11 12:03:37 +09:00
const_fold_func.v	verilog: refactored constant function evaluation	2021-02-04 10:18:27 -05:00
const_func_shadow.v	verilog: refactored constant function evaluation	2021-02-04 10:18:27 -05:00
constmuldivmod.v	Expand tests/simple/constmuldivmod.v	2020-05-28 22:59:04 +02:00
constpower.v	Fixed handling of power operator	2013-11-07 22:20:00 +01:00
defvalue.sv	Add defvalue test, minor autotest fixes for .sv files	2019-06-19 12:12:08 +02:00
dff_different_styles.v	Another block of spelling fixes	2015-08-14 23:27:05 +02:00
dff_init.v	Add test case from #997	2019-05-07 19:58:04 +02:00
dynslice.v	Add dynamic slicing Verilog testcase	2020-03-31 11:51:31 -07:00
fiedler-cooley.v	initial import	2013-01-05 11:13:26 +01:00
forgen01.v	Progress in Verific bindings	2014-03-17 01:56:00 +01:00
forgen02.v	Added test cases from 2012 paper on comparison of foss verilog synthesis tools	2013-03-31 11:17:56 +02:00
forloops.v	Add additional test cases for for-loops	2019-05-01 09:32:07 +02:00
fsm.v	Renamed some of the test cases in tests/simple to avoid name collisions	2014-07-25 13:01:45 +02:00
func_block.v	verilog: significant block scoping improvements	2021-01-31 09:42:09 -05:00
func_recurse.v	verilog: significant block scoping improvements	2021-01-31 09:42:09 -05:00
func_width_scope.v	verilog: significant block scoping improvements	2021-01-31 09:42:09 -05:00
genblk_collide.v	verilog: significant block scoping improvements	2021-01-31 09:42:09 -05:00
genblk_dive.v	verilog: significant block scoping improvements	2021-01-31 09:42:09 -05:00
genblk_order.v	verilog: significant block scoping improvements	2021-01-31 09:42:09 -05:00
genblk_port_shadow.v	verlog: allow shadowing module ports within generate blocks	2021-02-07 11:48:39 -05:00
generate.v	Merge pull request #2529 from zachjs/unnamed-genblk	2021-02-04 09:57:28 +00:00
graphtest.v	Squelch trailing whitespace	2017-04-12 15:11:09 +02:00
hierarchy.v	Another block of spelling fixes	2015-08-14 23:27:05 +02:00
hierdefparam.v	Fix handling of defparam for when default_nettype is none	2019-02-24 20:09:41 +01:00
i2c_master_tests.v	Renamed some of the test cases in tests/simple to avoid name collisions	2014-07-25 13:01:45 +02:00
ifdef_1.v	verilog: fix handling of nested ifdef directives	2021-03-01 12:28:33 -05:00
ifdef_2.v	verilog: fix handling of nested ifdef directives	2021-03-01 12:28:33 -05:00
implicit_ports.v	Rename implicit_ports.sv test to implicit_ports.v	2019-06-07 13:12:25 +02:00
local_loop_var.sv	verilog: significant block scoping improvements	2021-01-31 09:42:09 -05:00
localparam_attr.v	Added tests for Verilog frontent for attributes on parameters and localparams	2019-05-16 12:53:43 +02:00
loop_var_shadow.v	verilog: significant block scoping improvements	2021-01-31 09:42:09 -05:00
loops.v	Fixed trailing whitespaces	2015-07-02 11:14:30 +02:00
macro_arg_spaces.sv	verilog: allow spaces in macro arguments	2021-01-20 08:49:58 -07:00
macro_arg_surrounding_spaces.v	verilog: strip leading and trailing spaces in macro args	2021-01-28 11:26:35 -05:00
macros.v	Renamed some of the test cases in tests/simple to avoid name collisions	2014-07-25 13:01:45 +02:00
mem2reg.v	Add splitcmplxassign test case and silence splitcmplxassign warning	2019-05-01 10:01:54 +02:00
mem2reg_bounds_tern.v	mem2reg: tolerate out of bounds constant accesses	2021-06-08 15:02:57 -04:00
mem_arst.v	Make SV2017 compliant courtesy of @wsnyder	2019-12-12 07:34:07 -08:00
memory.v	Fixed bug with memories that do not have a down-to-zero data width	2016-08-22 14:27:46 +02:00
module_scope.v	verilog: support module scope identifiers in parametric modules	2021-03-16 11:01:30 -04:00
module_scope_case.v	verilog: check for module scope identifiers during width detection	2021-06-08 15:03:16 -04:00
multiplier.v	Added multiplier test case from eda playground	2013-12-18 13:43:53 +01:00
muxtree.v	improvements in muxtree/select_leaves test	2015-01-18 13:24:01 +01:00
named_genblk.v	verilog: significant block scoping improvements	2021-01-31 09:42:09 -05:00
nested_genblk_resolve.v	verilog: significant block scoping improvements	2021-01-31 09:42:09 -05:00
omsp_dbg_uart.v	Fixed trailing whitespaces	2015-07-02 11:14:30 +02:00
operators.v	Renamed some of the test cases in tests/simple to avoid name collisions	2014-07-25 13:01:45 +02:00
param_attr.v	Added tests for Verilog frontent for attributes on parameters and localparams	2019-05-16 12:53:43 +02:00
paramods.v	Renamed some of the test cases in tests/simple to avoid name collisions	2014-07-25 13:01:45 +02:00
partsel.v	Bugfix in partsel.v signed indices test cases	2020-05-02 11:21:01 +02:00
process.v	Fixed a bug in AST frontend for cases with non-blocking assigned variables as case values	2013-04-13 21:19:10 +02:00
realexpr.v	Add test case for real parameters	2019-08-20 11:38:21 +02:00
repwhile.v	Renamed some of the test cases in tests/simple to avoid name collisions	2014-07-25 13:01:45 +02:00
retime.v	Add retime test	2019-04-05 16:28:46 -07:00
rotate.v	Another block of spelling fixes	2015-08-14 23:27:05 +02:00
run-test.sh	tests/simple: remove "nullglob" shopt	2020-09-21 15:07:02 +02:00
scopes.v	Improved scope resolution of local regs in Verilog+AST frontend	2014-08-05 12:15:53 +02:00
signedexpr.v	Renamed some of the test cases in tests/simple to avoid name collisions	2014-07-25 13:01:45 +02:00
sincos.v	Fix in sincos testbench gen	2013-12-04 09:24:52 +01:00
specify.v	Fix tests/simple/specify.v	2018-03-27 14:34:00 +02:00
string_format.v	Allow %0s $display format specifier	2020-08-09 17:19:49 -04:00
subbytes.v	initial import	2013-01-05 11:13:26 +01:00
task_func.v	Fix handling of task output ports in clocked always blocks, fixes #857	2019-03-07 22:44:37 -08:00
undef_eqx_nex.v	Renamed some of the test cases in tests/simple to avoid name collisions	2014-07-25 13:01:45 +02:00
unnamed_block_decl.sv	verilog: significant block scoping improvements	2021-01-31 09:42:09 -05:00
usb_phy_tests.v	Renamed some of the test cases in tests/simple to avoid name collisions	2014-07-25 13:01:45 +02:00
values.v	Replaced RTLIL::Const::str with generic decoder method	2013-12-04 14:14:05 +01:00
verilog_primitives.v	verilog: fix buf/not primitives with multiple outputs	2021-03-17 11:44:03 -04:00
vloghammer.v	Another block of spelling fixes	2015-08-14 23:27:05 +02:00
wandwor.v	Add actual wandwor test that is part of "make test"	2019-05-28 16:42:50 +02:00
wreduce.v	Improvements in wreduce	2015-10-31 13:39:30 +01:00
xfirrtl	Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences.	2019-07-31 09:27:38 -07:00